diff options
Diffstat (limited to 'testsuite/vests/vhdl-ams/ashenden/compliant/generics')
14 files changed, 789 insertions, 0 deletions
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generics/control_unit.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/control_unit.vhd new file mode 100644 index 000000000..1fda52aaf --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/control_unit.vhd @@ -0,0 +1,39 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- code from book + +entity control_unit is + + generic ( Tpd_clk_out, Tpw_clk : delay_length; + debug : boolean := false ); + + port ( clk : in bit; + ready : in bit; + control1, control2 : out bit ); + +end entity control_unit; + +-- end code from book + + + +architecture test of control_unit is +begin +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generics/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/index-ams.txt new file mode 100644 index 000000000..7be1d3678 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/index-ams.txt @@ -0,0 +1,23 @@ +--------------------------------------------------------------------------------------------------------------------------------------------- +-- Chapter 9 - Generic Constants +--------------------------------------------------------------------------------------------------------------------------------------------- +-- Filename Primary Unit Secondary Unit Figure/Section +----------- ------------ -------------- -------------- +control_unit.vhd entity control_unit test Figure 12-1 +timer.vhd entity timer behavioral Figure 12-2 +reg.vhd entity reg behavioral Figure 12-3 +multiple_opamp.vhd entity multiple_opamp ideal Figure 12-4 +inline_01.vhd entity inline_01 test Section 12.1 +inline_02a.vhd entity resistor simple Section 12.1 +inline_03.vhd entity inline_03 test Section 12.1 +inline_05a.vhd entity inline_05a test Section 12.1 +inline_06.vhd entity inline_06 test Section 12.2 +inline_07.vhd entity inline_07 test Section 12.2 +inline_08.vhd entity inline_08 test Section 12.2 +inline_09a.vhd entity inline_09a test Section 12.2 +--------------------------------------------------------------------------------------------------------------------------------------------- +-- TestBenches +--------------------------------------------------------------------------------------------------------------------------------------------- +-- Filename Primary Unit Secondary Unit Tested Model +------------ ------------ -------------- ------------ +tb_timer_w_stim.vhd entity tb_timer_w_stim TB_timer_w_stim timer.vhd diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_01.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_01.vhd new file mode 100644 index 000000000..b3ae86af1 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_01.vhd @@ -0,0 +1,73 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- code from book + +entity and2 is + generic ( Tpd : time ); + port ( a, b : in bit; y : out bit ); +end entity and2; + + +architecture simple of and2 is +begin + + and2_function : + y <= a and b after Tpd; + +end architecture simple; + +-- end code from book + + +entity inline_01 is + +end entity inline_01; + + +---------------------------------------------------------------- + + +library util; use util.stimulus_generators.all; + +architecture test of inline_01 is + + signal a1, b1, sig1, sig2, sig_out : bit; + signal test_vector : bit_vector(1 to 3); + +begin + + -- code from book + + gate1 : entity work.and2(simple) + generic map ( Tpd => 2 ns ) + port map ( a => sig1, b => sig2, y => sig_out ); + + gate2 : entity work.and2(simple) + generic map ( Tpd => 3 ns ) + port map ( a => a1, b => b1, y => sig1 ); + + -- end code from book + + stimulus : all_possible_values ( bv => test_vector, + delay_between_values => 10 ns ); + + (sig2, a1, b1) <= test_vector; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_02a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_02a.vhd new file mode 100644 index 000000000..fa207c9b0 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_02a.vhd @@ -0,0 +1,35 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +-- code from book + +entity resistor is + generic ( resistance : real ); + port ( terminal pos, neg : electrical ); +end entity resistor; + +architecture simple of resistor is + quantity v across i through pos to neg; +begin + v == i * resistance; +end architecture simple; + +-- end code from book diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_03.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_03.vhd new file mode 100644 index 000000000..a86e7af51 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_03.vhd @@ -0,0 +1,49 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_03 is +end entity inline_03; + + + +architecture test of inline_03 is + + signal clk, ready : bit; + +begin + + dut1 : entity work.control_unit + -- code from book (in text) + generic map ( 200 ps, 1500 ps, false ) + -- end code from book + port map ( clk, ready, open, open ); + + dut2 : entity work.control_unit + -- code from book (in text) + generic map ( Tpd_clk_out => 200 ps, Tpw_clk => 1500 ps ) + -- end code from book + port map ( clk, ready, open, open ); + + dut3 : entity work.control_unit + -- code from book (in text) + generic map ( 200 ps, 1500 ps, debug => open ) + -- end code from book + port map ( clk, ready, open, open ); + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_05a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_05a.vhd new file mode 100644 index 000000000..54ac662bb --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_05a.vhd @@ -0,0 +1,46 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee; use ieee.std_logic_1164.all; +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity inline_05a is +end entity inline_05a; + + + +architecture test of inline_05a is + + signal start_n, reset, time_out : std_ulogic; + terminal interval_rc : electrical; + +begin + + -- code from book (in text) + + interval_timer : entity work.timer(behavioral) + generic map ( threshold => 2.5, + clamp_on_resistance => 0.01, + clamp_off_resistance => 10.0E+6 ) + port map ( trigger_n => start_n, reset => reset, q => time_out, + rc_ext => interval_rc ); + + -- end code from book + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_06.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_06.vhd new file mode 100644 index 000000000..baf7405e7 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_06.vhd @@ -0,0 +1,70 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- code from book + +entity reg is + port ( d : in bit_vector; q : out bit_vector; -- . . . ); + -- not in book + other_port : in bit := '0' ); + -- end not in book +end entity reg; + +-- end code from book + + +architecture test of reg is +begin + q <= d; +end architecture test; + + + +entity inline_06 is + +end entity inline_06; + + +---------------------------------------------------------------- + + +architecture test of inline_06 is + + -- code from book + + signal small_data : bit_vector(0 to 7); + signal large_data : bit_vector(0 to 15); + -- . . . + + -- end code from book + + +begin + + -- code from book + + problem_reg : entity work.reg + port map ( d => small_data, q => large_data, -- . . . ); + -- not in book + other_port => open ); + -- end not in book + + -- end code from book + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_07.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_07.vhd new file mode 100644 index 000000000..c59b06cd1 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_07.vhd @@ -0,0 +1,75 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- code from book + +entity reg is + generic ( width : positive ); + port ( d : in bit_vector(0 to width - 1); + q : out bit_vector(0 to width - 1); + -- . . . ); + -- not in book + other_port : in bit := '0' ); + -- end not in book +end entity reg; + +-- end code from book + + +architecture test of reg is +begin + q <= d; +end architecture test; + + + +entity inline_07 is + +end entity inline_07; + + +---------------------------------------------------------------- + + +architecture test of inline_07 is + + constant bus_size : positive := 16; + + -- code from book + + signal in_data, out_data : bit_vector(0 to bus_size - 1); + -- . . . + + -- end code from book + + +begin + + -- code from book + + ok_reg : entity work.reg + generic map ( width => bus_size ) + port map ( d => in_data, q => out_data, -- . . . ); + -- not in book + other_port => open ); + -- end not in book + + -- end code from book + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_08.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_08.vhd new file mode 100644 index 000000000..b1fea6421 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_08.vhd @@ -0,0 +1,69 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_08 is +end entity inline_08; + + +architecture test of inline_08 is + + -- code from book + + subtype state_vector is bit_vector(1 to 5); + + -- end code from book + + signal clk, reset : bit := '0'; + signal word_in, word_out : bit_vector(0 to 31); + signal state_in, state_out : state_vector; + +begin + + -- code from book + + word_reg : entity work.reg(behavioral) + generic map ( width => 32 ) + port map ( -- . . . ); + -- not in book + d => word_in, q => word_out, clk => clk, reset => reset ); + -- end not in book + + state_reg : entity work.reg(behavioral) + generic map ( width => state_vector'length ) + port map ( -- . . . ); + -- not in book + d => state_in, q => state_out, clk => clk, reset => reset ); + + -- end code from book + + clk_gen : clk <= '1' after 10 ns, '0' after 20 ns when clk = '0'; + + reset_gen : reset <= '1' after 80 ns, '0' after 105 ns; + + stimulus_word : word_in <= X"11111111" after 25 ns, + X"22222222" after 65 ns, + X"33333333" after 85 ns, + X"44444444" after 125 ns; + + stimulus_state : state_in <= "00001" after 25 ns, + "00010" after 65 ns, + "00011" after 85 ns, + "00100" after 125 ns; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_09a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_09a.vhd new file mode 100644 index 000000000..3ef59fb28 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_09a.vhd @@ -0,0 +1,49 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity inline_09a is + +end entity inline_09a; + + +architecture test of inline_09a is + + -- code from book + + constant num_sensors : positive := 8; + terminal sensors_raw, + sensors_buffered : electrical_vector(num_sensors - 1 downto 0); + -- ... + + -- end code from book + +begin + + -- code from book + + buf_amps : entity work.multiple_opamp(ideal) + generic map ( size => num_sensors, + gains => real_vector'(num_sensors - 1 downto 0 => 1.0) ) + port map ( sensors_raw, sensors_buffered ); + + -- end code from book + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generics/multiple_opamp.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/multiple_opamp.vhd new file mode 100644 index 000000000..ff3167bd5 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/multiple_opamp.vhd @@ -0,0 +1,48 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity multiple_opamp is + generic ( size : positive; + gains : real_vector ); + port ( terminal inputs, outputs : electrical_vector(1 to size) ); +end entity multiple_opamp; + +---------------------------------------------------------------- + +architecture ideal of multiple_opamp is + + quantity v_in across i_in through inputs to electrical_ref; + quantity v_out across outputs to electrical_ref; + alias gains_alias : real_vector(1 to size) is gains; + +begin + + assert gains'length = size + report "gains vector size differs from input/output size"; + + amplify : procedural is + begin + for index in 1 to size loop + v_out(index) := v_in(index) * gains_alias(index); + end loop; + end procedural amplify; + +end architecture ideal; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generics/reg.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/reg.vhd new file mode 100644 index 000000000..181064e41 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/reg.vhd @@ -0,0 +1,42 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity reg is + generic ( width : positive ); + port ( d : in bit_vector(0 to width - 1); + q : out bit_vector(0 to width - 1); + clk, reset : in bit ); +end entity reg; + +-------------------------------------------------- + +architecture behavioral of reg is +begin + + behavior : process (clk, reset) is + constant zero : bit_vector(0 to width - 1) := (others => '0'); + begin + if reset = '1' then + q <= zero; + elsif clk'event and clk = '1' then + q <= d; + end if; + end process behavior; + +end architecture behavioral; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generics/tb_timer_w_stim.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/tb_timer_w_stim.vhd new file mode 100644 index 000000000..21d4b38a0 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/tb_timer_w_stim.vhd @@ -0,0 +1,115 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library IEEE_proposed; use IEEE_proposed.electrical_systems.all; +library IEEE; use IEEE.std_logic_1164.all; + +entity tb_timer_w_stim is + +end tb_timer_w_stim; + +architecture TB_timer_w_stim of tb_timer_w_stim is + -- Component declarations + -- Signal declarations + terminal in_src, rc_ext : electrical; + signal trig, rst : std_ulogic; + signal tim_out : std_ulogic; +begin + -- Signal assignments + -- Component instances + vio : entity work.v_constant(ideal) + generic map( + level => 5.0 + ) + port map( + pos => in_src, + neg => ELECTRICAL_REF + ); + R1 : entity work.resistor(simple) + generic map( + resistance => 10.0e3 + ) + port map( + pos => in_src, + neg => rc_ext + ); + C1 : entity work.capacitor(ideal) + generic map( + cap => 10.0e-6 + ) + port map( + p1 => rc_ext, + p2 => electrical_ref + ); + timer1 : entity work.timer(behavioral) + generic map( + threshold => 2.0, + clamp_on_resistance => 1.0e-3, + clamp_off_resistance => 1.0e6 + ) + port map( + trigger_n => trig, + reset => rst, + q => tim_out, + rc_ext => rc_ext + ); + -- rst + P_rst : + process + begin + + wait for 0.000 ns; rst <= '1'; + + wait for 1.000 ms; rst <= '0'; + + wait for 100.000 ms; rst <= '1'; + + wait for 1.000 ms; rst <= '0'; + + wait; + end process; + + -- trig + P_trig : + process + begin + wait for 0.0 ns; trig <= '0'; + + wait for 5.000 ms; trig <= '1'; + + wait for 1.0 ms; trig <= '0'; + + wait for 1.0 ms; trig <= '1'; + + wait for 40.0 ms; trig <= '1'; + + wait for 1.0 ms; trig <= '0'; + + wait for 1.0 ms; trig <= '1'; + + wait for 40.0 ms; trig <= '1'; + + wait for 1.0 ms; trig <= '0'; + + wait for 1.0 ms; trig <= '1'; + wait; + end process; +end TB_timer_w_stim; + + diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generics/timer.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/timer.vhd new file mode 100644 index 000000000..793a9e504 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/timer.vhd @@ -0,0 +1,56 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee; use ieee.std_logic_1164.all; +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity timer is + generic ( threshold : real; + clamp_on_resistance, clamp_off_resistance : real ); + port ( signal trigger_n, reset : in std_ulogic; signal q : out std_ulogic; + terminal rc_ext : electrical ); +end entity timer; + +---------------------------------------------------------------- + +architecture behavioral of timer is + + quantity v_rc_ext across i_clamp through rc_ext to electrical_ref; + signal q_n : std_ulogic := '1'; + +begin + + if q_n = '1' use + i_clamp == v_rc_ext / clamp_on_resistance; + else + i_clamp == v_rc_ext / clamp_off_resistance; + end use; + + timer_state : process ( trigger_n, reset, v_rc_ext'above(threshold) ) is + begin + if reset = '1' or reset = 'H' or v_rc_ext > threshold then + q <= '0'; q_n <= '1'; + elsif trigger_n = '0' or trigger_n = 'L' then + q <= '1'; q_n <= '0'; + end if; + end process timer_state; + + break on q_n; + +end architecture behavioral; |