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Diffstat (limited to 'testsuite/vests/vhdl-ams/ashenden/compliant/fundamental')
9 files changed, 427 insertions, 0 deletions
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/adc.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/adc.vhd new file mode 100644 index 000000000..089ea0dda --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/adc.vhd @@ -0,0 +1,80 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity adc is + port ( quantity gain : in voltage; + terminal a : electrical; + signal clk : in bit; + signal d_out : out bit ); +end entity adc; + +architecture ideal of adc is + + constant ref : real := 5.0; + quantity v_in across a; + quantity v_amplified : voltage; + +begin + + v_amplified == v_in * gain; + + adc_behavior: process is + variable stored_d : bit; + begin + if clk = '1' then + if v_amplified > ref / 2.0 then + stored_d := '1'; + else + stored_d := '0'; + end if; + end if; + d_out <= stored_d after 5 ns; + wait on clk; + end process adc_behavior; + +end architecture ideal; + +architecture struct of adc is + + terminal a_amplified, ref, half_ref: electrical; + quantity v_ref across i_ref through ref; + signal d : bit; + +begin + + res1 : entity work.resistor(ideal) + port map ( ref, half_ref); + + res2 : entity work.resistor(ideal) + port map ( half_ref, electrical_ref ); + + amp : entity work.vc_amp(ideal) + port map ( gain, a, a_amplified ); + + comp : entity work.comparator(ideal) + port map ( a_amplified, half_ref, d); + + ff : entity work.d_ff(basic) + port map ( d, clk, d_out ); + + v_ref == 5.0; + +end architecture struct; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/comparator.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/comparator.vhd new file mode 100644 index 000000000..7c3bb4d46 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/comparator.vhd @@ -0,0 +1,41 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity comparator is + port ( terminal plus, minus : electrical; + signal value : out bit ); +end entity comparator; + +architecture ideal of comparator is + quantity diff across plus to minus; +begin + + comp_behavior: process is + begin + if diff > 0.0 then + value <= '1' after 5 ns; + else + value <= '0' after 5 ns; + end if; + wait on diff'above(0.0); + end process comp_behavior; + +end architecture ideal; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/d_ff.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/d_ff.vhd new file mode 100644 index 000000000..b586f69ab --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/d_ff.vhd @@ -0,0 +1,35 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity d_ff is + port ( d, clk : in bit; q : out bit ); +end d_ff; + +architecture basic of d_ff is +begin + + ff_behavior : process is + begin + if clk = '1' then + q <= d after 2 ns; + end if; + wait on clk; + end process ff_behavior; + +end architecture basic; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/index-ams.txt new file mode 100644 index 000000000..d4fed24a7 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/index-ams.txt @@ -0,0 +1,18 @@ +--------------------------------------------------------------------------------------------------------------------------------------------- +-- Chapter 1 - Fundamental Concepts +--------------------------------------------------------------------------------------------------------------------------------------------- +-- Filename Primary Unit Secondary Unit Figure/Section +----------- ------------ -------------- -------------- +adc.vhd entity adc ideal, struct Figures 1-13, 1-14, 1-17 +resistor.vhd entity resistor ideal Figure 1-16 +vc_amp.vhd entity vc_amp ideal Figure 1-16 +comparator.vhd entity comparator ideal Figure 1-16 +d_ff.vhd entity d_ff basic Figure 1-16 +propulsion.vhd entity propulsion mixed Figure 1-18 +test_bench-1.vhd entity test_bench example Figure 1-19 +--------------------------------------------------------------------------------------------------------------------------------------------- +-- TestBenches +--------------------------------------------------------------------------------------------------------------------------------------------- +-- Filename Primary Unit Secondary Unit Tested Model +------------ ------------ -------------- ------------ +tb_adc.vhd entity tb_adc tb_adc adc.vhd diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/propulsion.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/propulsion.vhd new file mode 100644 index 000000000..a96bb0dfc --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/propulsion.vhd @@ -0,0 +1,60 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; +use ieee_proposed.mechanical_systems.all; +use ieee_proposed.electrical_systems.all; + +entity propulsion is + port ( signal clk, reset : in bit; -- control inputs + signal rpm : in natural; -- requested rpm + signal forward : in bit ); -- requested direction +end entity propulsion; + +architecture mixed of propulsion is + terminal p1, p2 : electrical; + terminal shaft1, shaft2, shaft3 : rotational_v; + signal forward_gear : bit; + -- ... +begin + + motor : entity work.dc_motor(ideal) + port map ( p1, p2, shaft1 ); + + gear : entity work.gear_av(ideal) + port map ( forward_gear, shaft1, shaft2 ); + + intertia : entity work.inertia_av(ideal) + port map ( shaft2, shaft3 ); + + prop : entity work.propeller(ideal) + port map ( shaft3 ); + + control_section : process is + -- variable declarations for control_section to control voltage inputs + -- and gear shifting + -- ... + begin + -- ... + wait on clk, reset; + end process control_section; + + -- ... + +end architecture mixed; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/resistor.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/resistor.vhd new file mode 100644 index 000000000..5f492f448 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/resistor.vhd @@ -0,0 +1,32 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity resistor is + port ( terminal p1, p2 : electrical ); +end entity resistor ; + +architecture ideal of resistor is + quantity v across i through p1 to p2; + constant resistance : real := 10000.0; +begin + v == i * resistance; +end architecture ideal; + diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/tb_adc.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/tb_adc.vhd new file mode 100644 index 000000000..ef2517f02 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/tb_adc.vhd @@ -0,0 +1,78 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library IEEE; use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; + +library IEEE_proposed; use IEEE_proposed.electrical_systems.all; + +entity tb_adc is +end tb_adc; + +architecture tb_adc of tb_adc is + -- Component declarations + -- Signal declarations + signal clk_in : bit; + signal clk_in_tmp : std_logic; + signal dig_out1, dig_out2 : bit; + terminal sine_in : electrical; + quantity gain : real; +begin + -- Signal assignments + clk_in <= To_bit(clk_in_tmp); -- convert std_logic to bit + -- Component instances + v1 : entity work.v_sine(ideal) + generic map( + freq => 1.0, + amplitude => 5.0 + ) + port map( + pos => sine_in, + neg => ELECTRICAL_REF + ); + adc25 : entity work.adc(struct) + port map( + gain => gain, + a => sine_in, + d_out => dig_out1, + clk => clk_in + ); + adc26 : entity work.adc(ideal) + port map( + gain => gain, + a => sine_in, + d_out => dig_out2, + clk => clk_in + ); + clock1 : entity work.clock_duty(ideal) + generic map( + on_time => 1 ms, + off_time => 0.5 ms + ) + port map( + CLOCK_OUT => clk_in_tmp + ); + src1 : entity work.src_constant(ideal) + generic map( + level => 1.0 + ) + port map( + output => gain + ); +end tb_adc; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/test_bench-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/test_bench-1.vhd new file mode 100644 index 000000000..eff53a3e3 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/test_bench-1.vhd @@ -0,0 +1,51 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; +use ieee_proposed.mechanical_systems.all; +use ieee_proposed.electrical_systems.all; + +entity test_bench is +end entity test_bench; + +architecture example of test_bench is + + signal clk, reset: bit; + signal rpm : natural; + signal forward : bit; + +begin + dut : entity work.propulsion(mixed) + port map ( clk, reset, rpm, forward ); + + stimulus: process is + begin + clk <= '1'; reset <= '0'; rpm <= 0; forward <= '1'; wait for 10 sec; + clk <= '0'; wait for 10 sec; + clk <= '1'; rpm <= 50; wait for 20 sec; + clk <= '0'; wait for 20 sec; + clk <= '1'; rpm <= 0; wait for 20 sec; + clk <= '0'; wait for 20 sec; + clk <= '1'; rpm <= 50; forward <= '0'; wait for 20 sec; + clk <= '0'; wait for 20 sec; + -- ... + wait; + end process stimulus; + +end architecture example; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/vc_amp.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/vc_amp.vhd new file mode 100644 index 000000000..5347c283f --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/vc_amp.vhd @@ -0,0 +1,32 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity vc_amp is + port ( quantity g : in voltage; + terminal a, o : electrical ); +end entity vc_amp; + +architecture ideal of vc_amp is + quantity v_in across a; + quantity v_out across i_out through o; +begin + v_out == v_in * g; +end architecture ideal; |