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Diffstat (limited to 'testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/resistor.vhd')
| -rw-r--r-- | testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/resistor.vhd | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/resistor.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/resistor.vhd new file mode 100644 index 000000000..5f492f448 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/resistor.vhd @@ -0,0 +1,32 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity resistor is + port ( terminal p1, p2 : electrical ); +end entity resistor ; + +architecture ideal of resistor is + quantity v across i through p1 to p2; + constant resistance : real := 10000.0; +begin + v == i * resistance; +end architecture ideal; + |