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Diffstat (limited to 'testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/d_ff.vhd')
-rw-r--r-- | testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/d_ff.vhd | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/d_ff.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/d_ff.vhd new file mode 100644 index 000000000..b586f69ab --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/d_ff.vhd @@ -0,0 +1,35 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity d_ff is + port ( d, clk : in bit; q : out bit ); +end d_ff; + +architecture basic of d_ff is +begin + + ff_behavior : process is + begin + if clk = '1' then + q <= d after 2 ns; + end if; + wait on clk; + end process ff_behavior; + +end architecture basic; |