diff options
Diffstat (limited to 'testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling')
58 files changed, 3721 insertions, 0 deletions
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/S_R_flipflop-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/S_R_flipflop-1.vhd new file mode 100644 index 000000000..9702b9751 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/S_R_flipflop-1.vhd @@ -0,0 +1,28 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity S_R_flipflop is + port ( s, r : in bit; q, q_n : out bit ); + +begin + + check : assert not (s = '1' and r = '1') + report "Incorrect use of S_R_flip_flop: s and r both '1'"; + +end entity S_R_flipflop; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/S_R_flipflop.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/S_R_flipflop.vhd new file mode 100644 index 000000000..a726b736d --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/S_R_flipflop.vhd @@ -0,0 +1,39 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity S_R_flipflop is + port ( s, r : in bit; q, q_n : out bit ); +end entity S_R_flipflop; + +-------------------------------------------------- + +architecture functional of S_R_flipflop is + +begin + + q <= '1' when s = '1' else + '0' when r = '1'; + + q_n <= '0' when s = '1' else + '1' when r = '1'; + + check : assert not (s = '1' and r = '1') + report "Incorrect use of S_R_flip_flop: s and r both '1'"; + +end architecture functional; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/alu.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/alu.vhd new file mode 100644 index 000000000..4d9e5cac6 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/alu.vhd @@ -0,0 +1,138 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity alu is +end entity alu; + + +architecture test of alu is + + constant Tpd : delay_length := 2 ns; + + function "+" ( bv1, bv2 : in bit_vector ) return bit_vector is + + alias op1 : bit_vector(1 to bv1'length) is bv1; + alias op2 : bit_vector(1 to bv2'length) is bv2; + variable result : bit_vector(1 to bv1'length); + variable carry_in : bit; + variable carry_out : bit := '0'; + + begin + for index in result'reverse_range loop + carry_in := carry_out; -- of previous bit + result(index) := op1(index) xor op2(index) xor carry_in; + carry_out := (op1(index) and op2(index)) + or (carry_in and (op1(index) xor op2(index))); + end loop; + return result; + end function "+"; + + function "-" ( bv1, bv2 : in bit_vector ) return bit_vector is + + -- subtraction implemented by adding ((not bv2) + 1), ie -bv2 + + alias op1 : bit_vector(1 to bv1'length) is bv1; + alias op2 : bit_vector(1 to bv2'length) is bv2; + variable result : bit_vector(1 to bv1'length); + variable carry_in : bit; + variable carry_out : bit := '1'; + + begin + for index in result'reverse_range loop + carry_in := carry_out; -- of previous bit + result(index) := op1(index) xor (not op2(index)) xor carry_in; + carry_out := (op1(index) and (not op2(index))) + or (carry_in and (op1(index) xor (not op2(index)))); + end loop; + return result; + end function "-"; + + type alu_function_type is (alu_pass_a, alu_add, alu_sub, + alu_add_unsigned, alu_sub_unsigned, + alu_and, alu_or); + + signal alu_function : alu_function_type := alu_pass_a; + signal a, b : bit_vector(15 downto 0); + signal functional_result, equivalent_result : bit_vector(15 downto 0); + +begin + + functional_alu : block is + port ( result : out bit_vector(15 downto 0) ); + port map ( result => functional_result ); + begin + + -- code from book + + alu : with alu_function select + result <= a + b after Tpd when alu_add | alu_add_unsigned, + a - b after Tpd when alu_sub | alu_sub_unsigned, + a and b after Tpd when alu_and, + a or b after Tpd when alu_or, + a after Tpd when alu_pass_a; + + -- end code from book + + end block functional_alu; + + -------------------------------------------------- + + equivalent_alu : block is + port ( result : out bit_vector(15 downto 0) ); + port map ( result => equivalent_result ); + begin + + -- code from book + + alu : process is + begin + case alu_function is + when alu_add | alu_add_unsigned => result <= a + b after Tpd; + when alu_sub | alu_sub_unsigned => result <= a - b after Tpd; + when alu_and => result <= a and b after Tpd; + when alu_or => result <= a or b after Tpd; + when alu_pass_a => result <= a after Tpd; + end case; + wait on alu_function, a, b; + end process alu; + + -- end code from book + + end block equivalent_alu; + + -------------------------------------------------- + + stimulus : process is + begin + alu_function <= alu_add; wait for 10 ns; + a <= X"000A"; wait for 10 ns; + b <= X"0003"; wait for 10 ns; + alu_function <= alu_sub; wait for 10 ns; + alu_function <= alu_and; wait for 10 ns; + alu_function <= alu_or; wait for 10 ns; + alu_function <= alu_pass_a; wait for 10 ns; + + wait; + end process stimulus; + + verifier : + assert functional_result = equivalent_result + report "Functional and equivalent models give different results"; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/and2.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/and2.vhd new file mode 100644 index 000000000..479c3af75 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/and2.vhd @@ -0,0 +1,50 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee; use ieee.std_logic_1164.all; + +entity and2 is + port ( a, b : in std_ulogic; y : out std_ulogic ); +end entity and2; + +-------------------------------------------------- + +architecture detailed_delay of and2 is + + signal result : std_ulogic; + +begin + + gate : process (a, b) is + begin + result <= a and b; + end process gate; + + delay : process (result) is + begin + if result = '1' then + y <= reject 400 ps inertial '1' after 1.5 ns; + elsif result = '0' then + y <= reject 300 ps inertial '0' after 1.2 ns; + else + y <= reject 300 ps inertial 'X' after 500 ps; + end if; + end process delay; + +end architecture detailed_delay; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/and_or_inv.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/and_or_inv.vhd new file mode 100644 index 000000000..15c325da8 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/and_or_inv.vhd @@ -0,0 +1,57 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- not in book + +entity and_or_inv is + port ( a1, a2, b1, b2 : in bit := '1'; + y : out bit ); +end entity and_or_inv; + +-- end not in book + + +architecture primitive of and_or_inv is + + signal and_a, and_b : bit; + signal or_a_b : bit; + +begin + + and_gate_a : process (a1, a2) is + begin + and_a <= a1 and a2; + end process and_gate_a; + + and_gate_b : process (b1, b2) is + begin + and_b <= b1 and b2; + end process and_gate_b; + + or_gate : process (and_a, and_b) is + begin + or_a_b <= and_a or and_b; + end process or_gate; + + inv : process (or_a_b) is + begin + y <= not or_a_b; + end process inv; + +end architecture primitive; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/asym_delay.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/asym_delay.vhd new file mode 100644 index 000000000..122e95c5f --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/asym_delay.vhd @@ -0,0 +1,56 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity asym_delay is +end entity asym_delay; + + + +architecture test of asym_delay is + + signal a, z : bit; + +begin + + -- code from book + + asym_delay : process (a) is + constant Tpd_01 : time := 800 ps; + constant Tpd_10 : time := 500 ps; + begin + if a = '1' then + z <= transport a after Tpd_01; + else -- a = '0' + z <= transport a after Tpd_10; + end if; + end process asym_delay; + + -- end code from book + + + stimulus : process is + begin + a <= '1' after 2000 ps, + '0' after 4000 ps, + '1' after 6000 ps, + '0' after 6200 ps; + wait; + end process stimulus; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/clock_gen-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/clock_gen-1.vhd new file mode 100644 index 000000000..e1ff36b7b --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/clock_gen-1.vhd @@ -0,0 +1,41 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity clock_gen is +end entity clock_gen; + +architecture test of clock_gen is + + constant T_pw : time := 10 ns; + + signal clk : bit; + +begin + + -- code from book + + clock_gen : process is + begin + clk <= '1' after T_pw, '0' after 2*T_pw; + wait until clk = '0'; + end process clock_gen; + + -- end code from book + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/clock_gen-2.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/clock_gen-2.vhd new file mode 100644 index 000000000..af7a7d4ad --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/clock_gen-2.vhd @@ -0,0 +1,41 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity clock_gen is +end entity clock_gen; + +architecture test of clock_gen is + + constant T_pw : time := 10 ns; + + signal clk : bit; + +begin + + -- code from book + + clock_gen : process is + begin + clk <= '1' after T_pw, '0' after 2*T_pw; + wait for 2*T_pw; + end process clock_gen; + + -- end code from book + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/clock_gen.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/clock_gen.vhd new file mode 100644 index 000000000..10b54b4fe --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/clock_gen.vhd @@ -0,0 +1,42 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity clock_gen is +end entity clock_gen; + +architecture test of clock_gen is + + constant T_pw : time := 10 ns; + + signal clk : bit; + +begin + + -- code from book + + clock_gen : process (clk) is + begin + if clk = '0' then + clk <= '1' after T_pw, '0' after 2*T_pw; + end if; + end process clock_gen; + + -- end code from book + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/computer_system.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/computer_system.vhd new file mode 100644 index 000000000..15753d1bb --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/computer_system.vhd @@ -0,0 +1,82 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- not in book + +entity computer_system is +end entity computer_system; + +-- end not in book + + +architecture abstract of computer_system is + + subtype word is bit_vector(31 downto 0); + + signal address : natural; + signal read_data, write_data : word; + signal mem_read, mem_write : bit := '0'; + signal mem_ready : bit := '0'; + +begin + + cpu : process is + variable instr_reg : word; + variable PC : natural; + -- . . . -- other declarations + begin + loop + address <= PC; + mem_read <= '1'; + wait until mem_ready = '1'; + instr_reg := read_data; + mem_read <= '0'; + wait until mem_ready = '0'; + PC := PC + 4; + -- . . . -- execute the instruction + end loop; + end process cpu; + + memory : process is + type memory_array is array (0 to 2**14 - 1) of word; + variable store : memory_array := ( + -- . . . + -- not in book + 0 => X"0000_0000", + 1 => X"0000_0004", + 2 => X"0000_0008", + 3 => X"0000_000C", + 4 => X"0000_0010", + 5 => X"0000_0014", + others => X"0000_0000" + -- end not in book + ); + begin + wait until mem_read = '1' or mem_write = '1'; + if mem_read = '1' then + read_data <= store( address / 4 ); + mem_ready <= '1'; + wait until mem_read = '0'; + mem_ready <= '0'; + else + -- . . . -- perform write access + end if; + end process memory; + +end architecture abstract; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/counter.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/counter.vhd new file mode 100644 index 000000000..faf5f1414 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/counter.vhd @@ -0,0 +1,137 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- not in book + +package counter_types is + + -- code in book (in text) + + subtype digit is bit_vector(3 downto 0); + + -- end code in book (in text) + +end package counter_types; + + +entity add_1 is + port ( d0, d1, d2, d3 : in bit; + y0, y1, y2, y3 : out bit ); +end entity add_1; + + +architecture boolean_eqn of add_1 is +begin + + y0 <= not d0 after 4 ns; + + y1 <= (not d1 and d0) + or (d1 and not d0) after 4 ns; + + y2 <= (not d2 and d1 and d0) + or (d2 and not (d1 and d0)) after 4 ns; + + y3 <= (not d3 and d2 and d1 and d0) + or (d3 and not (d2 and d1 and d0)) after 4 ns; + +end architecture boolean_eqn; + + +entity buf4 is + port ( a0, a1, a2, a3 : in bit; + y0, y1, y2, y3 : out bit ); +end entity buf4; + + +architecture basic of buf4 is +begin + + y0 <= a0 after 2 ns; + y1 <= a1 after 2 ns; + y2 <= a2 after 2 ns; + y3 <= a3 after 2 ns; + +end architecture basic; + + +use work.counter_types.all; + +-- end not in book + + +entity counter is + port ( clk, clr : in bit; + q0, q1 : out digit ); +end entity counter; + +-------------------------------------------------- + +architecture registered of counter is + + signal current_val0, current_val1, next_val0, next_val1 : digit; + +begin + + val0_reg : entity work.reg4(struct) + port map ( d0 => next_val0(0), d1 => next_val0(1), + d2 => next_val0(2), d3 => next_val0(3), + q0 => current_val0(0), q1 => current_val0(1), + q2 => current_val0(2), q3 => current_val0(3), + clk => clk, clr => clr ); + + val1_reg : entity work.reg4(struct) + port map ( d0 => next_val1(0), d1 => next_val1(1), + d2 => next_val1(2), d3 => next_val1(3), + q0 => current_val1(0), q1 => current_val1(1), + q2 => current_val1(2), q3 => current_val1(3), + clk => clk, clr => clr ); + + incr0 : entity work.add_1(boolean_eqn) -- . . .; + -- not in book + port map ( d0 => current_val0(0), d1 => current_val0(1), + d2 => current_val0(2), d3 => current_val0(3), + y0 => next_val0(0), y1 => next_val0(1), + y2 => next_val0(2), y3 => next_val0(3) ); + -- end not in book + + incr1 : entity work.add_1(boolean_eqn) -- . . .; + -- not in book + port map ( d0 => current_val1(0), d1 => current_val1(1), + d2 => current_val1(2), d3 => current_val1(3), + y0 => next_val1(0), y1 => next_val1(1), + y2 => next_val1(2), y3 => next_val1(3) ); + -- end not in book + + buf0 : entity work.buf4(basic) -- . . .; + -- not in book + port map ( a0 => current_val0(0), a1 => current_val0(1), + a2 => current_val0(2), a3 => current_val0(3), + y0 => q0(0), y1 => q0(1), + y2 => q0(2), y3 => q0(3) ); + -- end not in book + + buf1 : entity work.buf4(basic) -- . . .; + -- not in book + port map ( a0 => current_val1(0), a1 => current_val1(1), + a2 => current_val1(2), a3 => current_val1(3), + y0 => q1(0), y1 => q1(1), + y2 => q1(2), y3 => q1(3) ); + -- end not in book + +end architecture registered; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/edge_triggered_Dff.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/edge_triggered_Dff.vhd new file mode 100644 index 000000000..d061a397c --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/edge_triggered_Dff.vhd @@ -0,0 +1,39 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity edge_triggered_Dff is + port ( D : in bit; clk : in bit; clr : in bit; + Q : out bit ); +end entity edge_triggered_Dff; + +-------------------------------------------------- + +architecture behavioral of edge_triggered_Dff is +begin + + state_change : process (clk, clr) is + begin + if clr = '1' then + Q <= '0' after 2 ns; + elsif clk'event and clk = '1' then + Q <= D after 2 ns; + end if; + end process state_change; + +end architecture behavioral; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/full_adder.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/full_adder.vhd new file mode 100644 index 000000000..9b17dc184 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/full_adder.vhd @@ -0,0 +1,38 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity full_adder is + port ( a, b, c_in : bit; s, c_out : out bit ); +end entity full_adder; + + +architecture truth_table of full_adder is +begin + + with bit_vector'(a, b, c_in) select + (c_out, s) <= bit_vector'("00") when "000", + bit_vector'("01") when "001", + bit_vector'("01") when "010", + bit_vector'("10") when "011", + bit_vector'("01") when "100", + bit_vector'("10") when "101", + bit_vector'("10") when "110", + bit_vector'("11") when "111"; + +end architecture truth_table; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/index-ams.txt new file mode 100644 index 000000000..aa17bf41c --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/index-ams.txt @@ -0,0 +1,82 @@ +--------------------------------------------------------------------------------------------------------------------------------------------- +-- Chapter 5 - Digital Modeling Constructs +--------------------------------------------------------------------------------------------------------------------------------------------- +-- Filename Primary Unit Secondary Unit Figure/Section +----------- ------------ -------------- -------------- +program_rom.vhd entity program_rom -- Figure 5-1 +and_or_inv.vhd entity and_or_inv primitive Figure 5-2 +clock_gen.vhd entity clock_gen test Figure 5-3 +mux.vhd entity mux test Figure 5-4 +edge_triggered_Dff.vhd entity edge_triggered_Dff behavioral Figure 5-5 +mux2.vhd entity mux2 behavioral Figure 5-6 +clock_gen-1.vhd entity clock_gen test Figure 5-7 +clock_gen-2.vhd entity clock_gen test Figure 5-8 +computer_system.vhd entity computer_system abstract Figure 5-9 +asym_delay.vhd entity asym_delay test Figure 5-12 +and2.vhd entity and2 detailed_delay Figure 5-16 +zmux.vhd entity zmux test Figure 5-17 +zmux-1.vhd entity zmux test Figure 5-18 +scheduler.vhd entity scheduler test Figure 5-19 +alu.vhd entity alu test Figure 5-20 +full_adder.vhd entity full_adder truth_table Figure 5-21 +S_R_flipflop.vhd entity S_R_flipflop functional Figure 5-22 +S_R_flipflop-1.vhd entity S_R_flipflop -- Figure 5-23 +rom.vhd entity rom -- Figure 5-24 +reg4.vhd entity reg4 struct Figure 5-25 +counter.vhd package counter_types -- Section 5.4 +-- entity add_1 boolean_eqn -- +-- entity buf4 basic -- +-- counter registered Figure 5-27 +microprocessor.vhd reg -- Figure 5-28 +-- microprocessor RTL Figure 5-28 +inline_01.vhd package adder_types -- -- +-- entity adder -- Section 5.1 +inline_02.vhd package adder_types -- -- +-- entity adder -- Section 5.1 +inline_03.vhd entity and_or_inv -- Section 5.1 +inline_04.vhd entity top_level -- Section 5.1 +inline_05.vhd -- abstract Section 5.2 +inline_06.vhd entity inline_06 test Section 5.3 +inline_07.vhd entity inline_07 test Section 5.3 +inline_08.vhd entity inline_08 test Section 5.3 +inline_09.vhd entity inline_09 test Section 5.3 +inline_10.vhd entity inline_10 test Section 5.3 +inline_11.vhd entity inline_11 test Section 5.3 +inline_12.vhd entity inline_12 test Section 5.3 +inline_13.vhd entity inline_13 test Section 5.3 +inline_14.vhd entity inline_14 test Section 5.3 +inline_15.vhd entity inline_15 test Section 5.3 +inline_16.vhd entity inline_16 test Section 5.3 +inline_17.vhd entity inline_17 test Section 5.3 +inline_18.vhd entity DRAM_controller fpld Section 5.4 +-- entity inline_18 test Section 5.4 +inline_19.vhd package inline_19 -- Section 5.4 +inline_20.vhd package inline_20_types -- Section 5.4 +-- entity FIFO -- -- +-- entity inline_20 test Section 5.4 +inline_21.vhd entity and_gate behavioral Section 5.4 +-- entity inline_21 test Section 5.4 +inline_22.vhd entity mux4 functional Section 5.4 +-- entity inline_22 test Section 5.4 +inline_23.vhd entity and_or_inv functional Section 5.4 +-- entity inline_23 test Section 5.4 +inline_24.vhd entity and3 functional Section 5.4 +-- entity inline_24 test Section 5.4 +inline_28a.vhd entity inline_28a test Section 5.3 +--------------------------------------------------------------------------------------------------------------------------------------------- +-- TestBenches +--------------------------------------------------------------------------------------------------------------------------------------------- +-- Filename Primary Unit Secondary Unit Tested Model +------------ ------------ -------------- ------------ +tb_and_or_inv.vhd entity tb_and_or_inv test and_or_inv.vhd +tb_edge_triggered_Dff.vhd entity tb_edge_triggered_Dff test edge_triggered_Dff.vhd +tb_mux2.vhd entity tb_mux2 test mux2.vhd +tb_and2.vhd entity tb_and2 test and2.vhd +tb_full_adder.vhd entity tb_full_adder test full_adder.vhd +tb_S_R_flipflop.vhd entity tb_S_R_flipflop test S_R_flipflop.vhd +tb_S_R_flipflop-1.vhd -- functional S_R_flipflop.vhd +-- entity tb_S_R_flipflop test -- +tb_rom.vhd -- do_nothing rom.vhd +-- entity tb_rom test -- +tb_reg4.vhd entity tb_reg4 test reg4.vhd +tb_counter.vhd entity tb_counter test counter.vhd diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_01.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_01.vhd new file mode 100644 index 000000000..adb54ff85 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_01.vhd @@ -0,0 +1,37 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- not in book + +package adder_types is + + subtype word is integer; + +end package adder_types; + + +use work.adder_types.all; + +-- end not in book + +entity adder is + port ( a : in word; + b : in word; + sum : out word ); +end entity adder; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_02.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_02.vhd new file mode 100644 index 000000000..898acfe7e --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_02.vhd @@ -0,0 +1,36 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- not in book + +package adder_types is + + subtype word is integer; + +end package adder_types; + + +use work.adder_types.all; + +-- end not in book + +entity adder is + port ( a, b : in word; + sum : out word ); +end entity adder; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_03.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_03.vhd new file mode 100644 index 000000000..2708126e0 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_03.vhd @@ -0,0 +1,23 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity and_or_inv is + port ( a1, a2, b1, b2 : in bit := '1'; + y : out bit ); +end entity and_or_inv; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_04.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_04.vhd new file mode 100644 index 000000000..7b83355e9 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_04.vhd @@ -0,0 +1,21 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity top_level is +end entity top_level; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_05.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_05.vhd new file mode 100644 index 000000000..a1ef02cc2 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_05.vhd @@ -0,0 +1,28 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +architecture abstract of adder is +begin + + add_a_b : process (a, b) is + begin + sum <= a + b; + end process add_a_b; + +end architecture abstract; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_06.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_06.vhd new file mode 100644 index 000000000..3fbe1ed08 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_06.vhd @@ -0,0 +1,72 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_06 is + +end entity inline_06; + + +---------------------------------------------------------------- + + +architecture test of inline_06 is + + signal y : bit := '0'; + signal or_a_b : bit := '0'; + signal clk : bit := '0'; + +begin + + + process_3_a : process is + begin + + -- code from book: + + y <= not or_a_b after 5 ns; + + -- end of code from book + + wait on or_a_b; + end process process_3_a; + + + stimulus_3_a : process is + begin + or_a_b <= '1' after 20 ns, + '0' after 40 ns; + wait; + end process stimulus_3_a; + + + process_3_b : process is + constant T_pw : delay_length := 10 ns; + begin + + -- code from book: + + clk <= '1' after T_pw, '0' after 2*T_pw; + + -- end of code from book + + wait for 2*T_pw; + end process process_3_b; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_07.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_07.vhd new file mode 100644 index 000000000..8a4554d9c --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_07.vhd @@ -0,0 +1,116 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_07 is + +end entity inline_07; + + +---------------------------------------------------------------- + + +library ieee; use ieee.std_logic_1164.all; + +architecture test of inline_07 is + + signal clk, d : std_ulogic; + + constant Tpw_clk : delay_length := 10 ns; + constant Tsu : delay_length := 4 ns; + +begin + + + process_3_c : process (clk, d) is + begin + + -- code from book: + + if clk'event and (clk = '1' or clk = 'H') + and (clk'last_value = '0' or clk'last_value = 'L') + then + assert d'last_event >= Tsu + report "Timing error: d changed within setup time of clk"; + end if; + + -- end of code from book + + end process process_3_c; + + + ---------------- + + + process_3_d : process (clk, d) is + begin + + -- code from book: + + assert (not clk'event) or clk'delayed'last_event >= Tpw_clk + report "Clock frequency too high"; + + -- end of code from book + + end process process_3_d; + + + ---------------- + + + process_3_e : process is + begin + + -- code from book: + + wait until clk = '1'; + + -- end of code from book + + report "clk changed to '1'"; + end process process_3_e; + + + ---------------- + + + stimulus_3_c_d : process is + begin + + clk <= '1' after 15 ns, + '0' after 30 ns, + '1' after 40 ns, + '0' after 50 ns, + 'H' after 60 ns, + '0' after 70 ns, + '1' after 80 ns, + 'L' after 90 ns, + 'H' after 100 ns, + 'L' after 120 ns, + '1' after 125 ns, -- should cause error + '0' after 130 ns; -- should cause error + + d <= '1' after 35 ns, + '0' after 77 ns, -- should cause error + '1' after 102 ns; + + wait; + end process stimulus_3_c_d; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_08.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_08.vhd new file mode 100644 index 000000000..bcc6d1a93 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_08.vhd @@ -0,0 +1,91 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_08 is + +end entity inline_08; + + +---------------------------------------------------------------- + + +library util; use util.stimulus_generators.all; + +architecture test of inline_08 is + + constant T_pd : delay_length := 5 ns; + + signal a, b : bit := '0'; + signal test_inputs : bit_vector(1 to 2); + +begin + + + block_3_f : block is + + signal sum, carry : bit; + + begin + + -- code from book: + + half_add : process is + begin + sum <= a xor b after T_pd; + carry <= a and b after T_pd; + wait on a, b; + end process half_add; + + -- end of code from book + + end block block_3_f; + + + ---------------- + + + block_3_g : block is + + signal sum, carry : bit; + + begin + + -- code from book: + + half_add : process (a, b) is + begin + sum <= a xor b after T_pd; + carry <= a and b after T_pd; + end process half_add; + + -- end of code from book + + end block block_3_g; + + + ---------------- + + + stimulus_3_f_g : + all_possible_values(test_inputs, 20 ns); + + (a, b) <= test_inputs; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_09.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_09.vhd new file mode 100644 index 000000000..7839e859d --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_09.vhd @@ -0,0 +1,119 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_09 is + +end entity inline_09; + + +---------------------------------------------------------------- + + +architecture test of inline_09 is + + signal clk, reset, trigger, test0, test1 : bit := '0'; + +begin + + + process_3_h : process is + begin + + -- code from book: + + wait until clk = '1'; + + -- end of code from book + + report "clk rising edge detected"; + + end process process_3_h; + + + ---------------- + + + process_3_i : process is + begin + + -- code from book: + + wait on clk until reset = '0'; + + -- end of code from book + + report "synchronous reset detected"; + + end process process_3_i; + + + ---------------- + + + process_3_j : process is + begin + + -- code from book: + + wait until trigger = '1' for 1 ms; + + -- end of code from book + + if trigger'event and trigger = '1' then + report "trigger rising edge detected"; + else + report "trigger timeout"; + end if; + + end process process_3_j; + + + ---------------- + + + -- code from book: + + test_gen : process is + begin + test0 <= '0' after 10 ns, '1' after 20 ns, '0' after 30 ns, '1' after 40 ns; + test1 <= '0' after 10 ns, '1' after 30 ns; + wait; + end process test_gen; + + -- end of code from book + + + ---------------- + + + stimulus_3_h_i_j : process is + begin + clk <= '1' after 10 ns, '0' after 20 ns, + '1' after 30 ns, '0' after 40 ns, + '1' after 50 ns, '0' after 60 ns, + '1' after 70 ns, '0' after 80 ns; + reset <= '1' after 45 ns, '0' after 75 ns; + trigger <= '1' after 10 ns, '0' after 20 ns, + '1' after 30 ns, '0' after 40 ns; + + wait; + end process stimulus_3_h_i_j; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_10.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_10.vhd new file mode 100644 index 000000000..bca36c805 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_10.vhd @@ -0,0 +1,66 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_10 is + +end entity inline_10; + + +---------------------------------------------------------------- + + +architecture test of inline_10 is + + signal data : bit_vector(7 downto 0) := X"FF"; + signal s : bit := '0'; + +begin + + + process_3_l : process is + begin + wait for 10 ns; + + -- code from book: + + data <= X"00"; + + -- end of code from book + + wait for 10 ns; + + -- code from book: + + s <= '1'; + -- . . . + if s = '1' then -- . . . + -- not in book + report "s is '1'"; + else + report "s is '0'"; + end if; + -- end not in boook + + -- end of code from book + + wait; + end process process_3_l; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_11.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_11.vhd new file mode 100644 index 000000000..c86fd0a05 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_11.vhd @@ -0,0 +1,63 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_11 is + +end entity inline_11; + + +---------------------------------------------------------------- + + +architecture test of inline_11 is + + signal line_in, line_out : bit := '0'; + +begin + + + -- code from book: + + transmission_line : process (line_in) is + begin + line_out <= transport line_in after 500 ps; + end process transmission_line; + + -- end of code from book + + + ---------------- + + + stimulus : process is + begin + line_in <= '1' after 2000 ps, + '0' after 4000 ps, + '1' after 6000 ps, + '0' after 6200 ps, + '1' after 8000 ps, + '0' after 8200 ps, + '1' after 8300 ps, + '0' after 8400 ps; + + wait; + end process stimulus; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_12.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_12.vhd new file mode 100644 index 000000000..3892d65c2 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_12.vhd @@ -0,0 +1,96 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_12 is + +end entity inline_12; + + +---------------------------------------------------------------- + + +architecture test of inline_12 is + + signal top_a, bottom_a : bit := '0'; + signal top_y, bottom_y : bit; + +begin + + + block_3_m : block is + port ( a : in bit; y : out bit := '1' ); + port map ( a => top_a, y => top_y ); + + begin + + -- code from book: + + inv : process (a) is + begin + y <= inertial not a after 3 ns; + end process inv; + + -- end of code from book + + end block block_3_m; + + + ---------------- + + + block_3_n : block is + port ( a : in bit; y : out bit := '1' ); + port map ( a => bottom_a, y => bottom_y); + + begin + + -- code from book: + + inv : process (a) is + begin + y <= reject 2 ns inertial not a after 3 ns; + end process inv; + + -- end of code from book + + end block block_3_n; + + + ---------------- + + + stimulus_3_m_n : process is + begin + top_a <= '1' after 1 ns, + '0' after 6 ns, + '1' after 8 ns; + bottom_a <= '1' after 1 ns, + '0' after 6 ns, + '1' after 9 ns, + '0' after 11.5 ns, + '1' after 16 ns, + '0' after 18 ns, + '1' after 19 ns, + '0' after 20 ns; + + wait; + end process stimulus_3_m_n; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_13.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_13.vhd new file mode 100644 index 000000000..54acc1142 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_13.vhd @@ -0,0 +1,59 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_13 is + +end entity inline_13; + + +---------------------------------------------------------------- + + +library ieee; use ieee.std_logic_1164.all; + +architecture test of inline_13 is + + signal s : std_ulogic; + +begin + + + process_3_o : process is + begin + s <= '1' after 11 ns, + 'X' after 12 ns, + '1' after 14 ns, + '0' after 15 ns, + '1' after 16 ns, + '1' after 17 ns, + '1' after 20 ns, + '0' after 25 ns; + wait for 10 ns; + + -- code from book: + + s <= reject 5 ns inertial '1' after 8 ns; + + -- end of code from book + + wait; + end process process_3_o; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_14.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_14.vhd new file mode 100644 index 000000000..359f880ea --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_14.vhd @@ -0,0 +1,87 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_14 is + +end entity inline_14; + + +---------------------------------------------------------------- + + +architecture test of inline_14 is + + signal PC, functional_next_PC, equivalent_next_PC : integer := 0; + +begin + + + block_3_p : block is + port ( next_PC : out integer ); + port map ( next_PC => functional_next_PC ); + begin + + -- code from book: + + PC_incr : next_PC <= PC + 4 after 5 ns; + + -- end of code from book + + end block block_3_p; + + + ---------------- + + + block_3_q : block is + port ( next_PC : out integer ); + port map ( next_PC => equivalent_next_PC ); + begin + + -- code from book: + + PC_incr : process is + begin + next_PC <= PC + 4 after 5 ns; + wait on PC; + end process PC_incr; + + -- end of code from book + + end block block_3_q; + + + ---------------- + + + stimulus : process is + begin + for i in 1 to 10 loop + PC <= i after 20 ns; + wait for 20 ns; + end loop; + wait; + end process stimulus; + + verifier : + assert functional_next_PC = equivalent_next_PC + report "Functional and equivalent models give different results"; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_15.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_15.vhd new file mode 100644 index 000000000..a0cd6e827 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_15.vhd @@ -0,0 +1,83 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_15 is + generic ( extended_reset : boolean := false ); +end entity inline_15; + + +---------------------------------------------------------------- + + +architecture test of inline_15 is + + signal functional_reset, equivalent_reset : bit := '0'; + +begin + + + block_3_r : block is + port ( reset : out bit ); + port map ( reset => functional_reset ); + begin + + -- code from book: + + reset_gen : reset <= '1', '0' after 200 ns when extended_reset else + '1', '0' after 50 ns; + + -- end of code from book + + end block block_3_r; + + + ---------------- + + + block_3_s : block is + port ( reset : out bit ); + port map ( reset => equivalent_reset ); + begin + + -- code from book: + + reset_gen : process is + begin + if extended_reset then + reset <= '1', '0' after 200 ns; + else + reset <= '1', '0' after 50 ns; + end if; + wait; + end process reset_gen; + + -- end of code from book + + end block block_3_s; + + + ---------------- + + + verifier : + assert functional_reset = equivalent_reset + report "Functional and equivalent models give different results"; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_16.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_16.vhd new file mode 100644 index 000000000..8be519e72 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_16.vhd @@ -0,0 +1,60 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_16 is + +end entity inline_16; + + +---------------------------------------------------------------- + + +architecture test of inline_16 is + + constant Tpd_01 : time := 800 ps; + constant Tpd_10 : time := 500 ps; + + signal a, z : bit; + +begin + + + -- code from book: + + asym_delay : z <= transport a after Tpd_01 when a = '1' else + a after Tpd_10; + + -- end of code from book + + + ---------------- + + + stimulus : process is + begin + a <= '1' after 2000 ps, + '0' after 4000 ps, + '1' after 6000 ps, + '0' after 6200 ps; + + wait; + end process stimulus; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_17.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_17.vhd new file mode 100644 index 000000000..f0a40ce37 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_17.vhd @@ -0,0 +1,69 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_17 is + +end entity inline_17; + + +---------------------------------------------------------------- + + +architecture test of inline_17 is + + signal s, r, q, q_n : bit := '0'; + +begin + + q <= '1' when s = '1' else + '0' when r = '1'; + + q_n <= '0' when s = '1' else + '1' when r = '1'; + + + -- code from book: + + check : process is + begin + assert not (s = '1' and r = '1') + report "Incorrect use of S_R_flip_flop: s and r both '1'"; + wait on s, r; + end process check; + + -- end of code from book + + + stimulus : process is + begin + wait for 10 ns; + s <= '1'; wait for 10 ns; + s <= '0'; wait for 10 ns; + r <= '1'; wait for 10 ns; + r <= '0'; wait for 10 ns; + s <= '1'; wait for 10 ns; + r <= '1'; wait for 10 ns; + s <= '0'; wait for 10 ns; + r <= '0'; wait for 10 ns; + + wait; + end process stimulus; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_18.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_18.vhd new file mode 100644 index 000000000..dee1aae59 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_18.vhd @@ -0,0 +1,92 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- code from book: + +entity DRAM_controller is + port ( rd, wr, mem : in bit; + ras, cas, we, ready : out bit ); +end entity DRAM_controller; + +-- end of code from book + + +---------------------------------------------------------------- + + +architecture fpld of DRAM_controller is +begin +end architecture fpld; + + +---------------------------------------------------------------- + + +entity inline_18 is + +end entity inline_18; + + +---------------------------------------------------------------- + + +architecture test of inline_18 is + + + +begin + + + block_4_a : block is + signal cpu_rd, cpu_wr, cpu_mem, + mem_ras, mem_cas, mem_we, cpu_rdy : bit; + begin + + -- code from book: + + main_mem_controller : entity work.DRAM_controller(fpld) + port map ( cpu_rd, cpu_wr, cpu_mem, + mem_ras, mem_cas, mem_we, cpu_rdy ); + + -- end of code from book + + end block block_4_a; + + + ---------------- + + + block_4_b : block is + signal cpu_rd, cpu_wr, cpu_mem, + mem_ras, mem_cas, mem_we, cpu_rdy : bit; + begin + + -- code from book: + + main_mem_controller : entity work.DRAM_controller(fpld) + port map ( rd => cpu_rd, wr => cpu_wr, + mem => cpu_mem, ready => cpu_rdy, + ras => mem_ras, cas => mem_cas, we => mem_we ); + + -- end of code from book + + end block block_4_b; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_19.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_19.vhd new file mode 100644 index 000000000..b24c90fc6 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_19.vhd @@ -0,0 +1,28 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +package inline_19 is + + -- code from book: + + subtype digit is bit_vector(3 downto 0); + + -- end of code from book + +end package inline_19; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_20.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_20.vhd new file mode 100644 index 000000000..ab99cf818 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_20.vhd @@ -0,0 +1,77 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +package inline_20_types is + + -- code from book: + + type FIFO_status is record + nearly_full, nearly_empty, full, empty : bit; + end record FIFO_status; + + -- end of code from book + +end package inline_20_types; + + +---------------------------------------------------------------- + + +use work.inline_20_types.all; + +entity FIFO is + port ( status : out FIFO_status; + other_ports : out bit ); +end entity FIFO; + + +---------------------------------------------------------------- + + +entity inline_20 is + +end entity inline_20; + + +---------------------------------------------------------------- + + +use work.inline_20_types.all; + +architecture test of inline_20 is + + signal start_flush, end_flush, DMA_buffer_full, DMA_buffer_empty : bit; + +begin + + -- code from book: + + DMA_buffer : entity work.FIFO + port map ( -- . . ., + status.nearly_full => start_flush, + status.nearly_empty => end_flush, + status.full => DMA_buffer_full, + status.empty => DMA_buffer_empty, -- . . . ); + -- not in book + other_ports => open ); + -- end not in book + + -- end of code from book + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_21.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_21.vhd new file mode 100644 index 000000000..d76021849 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_21.vhd @@ -0,0 +1,94 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- code from book: + +entity and_gate is + port ( i : in bit_vector; y : out bit ); +end entity and_gate; + +-- end of code from book + + +---------------------------------------------------------------- + + +architecture behavioral of and_gate is +begin + + reducer : process (i) is + constant Tpd : delay_length := 2 ns; + variable result : bit; + begin + result := '1'; + for index in i'range loop + result := result and i(index); + end loop; + y <= result after Tpd; + end process reducer; + +end architecture behavioral; + + +---------------------------------------------------------------- + + +entity inline_21 is + +end entity inline_21; + + +---------------------------------------------------------------- + + +library util; use util.stimulus_generators.all; + +architecture test of inline_21 is + + -- code from book: + + signal serial_select, write_en, bus_clk, serial_wr : bit; + + -- end of code from book + + signal test_input : bit_vector(2 downto 0); + +begin + + -- code from book: + + serial_write_gate : entity work.and_gate + port map ( i(1) => serial_select, + i(2) => write_en, + i(3) => bus_clk, + y => serial_wr ); + + -- end of code from book + + + ---------------- + + + stimulus : all_possible_values( bv => test_input, + delay_between_values => 10 ns ); + + (serial_select, write_en, bus_clk) <= test_input; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_22.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_22.vhd new file mode 100644 index 000000000..bcdf9bd2b --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_22.vhd @@ -0,0 +1,94 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- code from book: + +entity mux4 is + port ( i0, i1, i2, i3, sel0, sel1 : in bit; + z : out bit ); +end entity mux4; + +-- end of code from book + + +---------------------------------------------------------------- + + +architecture functional of mux4 is +begin + + out_select : process (sel0, sel1, i0, i1, i2, i3) is + subtype bits_2 is bit_vector(1 downto 0); + begin + case bits_2'(sel1, sel0) is + when "00" => z <= i0; + when "01" => z <= i1; + when "10" => z <= i2; + when "11" => z <= i3; + end case; + end process out_select; + +end architecture functional; + + +---------------------------------------------------------------- + + +entity inline_22 is + +end entity inline_22; + + +---------------------------------------------------------------- + + +architecture test of inline_22 is + + signal select_line, line0, line1, result_line : bit; + +begin + + + -- code from book: + + a_mux : entity work.mux4 + port map ( sel0 => select_line, i0 => line0, i1 => line1, + z => result_line, + sel1 => '0', i2 => '1', i3 => '1' ); + + -- end of code from book + + + ---------------- + + + stimulus : process is + begin + wait for 5 ns; + line0 <= '1'; wait for 5 ns; + line1 <= '1'; wait for 5 ns; + select_line <= '1'; wait for 5 ns; + line1 <= '0'; wait for 5 ns; + line0 <= '0'; wait for 5 ns; + + wait; + end process stimulus; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_23.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_23.vhd new file mode 100644 index 000000000..3f9ebc599 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_23.vhd @@ -0,0 +1,83 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- code from book: + +entity and_or_inv is + port ( a1, a2, b1, b2 : in bit := '1'; + y : out bit ); +end entity and_or_inv; + +-- end of code from book + + +---------------------------------------------------------------- + + +architecture functional of and_or_inv is +begin + + func : y <= not ((a1 and a2) or (b1 and b2)); + +end architecture functional; + + +---------------------------------------------------------------- + + +entity inline_23 is + +end entity inline_23; + + +---------------------------------------------------------------- + + +library util; use util.stimulus_generators.all; + +architecture test of inline_23 is + + signal A, B, C, F : bit; + signal test_input : bit_vector(2 downto 0); + +begin + + + -- code from book: + + f_cell : entity work.and_or_inv + port map ( a1 => A, a2 => B, b1 => C, b2 => open, y => F ); + + -- end of code from book + + + ---------------- + + + stimulus : all_possible_values( bv => test_input, + delay_between_values => 10 ns ); + + (A, B, C) <= test_input; + + verifier : + postponed assert F = not ((A and B) or C) + report "function model produced unexpected result"; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_24.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_24.vhd new file mode 100644 index 000000000..b3658c020 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_24.vhd @@ -0,0 +1,111 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- code from book: + +entity and3 is + port ( a, b, c : in bit := '1'; + z, not_z : out bit); +end entity and3; + +-- end of code from book + + +---------------------------------------------------------------- + + +architecture functional of and3 is +begin + + non_inverting: + z <= a and b and c; + + inverting: + not_z <= not (a and b and c); + +end architecture functional; + + +---------------------------------------------------------------- + + +entity inline_24 is + +end entity inline_24; + + +---------------------------------------------------------------- + + +library util; use util.stimulus_generators.all; + +architecture test of inline_24 is + + signal s1, s2, ctrl1_a, ctrl1_b : bit; + signal test_input : bit_vector(1 to 2); + +begin + + + block_4_a : block is + port ( ctrl1 : out bit ); + port map ( ctrl1 => ctrl1_a ); + begin + + -- code from book: + + g1 : entity work.and3 port map ( a => s1, b => s2, not_z => ctrl1 ); + + -- end of code from book + + end block block_4_a; + + + ---------------- + + + block_4_b : block is + port ( ctrl1 : out bit ); + port map ( ctrl1 => ctrl1_b ); + begin + + -- code from book: + + g1 : entity work.and3 port map ( a => s1, b => s2, not_z => ctrl1, + c => open, z => open ); + + -- end of code from book + + end block block_4_b; + + + ---------------- + + + stimulus : all_possible_values( bv => test_input, + delay_between_values => 10 ns ); + + (s1, s2) <= test_input; + + verifier : + assert ctrl1_a = ctrl1_b + report "versions differ"; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_28a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_28a.vhd new file mode 100644 index 000000000..d0f0b2178 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_28a.vhd @@ -0,0 +1,49 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_28a is + +end entity inline_28a; + + +---------------------------------------------------------------- + + +architecture test of inline_28a is + + quantity disp : real; + constant min_high : real := 2.5; + +begin + + + process_3_h : process is + begin + + -- code from book: + + wait until disp'above(min_high) for 2.0; + + -- end of code from book + + wait; + end process process_3_h; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/microprocessor.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/microprocessor.vhd new file mode 100644 index 000000000..14bf0b905 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/microprocessor.vhd @@ -0,0 +1,55 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity reg is + port ( d : in bit_vector(7 downto 0); + q : out bit_vector(7 downto 0); + clk : in bit ); +end entity reg; + +-------------------------------------------------- + +-- not in book + +entity microprocessor is +end entity microprocessor; + +-- end not in book + +architecture RTL of microprocessor is + + signal interrupt_req : bit; + signal interrupt_level : bit_vector(2 downto 0); + signal carry_flag, negative_flag, overflow_flag, zero_flag : bit; + signal program_status : bit_vector(7 downto 0); + signal clk_PSR : bit; + -- . . . + +begin + + PSR : entity work.reg + port map ( d(7) => interrupt_req, + d(6 downto 4) => interrupt_level, + d(3) => carry_flag, d(2) => negative_flag, + d(1) => overflow_flag, d(0) => zero_flag, + q => program_status, + clk => clk_PSR ); + -- . . . + +end architecture RTL; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/mux.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/mux.vhd new file mode 100644 index 000000000..7baf3571d --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/mux.vhd @@ -0,0 +1,68 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity mux is +end entity mux; + +architecture test of mux is + + constant prop_delay : time := 5 ns; + + signal a, b, sel, z : bit; + +begin + + -- code from book + + mux : process (a, b, sel) is + begin + case sel is + when '0' => + z <= a after prop_delay; + when '1' => + z <= b after prop_delay; + end case; + end process mux; + + -- end code from book + + + stimulus : process is + subtype stim_vector_type is bit_vector(0 to 3); + type stim_vector_array is array ( natural range <> ) of stim_vector_type; + constant stim_vector : stim_vector_array + := ( "0000", + "0010", + "0100", + "0111", + "1001", + "1010", + "1101", + "1111" ); + begin + for i in stim_vector'range loop + (a, b, sel) <= stim_vector(i)(0 to 2); + wait for 10 ns; + assert z = stim_vector(i)(3); + end loop; + wait; + end process stimulus; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/mux2.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/mux2.vhd new file mode 100644 index 000000000..2b3b0f104 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/mux2.vhd @@ -0,0 +1,45 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity mux2 is + port ( a, b, sel : in bit; + z : out bit ); +end entity mux2; + +-------------------------------------------------- + +architecture behavioral of mux2 is + + constant prop_delay : time := 2 ns; + +begin + + slick_mux : process is + begin + case sel is + when '0' => + z <= a after prop_delay; + wait on sel, a; + when '1' => + z <= b after prop_delay; + wait on sel, b; + end case; + end process slick_mux; + +end architecture behavioral; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/program_rom.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/program_rom.vhd new file mode 100644 index 000000000..34d3d35bc --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/program_rom.vhd @@ -0,0 +1,43 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- not in book + +library ieee; use ieee.std_logic_1164.all; + +-- end not in book + + +entity program_ROM is + port ( address : in std_ulogic_vector(14 downto 0); + data : out std_ulogic_vector(7 downto 0); + enable : in std_ulogic ); + + subtype instruction_byte is bit_vector(7 downto 0); + type program_array is array (0 to 2**14 - 1) of instruction_byte; + constant program : program_array + := ( X"32", X"3F", X"03", -- LDA $3F03 + X"71", X"23", -- BLT $23 + -- not in book + others => X"00" + -- end not in book + -- . . . + ); + +end entity program_ROM; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/reg4.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/reg4.vhd new file mode 100644 index 000000000..4451f4fd3 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/reg4.vhd @@ -0,0 +1,41 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity reg4 is + port ( clk, clr, d0, d1, d2, d3 : in bit; + q0, q1, q2, q3 : out bit ); +end entity reg4; + +---------------------------------------------- + +architecture struct of reg4 is +begin + + bit0 : entity work.edge_triggered_Dff(behavioral) + port map (d0, clk, clr, q0); + bit1 : entity work.edge_triggered_Dff(behavioral) + port map (d1, clk, clr, q1); + bit2 : entity work.edge_triggered_Dff(behavioral) + port map (d2, clk, clr, q2); + bit3 : entity work.edge_triggered_Dff(behavioral) + port map (d3, clk, clr, q3); + +end architecture struct; + + diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/rom.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/rom.vhd new file mode 100644 index 000000000..9c1165b4d --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/rom.vhd @@ -0,0 +1,35 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity ROM is + port ( address : in natural; + data : out bit_vector(0 to 7); + enable : in bit ); + +begin + + trace_reads : process (enable) is + begin + if enable = '1' then + report "ROM read at time " & time'image(now) + & " from address " & natural'image(address); + end if; + end process trace_reads; + +end entity ROM; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/scheduler.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/scheduler.vhd new file mode 100644 index 000000000..930990104 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/scheduler.vhd @@ -0,0 +1,108 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity scheduler is +end entity scheduler; + + +architecture test of scheduler is + + constant scheduling_delay : delay_length := 5 ns; + + subtype request_type is natural range 0 to 20; + type server_status_type is (ready, busy); + + signal first_priority_request, + first_normal_request, + reset_request : request_type := 0; + signal functional_request, equivalent_request : request_type; + signal priority_waiting : boolean := false; + signal server_status : server_status_type := busy; + +begin + + functional_scheduler : block is + port ( request : out request_type ); + port map ( request => functional_request ); + begin + + -- code from book + + scheduler : + request <= first_priority_request after scheduling_delay + when priority_waiting and server_status = ready else + first_normal_request after scheduling_delay + when not priority_waiting and server_status = ready else + unaffected + when server_status = busy else + reset_request after scheduling_delay; + + -- end code from book + + end block functional_scheduler; + + -------------------------------------------------- + + equivalent_scheduler : block is + port ( request : out request_type ); + port map ( request => equivalent_request ); + begin + + -- code from book + + scheduler : process is + begin + if priority_waiting and server_status = ready then + request <= first_priority_request after scheduling_delay; + elsif not priority_waiting and server_status = ready then + request <= first_normal_request after scheduling_delay; + elsif server_status = busy then + null; + else + request <= reset_request after scheduling_delay; + end if; + wait on first_priority_request, priority_waiting, server_status, + first_normal_request, reset_request; + end process scheduler; + + -- end code from book + + end block equivalent_scheduler; + + -------------------------------------------------- + + stimulus : process is + begin + first_priority_request <= 10; wait for 20 ns; + first_normal_request <= 5; wait for 20 ns; + server_status <= ready; wait for 20 ns; + server_status <= busy; wait for 20 ns; + priority_waiting <= true; wait for 20 ns; + server_status <= ready; wait for 20 ns; + first_normal_request <= 7; wait for 20 ns; + first_priority_request <= 12; wait for 20 ns; + + wait; + end process stimulus; + + verifier : + assert functional_request = equivalent_request + report "Functional and equivalent models give different results"; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_S_R_flipflop-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_S_R_flipflop-1.vhd new file mode 100644 index 000000000..0c747f63a --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_S_R_flipflop-1.vhd @@ -0,0 +1,62 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +architecture functional of S_R_flipflop is + +begin + + q <= '1' when s = '1' else + '0' when r = '1'; + + q_n <= '0' when s = '1' else + '1' when r = '1'; + +end architecture functional; + + +entity tb_S_R_flipflop is +end entity tb_S_R_flipflop; + + +architecture test of tb_S_R_flipflop is + + signal s, r : bit := '0'; + signal q, q_n : bit; + +begin + + dut : entity work.S_R_flipflop(functional) + port map ( s => s, r => r, q => q, q_n => q_n ); + + stimulus : process is + begin + wait for 10 ns; + s <= '1'; wait for 10 ns; + s <= '0'; wait for 10 ns; + r <= '1'; wait for 10 ns; + r <= '0'; wait for 10 ns; + s <= '1'; wait for 10 ns; + r <= '1'; wait for 10 ns; + s <= '0'; wait for 10 ns; + r <= '0'; wait for 10 ns; + + wait; + end process stimulus; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_S_R_flipflop.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_S_R_flipflop.vhd new file mode 100644 index 000000000..b694ff17d --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_S_R_flipflop.vhd @@ -0,0 +1,49 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity tb_S_R_flipflop is +end entity tb_S_R_flipflop; + + +architecture test of tb_S_R_flipflop is + + signal s, r : bit := '0'; + signal q, q_n : bit; + +begin + + dut : entity work.S_R_flipflop(functional) + port map ( s => s, r => r, q => q, q_n => q_n ); + + stimulus : process is + begin + wait for 10 ns; + s <= '1'; wait for 10 ns; + s <= '0'; wait for 10 ns; + r <= '1'; wait for 10 ns; + r <= '0'; wait for 10 ns; + s <= '1'; wait for 10 ns; + r <= '1'; wait for 10 ns; + s <= '0'; wait for 10 ns; + r <= '0'; wait for 10 ns; + + wait; + end process stimulus; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_and2.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_and2.vhd new file mode 100644 index 000000000..f1da3ee30 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_and2.vhd @@ -0,0 +1,62 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity tb_and2 is +end entity tb_and2; + + +library ieee; use ieee.std_logic_1164.all; + +architecture test of tb_and2 is + + signal a, b : std_ulogic := '0'; + signal y : std_ulogic; + +begin + + dut : entity work.and2(detailed_delay) + port map ( a => a, b => b, y => y ); + + stimulus : process is + begin + wait for 10 ns; + a <= '1'; wait for 10 ns; + b <= '1'; wait for 10 ns; + b <= '0'; wait for 10 ns; + + b <= '1', '0' after 250 ps; wait for 10 ns; + b <= '1', '0' after 350 ps; wait for 10 ns; + b <= '1', '0' after 450 ps; wait for 10 ns; + b <= '1', '0' after 550 ps; wait for 10 ns; + b <= '1', '0' after 650 ps; wait for 10 ns; + b <= '1', '0' after 750 ps; wait for 10 ns; + b <= '1', '0' after 850 ps; wait for 10 ns; + + b <= '1'; wait for 10 ns; + b <= '0', '1' after 250 ps; wait for 10 ns; + b <= '0', '1' after 350 ps; wait for 10 ns; + b <= '0', '1' after 450 ps; wait for 10 ns; + + b <= 'X'; wait for 10 ns; + b <= '0'; wait for 10 ns; + b <= 'X', '0' after 250 ps; wait for 10 ns; + wait; + end process stimulus; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_and_or_inv.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_and_or_inv.vhd new file mode 100644 index 000000000..3d2cb6a48 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_and_or_inv.vhd @@ -0,0 +1,64 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity tb_and_or_inv is +end entity tb_and_or_inv; + + +architecture test of tb_and_or_inv is + + signal a1, a2, b1, b2, y : bit; + +begin + + dut : entity work.and_or_inv(primitive) + port map ( a1 => a1, a2 => a2, b1 => b1, b2 => b2, + y => y ); + + stimulus : process is + subtype stim_vector_type is bit_vector(0 to 3); + type stim_vector_array is array ( natural range <> ) of stim_vector_type; + constant stim_vector : stim_vector_array + := ( "0000", + "0001", + "0010", + "0011", + "0100", + "0101", + "0110", + "0111", + "1000", + "1001", + "1010", + "1011", + "1100", + "1101", + "1110", + "1111" ); + begin + for i in stim_vector'range loop + (a1, a2, b1, b2) <= stim_vector(i); + wait for 10 ns; + assert y = not ( (stim_vector(i)(0) and stim_vector(i)(1)) + or (stim_vector(i)(2) and stim_vector(i)(3)) ); + end loop; + wait; + end process stimulus; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_counter.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_counter.vhd new file mode 100644 index 000000000..31fb9c088 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_counter.vhd @@ -0,0 +1,42 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity tb_counter is +end entity tb_counter; + + +use work.counter_types.all; + +architecture test of tb_counter is + + signal clk, clr : bit := '0'; + signal q0, q1 : digit; + +begin + + dut : entity work.counter(registered) + port map ( clk => clk, clr => clr, + q0 => q0, q1 => q1 ); + + clk_gen : clk <= not clk after 20 ns; + + clr_gen : clr <= '1' after 95 ns, + '0' after 135 ns; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_edge_triggered_Dff.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_edge_triggered_Dff.vhd new file mode 100644 index 000000000..725520a06 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_edge_triggered_Dff.vhd @@ -0,0 +1,49 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity tb_edge_triggered_Dff is +end entity tb_edge_triggered_Dff; + + +architecture test of tb_edge_triggered_Dff is + + signal D, clk, clr, Q : bit := '0'; + +begin + + dut : entity work.edge_triggered_Dff(behavioral) + port map ( D => D, clk => clk, clr => clr, + Q => Q ); + + stimulus : process is + begin + D <= '1'; wait for 10 ns; + clk <= '1'; wait for 10 ns; + D <= '0'; wait for 10 ns; + clk <= '0'; wait for 10 ns; + D <= '1'; wait for 10 ns; + clr <= '1'; wait for 10 ns; + clk <= '1'; wait for 10 ns; + clr <= '0'; wait for 10 ns; + clk <= '0'; wait for 10 ns; + + wait; + end process stimulus; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_full_adder.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_full_adder.vhd new file mode 100644 index 000000000..f4f8c00ba --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_full_adder.vhd @@ -0,0 +1,40 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity tb_full_adder is +end entity tb_full_adder; + + +library util; use util.stimulus_generators.all; + +architecture test of tb_full_adder is + + signal a, b, c_in, s, c_out : bit; + signal test_vector : bit_vector(1 to 3); + +begin + + dut : entity work.full_adder + port map ( a => a, b => b, c_in => c_in, s => s, c_out => c_out ); + + all_possible_values ( test_vector, 10 ns ); + + (a, b, c_in) <= test_vector; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_mux2.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_mux2.vhd new file mode 100644 index 000000000..e7bd163fd --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_mux2.vhd @@ -0,0 +1,54 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity tb_mux2 is +end entity tb_mux2; + +architecture test of tb_mux2 is + + signal a, b, sel, z : bit; + +begin + + dut : entity work.mux2(behavioral) + port map ( a => a, b => b, sel => sel, z => z ); + + stimulus : process is + subtype stim_vector_type is bit_vector(0 to 3); + type stim_vector_array is array ( natural range <> ) of stim_vector_type; + constant stim_vector : stim_vector_array + := ( "0000", + "0100", + "1001", + "1101", + "0010", + "0111", + "1010", + "1111" ); + begin + for i in stim_vector'range loop + (a, b, sel) <= stim_vector(i)(0 to 2); + wait for 10 ns; + assert z = stim_vector(i)(3); + end loop; + wait; + end process stimulus; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_reg4.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_reg4.vhd new file mode 100644 index 000000000..d05be9c7d --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_reg4.vhd @@ -0,0 +1,51 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity tb_reg4 is +end entity tb_reg4; + + +architecture test of tb_reg4 is + + signal clk, clr, d0, d1, d2, d3 : bit := '0'; + signal q0, q1, q2, q3 : bit; + +begin + + dut : entity work.reg4(struct) + port map ( clk => clk, clr => clr, + d0 => d0, d1 => d1, d2 => d2, d3 => d3, + q0 => q0, q1 => q1, q2 => q2, q3 => q3 ); + + stimulus : process is + begin + (d3, d2, d1, d0) <= bit_vector'(b"1010"); wait for 10 ns; + clk <= '1'; wait for 10 ns; + (d3, d2, d1, d0) <= bit_vector'(b"0101"); wait for 10 ns; + clk <= '0'; wait for 10 ns; + (d3, d2, d1, d0) <= bit_vector'(b"1111"); wait for 10 ns; + clr <= '1'; wait for 10 ns; + clk <= '1'; wait for 10 ns; + clr <= '0'; wait for 10 ns; + clk <= '0'; wait for 10 ns; + + wait; + end process stimulus; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_rom.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_rom.vhd new file mode 100644 index 000000000..d69e8b7ec --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_rom.vhd @@ -0,0 +1,53 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +architecture do_nothing of ROM is +begin +end architecture do_nothing; + + +entity tb_rom is +end entity tb_rom; + + +architecture test of tb_rom is + + signal address : natural := 0; + signal data : bit_vector(0 to 7); + signal enable : bit := '0'; + +begin + + dut : entity work.ROM(do_nothing) + port map ( address => address, data => data, enable => enable ); + + stimulus : process is + begin + wait for 100 ns; + address <= 1000; wait for 10 ns; + enable <= '1', '0' after 10 ns; wait for 90 ns; + address <= 1004; wait for 10 ns; + enable <= '1', '0' after 10 ns; wait for 90 ns; + address <= 1008; wait for 10 ns; + enable <= '1', '0' after 10 ns; wait for 90 ns; + + wait; + end process stimulus; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/zmux-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/zmux-1.vhd new file mode 100644 index 000000000..a42ae1248 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/zmux-1.vhd @@ -0,0 +1,88 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity zmux is +end entity zmux; + + +library util; use util.stimulus_generators.all; + +architecture test of zmux is + + signal sel0, sel1, d0, d1, d2, d3 : bit := '0'; + signal functional_z, equivalent_z : bit; + +begin + + functional_mux : block is + port ( z : out bit ); + port map ( z => functional_z ); + begin + + -- code from book + + zmux : z <= d0 when sel1 = '0' and sel0 = '0' else + d1 when sel1 = '0' and sel0 = '1' else + d2 when sel1 = '1' and sel0 = '0' else + d3; + + -- end code from book + + end block functional_mux; + + -------------------------------------------------- + + equivalent_mux : block is + port ( z : out bit ); + port map ( z => equivalent_z ); + begin + + -- code from book + + zmux : process is + begin + if sel1 = '0' and sel0 = '0' then + z <= d0; + elsif sel1 = '0' and sel0 = '1' then + z <= d1; + elsif sel1 = '1' and sel0 = '0' then + z <= d2; + else + z <= d3; + end if; + wait on d0, d1, d2, d3, sel0, sel1; + end process zmux; + + -- end code from book + + end block equivalent_mux; + + -------------------------------------------------- + + stimulus : + all_possible_values( bv(0) => sel0, bv(1) => sel1, + bv(2) => d0, bv(3) => d1, + bv(4) => d2, bv(5) => d3, + delay_between_values => 10 ns ); + + verifier : + assert functional_z = equivalent_z + report "Functional and equivalent models give different results"; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/zmux.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/zmux.vhd new file mode 100644 index 000000000..2f27a8c96 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/zmux.vhd @@ -0,0 +1,88 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity zmux is +end entity zmux; + + +library util; use util.stimulus_generators.all; + +architecture test of zmux is + + signal sel0, sel1, d0, d1, d2, d3 : bit := '0'; + signal functional_z, equivalent_z : bit; + +begin + + functional_mux : block is + port ( z : out bit ); + port map ( z => functional_z ); + begin + + -- code from book + + zmux : z <= d0 when sel1 = '0' and sel0 = '0' else + d1 when sel1 = '0' and sel0 = '1' else + d2 when sel1 = '1' and sel0 = '0' else + d3 when sel1 = '1' and sel0 = '1'; + + -- end code from book + + end block functional_mux; + + -------------------------------------------------- + + equivalent_mux : block is + port ( z : out bit ); + port map ( z => equivalent_z ); + begin + + -- code from book + + zmux : process is + begin + if sel1 = '0' and sel0 = '0' then + z <= d0; + elsif sel1 = '0' and sel0 = '1' then + z <= d1; + elsif sel1 = '1' and sel0 = '0' then + z <= d2; + elsif sel1 = '1' and sel0 = '1' then + z <= d3; + end if; + wait on d0, d1, d2, d3, sel0, sel1; + end process zmux; + + -- end code from book + + end block equivalent_mux; + + -------------------------------------------------- + + stimulus : + all_possible_values( bv(0) => sel0, bv(1) => sel1, + bv(2) => d0, bv(3) => d1, + bv(4) => d2, bv(5) => d3, + delay_between_values => 10 ns ); + + verifier : + assert functional_z = equivalent_z + report "Functional and equivalent models give different results"; + +end architecture test; |