1 files changed, 37 insertions, 0 deletions
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_01.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_01.vhd
new file mode 100644
index 000000000..adb54ff85
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_01.vhd
@@ -0,0 +1,37 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- not in book
+
+package adder_types is
+
+  subtype word is integer;
+
+end package adder_types;
+
+
+use work.adder_types.all;
+
+-- end not in book
+
+entity adder is
+  port ( a : in word;
+         b : in word;
+         sum : out word );
+end entity adder;