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diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/S_R_flipflop.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/S_R_flipflop.vhd
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+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/S_R_flipflop.vhd
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+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity S_R_flipflop is
+  port ( s, r : in bit;  q, q_n : out bit );
+end entity S_R_flipflop;
+
+--------------------------------------------------
+
+architecture functional of S_R_flipflop is
+
+begin
+
+  q <= '1' when s = '1' else
+       '0' when r = '1';
+
+  q_n <= '0' when s = '1' else
+         '1' when r = '1';
+
+  check : assert not (s = '1' and r = '1')
+            report "Incorrect use of S_R_flip_flop: s and r both '1'";
+
+end architecture functional;