diff options
Diffstat (limited to 'testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs')
29 files changed, 1581 insertions, 0 deletions
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/automotive_valve.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/automotive_valve.vhd new file mode 100644 index 000000000..71b19f557 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/automotive_valve.vhd @@ -0,0 +1,34 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +use work.automotive_valve_defs.all; + +entity automotive_valve is + port ( terminal p1, p2 : valve_fluidic; + terminal control : valve_translational ); +end entity automotive_valve; + + +-- not in book + +architecture test of automotive_valve is +begin +end architecture test; + +-- end not in book diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/automotive_valve_defs.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/automotive_valve_defs.vhd new file mode 100644 index 000000000..bf41f4883 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/automotive_valve_defs.vhd @@ -0,0 +1,38 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; +use ieee_proposed.fluidic_systems.all, ieee_proposed.mechanical_systems.all; + +package automotive_valve_defs is + + subnature valve_fluidic is fluidic + tolerance "valve_pressure" across "valve_vflow_rate" through; + + subnature valve_translational is translational + tolerance "valve_displacement" across "valve_force" through; + + -- ... -- other useful declarations + + component automotive_valve is + port ( terminal p1, p2 : valve_fluidic; + terminal control : valve_translational ); + end component automotive_valve; + +end package automotive_valve_defs; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/brake_system.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/brake_system.vhd new file mode 100644 index 000000000..0d7a4ad23 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/brake_system.vhd @@ -0,0 +1,51 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- not in book + +use work.automotive_valve_defs.all; + +entity brake_system is +end entity brake_system; + +-- end not in book + + + +architecture structure of brake_system is + + use work.automotive_valve_defs.all; + + -- ... -- declarations of other components, terminals, etc + + -- not in book + terminal master_reservoir, brake_line : valve_fluidic; + terminal brake_pedal : valve_translational; + -- end not in book + +begin + + pedal_valve : component automotive_valve + port map ( p1 => master_reservoir, + p2 => brake_line, + control => brake_pedal ); + + -- ... -- other component instances + +end architecture structure; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/computer_structure.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/computer_structure.vhd new file mode 100644 index 000000000..d0ee652ce --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/computer_structure.vhd @@ -0,0 +1,37 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +configuration computer_structure of computer_system is + + for structure + + for interface_decoder : decoder_2_to_4 + use entity work.decoder_3_to_8(basic) + generic map ( Tpd_01 => prop_delay, Tpd_10 => prop_delay ) + port map ( s0 => in0, s1 => in1, s2 => '0', + enable => '1', + y0 => out0, y1 => out1, y2 => out2, y3 => out3, + y4 => open, y5 => open, y6 => open, y7 => open ); + end for; + + -- . . . + + end for; + +end configuration computer_structure; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/computer_system.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/computer_system.vhd new file mode 100644 index 000000000..df8a7b60b --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/computer_system.vhd @@ -0,0 +1,64 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- not in book + +entity computer_system is +end entity computer_system; + + +library util; use util.stimulus_generators.all; + +-- end not in book + + +architecture structure of computer_system is + + component decoder_2_to_4 is + generic ( prop_delay : delay_length ); + port ( in0, in1 : in bit; + out0, out1, out2, out3 : out bit ); + end component decoder_2_to_4; + + -- . . . + + -- not in book + + signal addr : bit_vector(5 downto 4); + signal interface_a_select, interface_b_select, + interface_c_select, interface_d_select : bit; + -- end not in book + +begin + + interface_decoder : component decoder_2_to_4 + generic map ( prop_delay => 4 ns ) + port map ( in0 => addr(4), in1 => addr(5), + out0 => interface_a_select, out1 => interface_b_select, + out2 => interface_c_select, out3 => interface_d_select ); + + -- . . . + + -- not in book + + all_possible_values(addr, 10 ns); + + -- end not in book + +end architecture structure; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/control_section.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/control_section.vhd new file mode 100644 index 000000000..3729acba9 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/control_section.vhd @@ -0,0 +1,89 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- not in book + +library ieee; use ieee.std_logic_1164.all; + +entity control_section is +end entity control_section; + +-- end not in book + + +architecture structural of control_section is + + component reg is + generic ( width : positive ); + port ( clk : in std_logic; + d : in std_logic_vector(0 to width - 1); + q : out std_logic_vector(0 to width - 1) ); + end component reg; + + for flag_reg : reg + use entity work.reg(gate_level) + port map ( clock => clk, data_in => d, data_out => q ); + + -- . . . + + -- not in book + signal clock_phase1, zero_result, neg_result, overflow_result, + zero_flag, neg_flag, overflow_flag : std_logic; + -- end not in book + +begin + + flag_reg : component reg + generic map ( width => 3 ) + port map ( clk => clock_phase1, + d(0) => zero_result, d(1) => neg_result, + d(2) => overflow_result, + q(0) => zero_flag, q(1) => neg_flag, + q(2) => overflow_flag ); + + -- . . . + + -- not in book + + stimulus : process is + begin + clock_phase1 <= '0'; + zero_result <= '0'; neg_result <= '0'; overflow_result <= '0'; wait for 10 ns; + clock_phase1 <= '1', '0' after 5 ns; wait for 10 ns; + zero_result <= '0'; neg_result <= '0'; overflow_result <= '1'; wait for 10 ns; + clock_phase1 <= '1', '0' after 5 ns; wait for 10 ns; + zero_result <= '0'; neg_result <= '1'; overflow_result <= '0'; wait for 10 ns; + clock_phase1 <= '1', '0' after 5 ns; wait for 10 ns; + zero_result <= '0'; neg_result <= '1'; overflow_result <= '1'; wait for 10 ns; + clock_phase1 <= '1', '0' after 5 ns; wait for 10 ns; + zero_result <= '1'; neg_result <= '0'; overflow_result <= '0'; wait for 10 ns; + clock_phase1 <= '1', '0' after 5 ns; wait for 10 ns; + zero_result <= '1'; neg_result <= '0'; overflow_result <= '1'; wait for 10 ns; + clock_phase1 <= '1', '0' after 5 ns; wait for 10 ns; + zero_result <= '1'; neg_result <= '1'; overflow_result <= '0'; wait for 10 ns; + clock_phase1 <= '1', '0' after 5 ns; wait for 10 ns; + zero_result <= '1'; neg_result <= '1'; overflow_result <= '1'; wait for 10 ns; + clock_phase1 <= '1', '0' after 5 ns; wait for 10 ns; + + wait; + end process stimulus; + + -- end not in book + +end architecture structural; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/controller_with_timing-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/controller_with_timing-1.vhd new file mode 100644 index 000000000..d7b8ac4cf --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/controller_with_timing-1.vhd @@ -0,0 +1,34 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +configuration controller_with_timing of control_section is + + for structural + + for flag_reg : reg + generic map ( t_setup => 200 ps, t_hold => 150 ps, + t_pd => 150 ps, width => width ) + port map ( reset_n => '1' ); + end for; + + -- . . . + + end for; + +end configuration controller_with_timing; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/decoder_3_to_8.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/decoder_3_to_8.vhd new file mode 100644 index 000000000..eba7230ea --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/decoder_3_to_8.vhd @@ -0,0 +1,53 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity decoder_3_to_8 is + generic ( Tpd_01, Tpd_10 : delay_length ); + port ( s0, s1, s2 : in bit; + enable : in bit; + y0, y1, y2, y3, y4, y5, y6, y7 : out bit ); +end entity decoder_3_to_8; + + +-- not in book + +architecture basic of decoder_3_to_8 is +begin + + process (enable, s2, s1, s0) is + begin + if enable = '0' then + (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00000000"); + else + case bit_vector'(s2, s1, s0) is + when "000" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00000001"); + when "001" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00000010"); + when "010" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00000100"); + when "011" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00001000"); + when "100" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00010000"); + when "101" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00100000"); + when "110" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("01000000"); + when "111" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("10000000"); + end case; + end if; + end process; + +end architecture basic; + +-- end not in book diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/fm_radio.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/fm_radio.vhd new file mode 100644 index 000000000..2c4163ba3 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/fm_radio.vhd @@ -0,0 +1,45 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- not in book + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity fm_radio is +end entity fm_radio; + +-- end not in book + + + +architecture top_level of fm_radio is + + terminal left_decoded, left_filtered : electrical; + terminal right_decoded, right_filtered : electrical; + -- ... + +begin + + left_pilot_filter : configuration work.notch_filter_down_to_device_level + port map ( input => left_decoded, output => left_filtered, + vdd => vdd, vss => vss, gnd => gnd ); + + -- ... + +end architecture top_level; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/index-ams.txt new file mode 100644 index 000000000..58e31b1be --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/index-ams.txt @@ -0,0 +1,47 @@ +--------------------------------------------------------------------------------------------------------------------------------------------- +-- Chapter 16 - Components and Configurations +--------------------------------------------------------------------------------------------------------------------------------------------- +-- Filename Primary Unit Secondary Unit Figure/Section +----------- ------------ -------------- -------------- +opamp.vhd entity bulk_cmos_nfet basic, detailed -- +-- entity opamp struct Figure 16-1 +automotive_valve_defs.vhd package automotive_valve_defs -- Figure 16-2 +automotive_valve.vhd entity automotive_valve test Figure 16-3 +brake_system.vhd entity brake_system structure Figure 16-4 +opamp_mosfets.vhd configuration opamp_mosfets -- Figure 16-5 +notch_filter.vhd entity notch_filter opamp_based Figure 16-6 +notch_filter_down_to_device_level.vhd configuration notch_filter_down_to_device_level -- Figure 16-7 +notch_filter_full.vhd configuration full -- Figure 16-8 +fm_radio.vhd entity fm_radio top_level Figure 16-9 +successive_approx_adc.vhd entity successive_approx_adc struct Figure 16-10 +sensor_interface.vhd entity sensor_interface structural Figure 16-11 +sensor_interface_with_timing.vhd configuration sensor_interface_with_timing -- Figure 16-12 +computer_system.vhd entity computer_system structure Figure 16-13 +decoder_3_to_8.vhd entity decoder_3_to_8 basic Figure 16-14 +computer_structure.vhd configuration computer_structure -- Figure 16-15 +single_board_computer.vhd entity single_board_computer structural Figure 16-17 +intermediate.vhd entity XYZ3000_cpu full_function -- +-- entity memory_array behavioral -- +-- configuration intermediate -- Figure 16-18 +logic_block.vhd entity nand3 behavioral -- +-- entity logic_block ideal Figure 16-19 +reg-1.vhd entity reg gate_level Figure 16-21 +control_section.vhd entity control_section structural Figure 16-20 +controller_with_timing-1.vhd configuration controller_with_timing -- Figure 16-22 +interlock_control.vhd entity not_gate primitive -- +-- entity interlock_control detailed_timing Figure 16-23 +interlock_control_with_estimates.vhd configuration interlock_control_with_estimates -- Figure 16-24 +-- configuration interlock_control_with_actual -- Figure 16-24 +misc_logic.vhd entity misc_logic gate_level Figure 16-25 +misc_logic_reconfigured.vhd configuration misc_logic_reconfigured -- Figure 16-26 +inline_02a.vhd configuration inline_02a -- Section 16.2 +inline_04a.vhd entity inline_04a test -- +-- configuration inline_04a_test -- Section 16.2 +inline_05.vhd entity inline_05 test Section 16.2 +-- entity nand2 -- Section 16.2 +-- configuration inline_05_test -- Section 16.2 +--------------------------------------------------------------------------------------------------------------------------------------------- +-- TestBenches +--------------------------------------------------------------------------------------------------------------------------------------------- +-- Filename Primary Unit Secondary Unit Tested Model +------------ ------------ -------------- ------------ diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/inline_02a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/inline_02a.vhd new file mode 100644 index 000000000..41f40cbbe --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/inline_02a.vhd @@ -0,0 +1,34 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +configuration inline_02a of opamp is + + for struct + + -- code from book (in text) + + for m1, m2 : nfet + use entity work.bulk_cmos_nfet(basic); + end for; + + -- end code from book + + end for; + +end configuration inline_02a; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/inline_04a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/inline_04a.vhd new file mode 100644 index 000000000..9447cb34a --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/inline_04a.vhd @@ -0,0 +1,57 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity inline_04a is +end entity inline_04a; + + +architecture test of inline_04a is + + component opamp is + port ( terminal plus_in, minus_in, output, vdd, vss, gnd : electrical ); + end component opamp; + + terminal plus_in, minus_in, output, vdd, vss, gnd : electrical; + +begin + + voltage_amp : component opamp + port map ( plus_in => plus_in, minus_in => minus_in, output => output, + vdd => vdd, vss => vss, gnd => gnd ); + +end architecture test; + + +configuration inline_04a_test of inline_04a is + + for test + + -- code from book (in text) + + for voltage_amp : opamp + use configuration work.opamp_mosfets; + end for; + + -- end code from book + + end for; + +end configuration inline_04a_test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/inline_05.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/inline_05.vhd new file mode 100644 index 000000000..ec39f8d0c --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/inline_05.vhd @@ -0,0 +1,74 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_05 is +end entity inline_05; + + +architecture test of inline_05 is + + -- code from book + + component nand3 is + port ( a, b, c : in bit := '1'; y : out bit ); + end component nand3; + + -- end code from book + + signal s1, s2, s3 : bit; + +begin + + -- code from book + + gate1 : component nand3 + port map ( a => s1, b => s2, c => open, y => s3 ); + + -- end code from book + +end architecture test; + + + +-- code from book + +entity nand2 is + port ( a, b : in bit := '1'; y : out bit ); +end entity nand2; + +-- end code from book + + + + +configuration inline_05_test of inline_05 is + + for test + + -- code from book + + for gate1 : nand3 + use entity work.nand2(basic); + end for; + + -- end code from book + + end for; + +end configuration inline_05_test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/interlock_control.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/interlock_control.vhd new file mode 100644 index 000000000..fe566b0e2 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/interlock_control.vhd @@ -0,0 +1,113 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee; use ieee.std_logic_1164.all; + +entity nor_gate is + generic ( width : positive; + Tpd01, Tpd10 : delay_length ); + port ( input : in std_logic_vector(0 to width - 1); + output : out std_logic ); +end entity nor_gate; + + +architecture primitive of nor_gate is + + function max ( a, b : delay_length ) return delay_length is + begin + if a > b then + return a; + else + return b; + end if; + end function max; + +begin + + reducer : process (input) is + variable result : std_logic; + begin + result := '0'; + for index in input'range loop + result := result or input(index); + end loop; + if not result = '1' then + output <= not result after Tpd01; + elsif not result = '0' then + output <= not result after Tpd10; + else + output <= not result after max(Tpd01, Tpd10); + end if; + end process reducer; + +end architecture primitive; + + +library ieee; use ieee.std_logic_1164.all; +library cell_lib; + +entity interlock_control is +end entity interlock_control; + + +-- code from book + +architecture detailed_timing of interlock_control is + + component nor_gate is + generic ( input_width : positive ); + port ( input : in std_logic_vector(0 to input_width - 1); + output : out std_logic ); + end component nor_gate; + + for ex_interlock_gate : nor_gate + use entity cell_lib.nor_gate(primitive) + generic map ( width => input_width, + Tpd01 => 250 ps, Tpd10 => 200 ps ); -- estimates + + -- . . . + + -- not in book + signal reg_access_hazard, load_hazard, stall_ex_n : std_logic; + -- end not in book + +begin + + ex_interlock_gate : component nor_gate + generic map ( input_width => 2 ) + port map ( input(0) => reg_access_hazard, + input(1) => load_hazard, + output => stall_ex_n); + + -- . . . + + -- not in book + + reg_access_hazard <= '0' after 10 ns, '1' after 20 ns, 'X' after 30 ns; + + load_hazard <= '0' after 2 ns, '1' after 4 ns, 'X' after 6 ns, + '0' after 12 ns, '1' after 14 ns, 'X' after 16 ns, + '0' after 22 ns, '1' after 24 ns, 'X' after 26 ns, + '0' after 32 ns, '1' after 34 ns, 'X' after 36 ns; + + -- end not in book + +end architecture detailed_timing; + +-- end code from book diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/interlock_control_with_estimates.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/interlock_control_with_estimates.vhd new file mode 100644 index 000000000..f6d4a51e6 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/interlock_control_with_estimates.vhd @@ -0,0 +1,44 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +configuration interlock_control_with_estimates of interlock_control is + + for detailed_timing + + end for; + + -- . . . + +end configuration interlock_control_with_estimates; + +-------------------------------------------------- + +configuration interlock_control_with_actual of interlock_control is + + for detailed_timing + + for ex_interlock_gate : nor_gate + generic map ( Tpd01 => 320 ps, Tpd10 => 230 ps ); + end for; + + -- . . . + + end for; + +end configuration interlock_control_with_actual; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/intermediate.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/intermediate.vhd new file mode 100644 index 000000000..53342b411 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/intermediate.vhd @@ -0,0 +1,76 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- analyze into resource library chips + +entity XYZ3000_cpu is + port ( clock : in bit; addr_data : inout bit_vector(31 downto 0); + other_port : in bit := '0' ); +end entity XYZ3000_cpu; + + +architecture full_function of XYZ3000_cpu is +begin +end architecture full_function; + + +-- analyze into work library + +entity memory_array is + port ( addr : in bit_vector(25 downto 0); other_port : in bit := '0' ); +end entity memory_array; + + +architecture behavioral of memory_array is +begin +end architecture behavioral; + + + +-- code from book + +library chips; + +configuration intermediate of single_board_computer is + + for structural + + for cpu : processor + use entity chips.XYZ3000_cpu(full_function) + port map ( clock => clk, addr_data => a_d, -- . . . ); + -- not in book + other_port => open ); + -- end not in book + end for; + + for main_memory : memory + use entity work.memory_array(behavioral); + end for; + + for all : serial_interface + use open; + end for; + + -- . . . + + end for; + +end configuration intermediate; + +-- end code from book diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/logic_block.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/logic_block.vhd new file mode 100644 index 000000000..a1d95b85c --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/logic_block.vhd @@ -0,0 +1,75 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- code from book (in text) + +entity nand3 is + port ( a, b, c : in bit; y : out bit ); +end entity nand3; + +-- end code from book + +architecture behavioral of nand3 is +begin + y <= not (a and b and c); +end architecture behavioral; + + + +entity logic_block is +end entity logic_block; + + +-- code from book + +library gate_lib; + +architecture ideal of logic_block is + + component nand2 is + port ( in1, in2 : in bit; result : out bit ); + end component nand2; + + for all : nand2 + use entity gate_lib.nand3(behavioral) + port map ( a => in1, b => in2, c => '1', y => result ); + + -- . . . -- other declarations + + -- not in book + signal s1, s2, s3 : bit := '0'; + +begin + + gate1 : component nand2 + port map ( in1 => s1, in2 => s2, result => s3 ); + + -- . . . -- other concurrent statements + + -- not in book + + s1 <= '1' after 20 ns; + + s2 <= '1' after 10 ns, '0' after 20 ns, '1' after 30 ns; + + -- end not in book + +end architecture ideal; + +-- end code from book diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/misc_logic.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/misc_logic.vhd new file mode 100644 index 000000000..da51c5802 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/misc_logic.vhd @@ -0,0 +1,64 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library project_lib; +library util; use util.stimulus_generators.all; + +entity misc_logic is +end entity misc_logic; + + +-- code from book + +architecture gate_level of misc_logic is + + component nand3 is + generic ( Tpd : delay_length ); + port ( a, b, c : in bit; y : out bit ); + end component nand3; + + for all : nand3 + use entity project_lib.nand3(basic); + + -- . . . + + -- not in book + signal sig1, sig2, sig3, out_sig : bit; + signal test_vector : bit_vector(1 to 3); + -- end not in book + +begin + + gate1 : component nand3 + generic map ( Tpd => 2 ns ) + port map ( a => sig1, b => sig2, c => sig3, y => out_sig ); + + -- . . . + + -- not in book + + all_possible_values(test_vector, 10 ns); + + (sig1, sig2, sig3) <= test_vector; + + -- end not in book + +end architecture gate_level; + +-- end code from book diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/misc_logic_reconfigured.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/misc_logic_reconfigured.vhd new file mode 100644 index 000000000..7a4a73519 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/misc_logic_reconfigured.vhd @@ -0,0 +1,31 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +configuration misc_logic_reconfigured of misc_logic is + + for gate_level + + for gate1 : nand3 + generic map ( Tpd => 1.6 ns ) + port map ( a => c, c => a, b => b, y => y ); + end for; + + end for; + +end configuration misc_logic_reconfigured; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/notch_filter.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/notch_filter.vhd new file mode 100644 index 000000000..00842f4c4 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/notch_filter.vhd @@ -0,0 +1,54 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity notch_filter is + port ( terminal input, output, vdd, vss, gnd : electrical ); +end entity notch_filter; + +---------------------------------------------------------------- + +architecture opamp_based of notch_filter is + + component simple_opamp is + port ( terminal plus_in, minus_in, output, vdd, vss, gnd : electrical ); + end component simple_opamp; + -- ... + + terminal opamp1_in, opamp1_out, opamp2_in, -- ... + -- not in book + other_terminal + -- end not in book + : electrical; + +begin + + opamp1 : component simple_opamp + port map ( plus_in => gnd, minus_in => opamp1_in, output => opamp1_out, + vdd => vdd, vss => vss, gnd => gnd ); + + opamp2 : component simple_opamp + port map ( plus_in => gnd, minus_in => opamp2_in, output => output, + vdd => vdd, vss => vss, gnd => gnd ); + + -- other component instances + -- ... + +end architecture opamp_based; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/notch_filter_down_to_device_level.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/notch_filter_down_to_device_level.vhd new file mode 100644 index 000000000..0d3098039 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/notch_filter_down_to_device_level.vhd @@ -0,0 +1,32 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +configuration notch_filter_down_to_device_level of notch_filter is + + for opamp_based + + for all : simple_opamp + use configuration work.opamp_mosfets; + end for; + + -- ... -- bindings for other component instances + + end for; -- end of architecture opamp_based + +end configuration notch_filter_down_to_device_level; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/notch_filter_full.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/notch_filter_full.vhd new file mode 100644 index 000000000..93eee766a --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/notch_filter_full.vhd @@ -0,0 +1,49 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library cmos_lib; use cmos_lib.bulk_cmos_nfet; + +configuration full of notch_filter is + + for opamp_based -- architecture of notch_filter + + for all : simple_opamp + use entity work.opamp(struct); + + for struct -- architecture of opamp + + for m1, m2 : nfet + use entity bulk_cmos_nfet(detailed); + end for; + + for others : nfet + use entity bulk_cmos_nfet(basic); + end for; + + -- ... + + end for; -- end of architecture struct + + end for; + + -- ... -- bindings for other component instances + + end for; -- end of architecture opamp_based + +end configuration full; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/opamp.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/opamp.vhd new file mode 100644 index 000000000..f6805923e --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/opamp.vhd @@ -0,0 +1,78 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity bulk_cmos_nfet is + generic ( Vt : real; + transconductance : real ); + port ( terminal gate, drain, source : electrical ); +end entity bulk_cmos_nfet; + + +architecture basic of bulk_cmos_nfet is +begin +end architecture basic; + + +architecture detailed of bulk_cmos_nfet is +begin +end architecture detailed; + + +-- code from book + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity opamp is + port ( terminal plus_in, minus_in, output, vdd, vss, gnd : electrical ); +end entity opamp; + +---------------------------------------------------------------- + +architecture struct of opamp is + + component nfet is + generic ( Vt : real; + transconductance : real ); + port ( terminal gate, drain, source : electrical ); + end component nfet; + + terminal int_1, int_2, int_3, -- ... + -- not in book + other_terminal + -- end not in book + : electrical; + +begin + + m1 : component nfet + generic map ( Vt => 0.026, transconductance => 1.0 ) + port map ( gate => plus_in, drain => int_1, source => int_2 ); + + m2 : component nfet + generic map ( Vt => 0.026, transconductance => 1.0 ) + port map ( gate => minus_in, drain => int_1, source => int_3 ); + + -- other component instances + -- ... + +end architecture struct; + +-- end code from book diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/opamp_mosfets.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/opamp_mosfets.vhd new file mode 100644 index 000000000..42f238294 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/opamp_mosfets.vhd @@ -0,0 +1,39 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library cmos_lib; +use cmos_lib.bulk_cmos_nfet; + +configuration opamp_mosfets of opamp is + + for struct -- architecture of opamp + + for m1, m2 : nfet + use entity bulk_cmos_nfet(detailed); + end for; + + for others : nfet + use entity bulk_cmos_nfet(basic); + end for; + + -- ... + + end for; -- end of architecture struct + +end configuration opamp_mosfets; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/reg-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/reg-1.vhd new file mode 100644 index 000000000..445b8888a --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/reg-1.vhd @@ -0,0 +1,50 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee; use ieee.std_logic_1164.all; + +entity reg is + generic ( t_setup, t_hold, t_pd : delay_length; + width : positive ); + port ( clock : in std_logic; + reset_n : in std_logic := 'H'; + data_in : in std_logic_vector(0 to width - 1); + data_out : out std_logic_vector(0 to width - 1) ); +end entity reg; + + + +-- not in book + +architecture gate_level of reg is + +begin + + store : process (clock, reset_n) is + begin + if reset_n = '0' or reset_n = 'L' then + data_out <= (others => '0') after t_pd; + elsif rising_edge(clock) then + data_out <= data_in after t_pd; + end if; + end process store; + +end architecture gate_level; + +-- end not in book diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/sensor_interface.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/sensor_interface.vhd new file mode 100644 index 000000000..d676652b3 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/sensor_interface.vhd @@ -0,0 +1,64 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- not in book + +library ieee; use ieee.std_logic_1164.all; +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity sensor_interface is + +end entity sensor_interface; + +-- end not in book + + + +architecture structural of sensor_interface is + + component adc is + generic ( width : positive ); + port ( terminal analog_in : electrical; + signal clock : in std_logic; + signal start : in std_logic; + signal eoc : out std_logic; + signal data_out : out std_logic_vector(0 to width - 1) ); + end component adc; + + -- ... + + -- not in book + terminal sensor_input : electrical; + signal clk, start_conversion, end_conversion : std_logic; + signal sensor_data : std_logic_vector(0 to 7); + -- end not in book + +begin + + sensor_adc : component adc + generic map ( width => sensor_data'length ) + port map ( analog_in => sensor_input, + clock => clk, + start => start_conversion, + eoc => end_conversion, + data_out => sensor_data ); + + -- ... + +end architecture structural; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/sensor_interface_with_timing.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/sensor_interface_with_timing.vhd new file mode 100644 index 000000000..c7a03a394 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/sensor_interface_with_timing.vhd @@ -0,0 +1,34 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +configuration sensor_interface_with_timing of sensor_interface is + + for structural + + for sensor_adc : adc + use entity work.successive_approx_adc(struct) + generic map ( t_setup => 200 ps, t_hold => 150 ps, t_pd => 150 ps, + width => width ); + end for; + + -- ... + + end for; + +end configuration sensor_interface_with_timing; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/single_board_computer.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/single_board_computer.vhd new file mode 100644 index 000000000..10be48856 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/single_board_computer.vhd @@ -0,0 +1,81 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- not in book +entity single_board_computer is +end entity single_board_computer; +-- end not in book + + +architecture structural of single_board_computer is + + -- . . . -- type and signal declarations + + -- not in book + + subtype word is bit_vector(31 downto 0); + signal sys_clk : bit; + signal cpu_a_d, latched_addr : word; + + -- end not in book + + component processor is + port ( clk : in bit; a_d : inout word; -- . . . ); + -- not in book + other_port : in bit := '0' ); + -- end not in book + end component processor; + + component memory is + port ( addr : in bit_vector(25 downto 0); -- . . . ); + -- not in book + other_port : in bit := '0' ); + -- end not in book + end component memory; + + component serial_interface is + port ( clk : in bit; address : in bit_vector(3 downto 0); -- . . . ); + -- not in book + other_port : in bit := '0' ); + -- end not in book + end component serial_interface; + +begin + + cpu : component processor + port map ( clk => sys_clk, a_d => cpu_a_d, -- . . . ); + -- not in book + other_port => open ); + -- end not in book + + main_memory : component memory + port map ( addr => latched_addr(25 downto 0), -- . . . ); + -- not in book + other_port => open ); + -- end not in book + + serial_interface_a : component serial_interface + port map ( clk => sys_clk, address => latched_addr(3 downto 0), -- . . . ); + -- not in book + other_port => open ); + -- end not in book + + -- . . . + +end architecture structural; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/successive_approx_adc.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/successive_approx_adc.vhd new file mode 100644 index 000000000..18de7922e --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/successive_approx_adc.vhd @@ -0,0 +1,40 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee; use ieee.std_logic_1164.all; +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity successive_approx_adc is + generic ( t_setup, t_hold, t_pd : delay_length; + width : positive ); + port ( terminal analog_in : electrical; + signal clock : in std_logic; + signal start : in std_logic; + signal eoc : out std_logic; + signal data_out : out std_logic_vector(0 to width - 1) ); +end entity successive_approx_adc; + + +-- not in book + +architecture struct of successive_approx_adc is + +begin + +end architecture struct; |