diff options
Diffstat (limited to 'testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups')
27 files changed, 1729 insertions, 0 deletions
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/74x138.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/74x138.vhd new file mode 100644 index 000000000..dd3f90210 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/74x138.vhd @@ -0,0 +1,53 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +package physical_attributes is + + -- code from book (in text) + + attribute layout_ignore : boolean; + attribute pin_number : positive; + + -- end code from book + +end package physical_attributes; + + +-- code from book + +library ieee; use ieee.std_logic_1164.all; +use work.physical_attributes.all; + +entity \74x138\ is + generic ( Tpd : time ); + port ( en1, en2a_n, en2b_n : in std_logic; + s0, s1, s2 : in std_logic; + y0, y1, y2, y3, y4, y5, y6, y7 : out std_logic ); + + attribute layout_ignore of Tpd : constant is true; + + attribute pin_number of s0 : signal is 1; + attribute pin_number of s1 : signal is 2; + attribute pin_number of s2 : signal is 3; + attribute pin_number of en2a_n : signal is 4; + -- . . . + +end entity \74x138\; + +-- code from book diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/CPU.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/CPU.vhd new file mode 100644 index 000000000..a475d11c9 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/CPU.vhd @@ -0,0 +1,72 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +package cell_attributes is + + type length is range 0 to integer'high + units nm; + um = 1000 nm; + mm = 1000 um; + mil = 25400 nm; + end units length; + + type coordinate is record + x, y : length; + end record coordinate; + + attribute cell_position : coordinate; + +end package cell_attributes; + + + +entity CPU is +end entity CPU; + + +-- code from book + +architecture cell_based of CPU is + + component fpu is + port ( -- . . . ); + -- not in book + port_name : bit := '0' ); + -- end not in book + end component; + + use work.cell_attributes.all; + + attribute cell_position of the_fpu : label is ( 540 um, 1200 um ); + + -- . . . + +begin + + the_fpu : component fpu + port map ( -- . . . ); + -- not in book + port_name => open ); + -- end not in book + + -- . . . + +end architecture cell_based; + +-- end code from book diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/add_with_overflow.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/add_with_overflow.vhd new file mode 100644 index 000000000..dd06f91a6 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/add_with_overflow.vhd @@ -0,0 +1,68 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity add_with_overflow is +end entity add_with_overflow; + + +architecture test of add_with_overflow is +begin + +-- code from book + +process is + + procedure add_with_overflow ( a, b : in integer; + sum : out integer; + overflow : out boolean ) is -- . . . + + -- not in book + begin + end; + -- end not in book + + procedure add_with_overflow ( a, b : in bit_vector; + sum : out bit_vector; + overflow : out boolean ) is -- . . . + + -- not in book + begin + end; + -- end not in book + + attribute built_in : string; + + attribute built_in of + add_with_overflow [ integer, integer, + integer, boolean ] : procedure is "int_add_overflow"; + + attribute built_in of + add_with_overflow [ bit_vector, bit_vector, + bit_vector, boolean ] : procedure is "bit_vector_add_overflow"; + +begin + -- . . . + -- not in book + wait; + -- end not in book +end process; + +-- end code from book + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/bottom.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/bottom.vhd new file mode 100644 index 000000000..0ddddd90c --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/bottom.vhd @@ -0,0 +1,87 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity bottom is + port ( -- . . . ); + -- + port_name : in bit := '0' ); + -- +end entity bottom; + +-------------------------------------------------- + +architecture bottom_arch of bottom is + + signal bot_sig : -- . . .; -- 5 + -- + bit; + -- + + procedure proc ( -- . . . ) is + -- + param_name : in bit := '0' ) is + -- + variable v : -- . . .; -- 6 + -- + bit; + -- + begin + -- . . . + -- + report "--6: " & v'path_name; + report "--6: " & v'instance_name; + -- + end procedure proc; + +begin + + delays : block is + constant d : integer := 1; -- 7 + begin + -- . . . + -- + assert false report "--7: " & d'path_name; + assert false report "--7: " & d'instance_name; + -- + end block delays; + + func : block is + begin + + process is + variable v : -- . . .; -- 8 + -- + bit; + -- + begin + -- . . . + -- + report "--5: " & bot_sig'path_name; + report "--5: " & bot_sig'instance_name; + report "--8: " & v'path_name; + report "--8: " & v'instance_name; + proc(param_name => open); + wait; + -- + -- + end process; + + end block func; + +end architecture bottom_arch; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/clock_buffer.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/clock_buffer.vhd new file mode 100644 index 000000000..31683f7e7 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/clock_buffer.vhd @@ -0,0 +1,53 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +package constraints is + + -- code from book (in text) + + group port_pair is ( signal, signal ); + + attribute max_prop_delay : time; + + -- end code from book + +end package constraints; + + + +-- code from book + +library ieee; use ieee.std_logic_1164.all; +use work.constraints.port_pair, work.constraints.max_prop_delay; + +entity clock_buffer is + port ( clock_in : in std_logic; + clock_out1, clock_out2, clock_out3 : out std_logic ); + + group clock_to_out1 : port_pair ( clock_in, clock_out1 ); + group clock_to_out2 : port_pair ( clock_in, clock_out2 ); + group clock_to_out3 : port_pair ( clock_in, clock_out3 ); + + attribute max_prop_delay of clock_to_out1 : group is 2 ns; + attribute max_prop_delay of clock_to_out2 : group is 2 ns; + attribute max_prop_delay of clock_to_out3 : group is 2 ns; + +end entity clock_buffer; + +-- end code from book diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/controller.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/controller.vhd new file mode 100644 index 000000000..c1953b5c3 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/controller.vhd @@ -0,0 +1,50 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity controller is +end entity controller; + + +architecture test of controller is + + signal clk : bit; + + attribute synthesis_hint : string; + +begin + + -- code from book + + controller : process is + + attribute synthesis_hint of control_loop : label is + "implementation:FSM(clk)"; + -- . . . + + begin + -- . . . -- initialization + control_loop : loop + wait until clk = '1'; + -- . . . + end loop; + end process controller; + + -- end code fom book + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/display_interface.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/display_interface.vhd new file mode 100644 index 000000000..a2795917e --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/display_interface.vhd @@ -0,0 +1,41 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +package display_interface is + + -- . . . + + -- not in book + type status_type is (t1, t2, t3); + -- end not in book + + procedure create_window ( size_x, size_y : natural; + status : out status_type ); + + attribute foreign of create_window : procedure is + "language Ada; with window_operations;" & + "bind to window_operations.create_window;" & + "parameter size_x maps to size_x : in natural;" & + "parameter size_y maps to size_y : in natural;" & + "parameter status maps to status : out window_operations.status_type;" & + "others map to default"; + + -- . . . + +end package display_interface; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/flipflop.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/flipflop.vhd new file mode 100644 index 000000000..53d6c3bc2 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/flipflop.vhd @@ -0,0 +1,44 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity flipflop is + generic ( Tsetup : delay_length ); + port ( clk, d : in bit; q : out bit ); +end entity flipflop; + + +-- code from book + +architecture behavior of flipflop is +begin + + timing_check : process (clk) is + begin + if clk = '1' then + assert d'last_event >= Tsetup + report "set up violation detected in " & timing_check'path_name + severity error; + end if; + end process timing_check; + + -- . . . -- functionality + +end architecture behavior; + +-- end code from book diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/gate_components.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/gate_components.vhd new file mode 100644 index 000000000..271dbbd9d --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/gate_components.vhd @@ -0,0 +1,53 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- analyze into resource library graphics + +package graphics_pkg is + + attribute graphic_symbol : string; + attribute graphic_style : string; + +end package graphics_pkg; + + + +-- code from book + +library ieee; use ieee.std_logic_1164.all; +library graphics; + +package gate_components is + + use graphics.graphics_pkg.graphic_symbol, + graphics.graphics_pkg.graphic_style; + + component and2 is + generic ( prop_delay : delay_length ); + port ( a, b : in std_logic; y : out std_logic ); + end component and2; + + attribute graphic_symbol of and2 : component is "and2"; + attribute graphic_style of and2 : component is "color:default, weight:bold"; + + -- . . . + +end package gate_components; + +-- end code from book diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/index-ams.txt new file mode 100644 index 000000000..90d6c36ec --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/index-ams.txt @@ -0,0 +1,48 @@ +--------------------------------------------------------------------------------------------------------------------------------------------- +-- Chapter 22 - Attributes and Groups +--------------------------------------------------------------------------------------------------------------------------------------------- +-- Filename Primary Unit Secondary Unit Figure/Section +----------- ------------ -------------- -------------- +flipflop.vhd entity flipflop behavior Figure 22-8 +mem_pkg.vhd package mem_pkg body Figure 22-9 +top.vhd entity top top_arch Figure 22-10 +bottom.vhd entity bottom bottom_arch Figure 22-12 +add_with_overflow.vhd entity add_with_overflow test Figure 22-14 +74x138.vhd package physical_attributes -- Section 22.2 +-- entity \74x138\ -- Figure 22-15 +mem_read.vhd entity mem_read test Figure 22-16 +gate_components.vhd package graphics_pkg -- -- +-- package gate_components -- Figure 22-17 +CPU.vhd package cell_attributes -- -- +-- entity CPU cell_based Figure 22-18 +controller.vhd entity controller test Figure 22-19 +voltage_defs.vhd package voltage_defs -- Figure 22-20 +sequencer.vhd package timing_attributes -- -- +-- entity sequencer structural Figure 22-21 +display_interface.vhd package display_interface -- Figure 22-22 +clock_buffer.vhd package constraints -- Section 20.3 +-- entity clock_buffer -- Figure 20-23 +inline_01.vhd package utility_definitions -- -- +-- entity inline_01 test Section 22.1 +inline_02.vhd entity inline_02 test Section 22.1 +inline_03.vhd package inline_03_defs -- Section 22.2 +-- entity inline_03 test Section 22.2 +inline_04.vhd package inline_04 -- -- +-- entity flipflop std_cell Section 22.2 +-- package model_utilities -- Section 22.2 +inline_05.vhd entity inline_05 test Section 22.2 +inline_06.vhd entity inline_06 test Section 22.2 +inline_07.vhd entity inline_07 test Section 22.2 +inline_08.vhd entity inline_08 test Section 22.2 +inline_09.vhd package inline_09_defs -- -- +-- entity e arch -- +-- entity inline_09 test Section 22.2 +inline_10.vhd package inline_10 -- Section 22.2 +-- entity and2 accelerated Section 22.2 +inline_11.vhd entity inline_11 test Section 22.3 +--------------------------------------------------------------------------------------------------------------------------------------------- +-- TestBenches +--------------------------------------------------------------------------------------------------------------------------------------------- +-- Filename Primary Unit Secondary Unit Tested Model +------------ ------------ -------------- ------------ +tb_flipflop.vhd entity tb_flipflop test flipflop.vhd diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_01.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_01.vhd new file mode 100644 index 000000000..7516d539c --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_01.vhd @@ -0,0 +1,61 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- analyze into resource library utilities + +package utility_definitions is + + constant word_size : natural := 16; + +end package utility_definitions; + + + +library utilities; + +entity inline_01 is + +end entity inline_01; + + +---------------------------------------------------------------- + + +architecture test of inline_01 is +begin + + + process is + begin + + report + + -- code from book: + + utilities.utility_definitions.word_size'simple_name + + -- end of code from book + + ; + + wait; + end process; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_02.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_02.vhd new file mode 100644 index 000000000..36f102d64 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_02.vhd @@ -0,0 +1,69 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library project; + +entity inline_02 is +end entity inline_02; + + +architecture test of inline_02 is +begin + + process is + + use project.mem_pkg; + use project.mem_pkg.all; + variable words : word_array(0 to 3); + + begin + assert + -- code from book (in text) + mem_pkg'path_name = ":project:mem_pkg:" + -- end code from book + ; + report mem_pkg'path_name; + + assert + -- code from book (in text) + word'path_name = ":project:mem_pkg:word" + -- end code from book + ; + report word'path_name; + + assert + -- code from book (in text) + word_array'path_name = ":project:mem_pkg:word_array" + -- end code from book + ; + + report word_array'path_name; + + assert + -- code from book (in text) + load_array'path_name = ":project:mem_pkg:load_array" + -- end code from book + ; + report load_array'path_name; + + load_array(words, "/dev/null"); + wait; + end process; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_03.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_03.vhd new file mode 100644 index 000000000..749cbee36 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_03.vhd @@ -0,0 +1,102 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +package inline_03_defs is + + -- code from book: + + attribute cell_name : string; + attribute pin_number : positive; + attribute max_wire_delay : delay_length; + attribute encoding : bit_vector; + + + type length is range 0 to integer'high + units nm; + um = 1000 nm; + mm = 1000 um; + mil = 25400 nm; + end units length; + + type coordinate is record + x, y : length; + end record coordinate; + + attribute cell_position : coordinate; + + -- end of code from book + +end package inline_03_defs; + + + + +entity inline_03 is + +end entity inline_03; + + +---------------------------------------------------------------- + + +architecture std_cell of inline_03 is + + use work.inline_03_defs.all; + + signal enable, clk : bit; + + type state_type is (idle_state, other_state); + + -- code from book: + + attribute cell_name of std_cell : architecture is "DFF_SR_QQNN"; + attribute pin_number of enable : signal is 14; + attribute max_wire_delay of clk : signal is 50 ps; + attribute encoding of idle_state : literal is b"0000"; + attribute cell_position of the_fpu : label is ( 540 um, 1200 um ); + + -- end of code from book + +begin + + the_fpu : block is + begin + end block the_fpu; + + process is + use std.textio.all; + variable L : line; + begin + write(L, std_cell'cell_name); + writeline(output, L); + write(L, enable'pin_number); + writeline(output, L); + write(L, clk'max_wire_delay); + writeline(output, L); + write(L, idle_state[return state_type]'encoding); + writeline(output, L); + write(L, length'image(the_fpu'cell_position.x)); + write(L, ' '); + write(L, length'image(the_fpu'cell_position.y)); + writeline(output, L); + + wait; + end process; + +end architecture std_cell; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_04.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_04.vhd new file mode 100644 index 000000000..5cd9ec28b --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_04.vhd @@ -0,0 +1,63 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +package inline_04 is + + attribute cell_name : string; + +end package inline_04; + + + +entity flipflop is + +end entity flipflop; + + + +use work.inline_04.all; + +-- code from book: + +architecture std_cell of flipflop is + + attribute cell_name of std_cell : architecture is "DFF_SR_QQNN"; + + -- . . . -- other declarations + +begin + -- . . . +end architecture std_cell; + +-- end of code from book + + + +-- code from book: + +package model_utilities is + + attribute optimize : string; + attribute optimize of model_utilities : package is "level_4"; + + -- . . . + +end package model_utilities; + +-- end of code from book diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_05.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_05.vhd new file mode 100644 index 000000000..340664b08 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_05.vhd @@ -0,0 +1,68 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_05 is + +end entity inline_05; + + +---------------------------------------------------------------- + + +architecture test of inline_05 is + + type stimulus_list is array (natural range <>) of integer; + + + -- code from book: + + function "&" ( a, b : stimulus_list ) return stimulus_list; + + attribute debug : string; + attribute debug of + "&" [ stimulus_list, stimulus_list return stimulus_list ] : function is + "source_statement_step"; + + + type mvl is ('X', '0', '1', 'Z'); + type mvl_vector is array ( integer range <>) of mvl; + function resolve_mvl ( drivers : mvl_vector ) return mvl; + + subtype resolved_mvl is resolve_mvl mvl; + + + type builtin_types is (builtin_bit, builtin_mvl, builtin_integer); + attribute builtin : builtin_types; + + attribute builtin of resolved_mvl : subtype is builtin_mvl; + + -- end of code from book + + function "&" ( a, b : stimulus_list ) return stimulus_list is + begin + return stimulus_list'(1 to 0 => 0); + end function "&"; + + function resolve_mvl ( drivers : mvl_vector ) return mvl is + begin + return drivers(drivers'left); + end function resolve_mvl; + +begin +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_06.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_06.vhd new file mode 100644 index 000000000..2d0b8758e --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_06.vhd @@ -0,0 +1,85 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_06 is + +end entity inline_06; + + +---------------------------------------------------------------- + +use std.textio.all; + +architecture test of inline_06 is + + subtype encoding_type is bit_vector(1 downto 0); + attribute encoding : encoding_type; + +begin + + + process1 : process is + + -- code from book: + + type controller_state is (idle, active, fail_safe); + type load_level is (idle, busy, overloaded); + + attribute encoding of idle [ return controller_state ] : literal is b"00"; + attribute encoding of active [ return controller_state ] : literal is b"01"; + attribute encoding of fail_safe [ return controller_state ] : literal is b"10"; + + -- end of code from book + + variable L : line; + + begin + write(L, string'("process1")); + writeline(output, L); + write(L, idle [ return controller_state ] ' encoding); + writeline(output, L); + write(L, active [ return controller_state ] ' encoding); + writeline(output, L); + write(L, fail_safe [ return controller_state ] ' encoding); + writeline(output, L); + wait; + end process process1; + + + process2 : process is + + type controller_state is (idle, active, fail_safe); + type load_level is (idle, busy, overloaded); + + attribute encoding of idle : literal is b"11"; + + variable L : line; + + begin + write(L, string'("process2")); + writeline(output, L); + write(L, idle [ return controller_state ] ' encoding); + writeline(output, L); + write(L, idle [ return load_level ] ' encoding); + writeline(output, L); + wait; + end process process2; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_07.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_07.vhd new file mode 100644 index 000000000..6ed29d90a --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_07.vhd @@ -0,0 +1,62 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_07 is + +end entity inline_07; + + +---------------------------------------------------------------- + + +architecture test of inline_07 is + + component multiplier is + end component multiplier; + + type length is range 0 to integer'high + units nm; + um = 1000 nm; + mm = 1000 um; + mil = 25400 nm; + end units length; + + type coordinate is record + x, y : length; + end record coordinate; + + type orientation_type is (up, down, left, right); + + attribute cell_allocation : string; + attribute cell_position : coordinate; + attribute cell_orientation : orientation_type; + + -- code from book: + + attribute cell_allocation of mult : label is "wallace_tree_multiplier"; + attribute cell_position of mult : label is ( 1200 um, 4500 um ); + attribute cell_orientation of mult : label is down; + + -- end of code from book + +begin + + mult : component multiplier; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_08.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_08.vhd new file mode 100644 index 000000000..20050940e --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_08.vhd @@ -0,0 +1,117 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_08 is + +end entity inline_08; + + +---------------------------------------------------------------- + + +library ieee; use ieee.std_logic_1164.all; + +architecture std_cell of inline_08 is + + attribute cell_name : string; + attribute pin_number : positive; + attribute max_wire_delay : delay_length; + attribute encoding : bit_vector; + + type length is range 0 to integer'high + units nm; + um = 1000 nm; + mm = 1000 um; + mil = 25400 nm; + end units length; + + type coordinate is record + x, y : length; + end record coordinate; + + attribute cell_position : coordinate; + + type built_in_type is (bv_incr, std_incr); + attribute built_in : built_in_type; + + signal enable, clk : bit; + + type state_type is (idle_state, other_state); + + type speed_range is (high, other_speed); + type coolant_level is (high, other_level); + + attribute representation : string; + + function increment ( vector : in bit_vector ) return bit_vector is + begin + end; + + function increment ( vector : in std_logic_vector ) return std_logic_vector is + begin + end; + + attribute cell_name of std_cell : architecture is "DFF_SR_QQNN"; + attribute pin_number of enable : signal is 14; + attribute max_wire_delay of clk : signal is 50 ps; + attribute encoding of idle_state : literal is b"0000"; + attribute cell_position of the_fpu : label is ( 540 um, 1200 um ); + attribute built_in of + increment [ bit_vector return bit_vector ] : function is bv_incr; + attribute built_in of + increment [ std_logic_vector return std_logic_vector ] : function is std_incr; + attribute representation of high [ return speed_range ] : literal is "byte"; + attribute representation of high [ return coolant_level ] : literal is "word"; + +begin + + the_fpu : block is + begin + end block the_fpu; + + process is + variable v1 : string(1 to 11); + variable v2 : positive; + variable v3 : time; + variable v4 : bit_vector(0 to 3); + variable v5 : coordinate; + variable v6, v7 : built_in_type; + variable v8, v9 : string(1 to 4); + begin + + -- code from book included... + + v1 := std_cell'cell_name ; + v2 := enable'pin_number ; + v3 := clk'max_wire_delay ; + v4 := idle_state'encoding ; + v5 := the_fpu'cell_position ; + + v6 := increment [ bit_vector return bit_vector ] 'built_in ; + v7 := increment [ std_logic_vector return std_logic_vector ] 'built_in ; + + v8 := high [ return speed_range ] 'representation ; + v9 := high [ return coolant_level ] 'representation ; + + -- end code from book + + wait; + end process; + +end architecture std_cell; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_09.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_09.vhd new file mode 100644 index 000000000..7ecccaaca --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_09.vhd @@ -0,0 +1,67 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +package inline_09_defs is + + attribute attr : integer; + +end package inline_09_defs; + + + +use work.inline_09_defs.all; + +entity e is + port ( p : in bit ); + attribute attr of p : signal is 1; +end entity e; + + +architecture arch of e is +begin + + assert false report integer'image(p'attr); + +end architecture arch; + + + +use work.inline_09_defs.all; + +entity inline_09 is +end entity inline_09; + + + +architecture test of inline_09 is + + signal s : bit; + + attribute attr of s : signal is 2; + +begin + + -- code from book + + c1 : entity work.e(arch) + port map ( p => s ); + + -- end code from book + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_10.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_10.vhd new file mode 100644 index 000000000..267f4aeef --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_10.vhd @@ -0,0 +1,44 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +package inline_10 is + + -- code from book + + attribute foreign : string; + + -- end code from book + +end package inline_10; + + + +entity and2 is +end entity and2; + + +-- code from book + +architecture accelerated of and2 is + attribute foreign of accelerated : architecture is + "accelerate/function:and_2in/nocheck"; +begin +end architecture accelerated; + +-- end code from book diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_11.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_11.vhd new file mode 100644 index 000000000..11d66caf9 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_11.vhd @@ -0,0 +1,67 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_11 is + +end entity inline_11; + + +---------------------------------------------------------------- + + +architecture test of inline_11 is + + component comp is + end component comp; + + signal clk_phase1, clk_phase2 : bit; + + -- code from book: + + group signal_pair is (signal, signal); + + group clock_pair : signal_pair ( clk_phase1, clk_phase2 ); + + attribute max_skew : time; + + attribute max_skew of clock_pair : group is 200 ps; + + group component_instances is ( label <> ); + + group U1 : component_instances ( nand1, nand2, nand3 ); + group U2 : component_instances ( inv1, inv2 ); + + attribute IC_allocation : string; + + attribute IC_allocation of U1 : group is "74LS00"; + attribute IC_allocation of U2 : group is "74LS04"; + + -- end of code from book + +begin + + + nand1 : component comp; + nand2 : component comp; + nand3 : component comp; + inv1 : component comp; + inv2 : component comp; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/mem_pkg.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/mem_pkg.vhd new file mode 100644 index 000000000..39655036a --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/mem_pkg.vhd @@ -0,0 +1,63 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +package mem_pkg is + + subtype word is bit_vector(0 to 31); + type word_array is array (natural range <>) of word; + + procedure load_array ( words : out word_array; file_name : string ); + +end package mem_pkg; + +-------------------------------------------------- + +package body mem_pkg is + + procedure load_array ( words : out word_array; file_name : string ) is + -- words'path_name = ":project:mem_pkg:load_array:words" + + use std.textio.all; + file load_file : text open read_mode is file_name; + -- load_file'path_name = ":project:mem_pkg:load_array:load_file" + + procedure read_line is + -- read_line'path_name = ":project:mem_pkg:load_array:read_line:" + variable current_line : line; + -- current_line'path_name = + -- ":project:mem_pkg:load_array:read_line:current_line" + begin + -- . . . + -- not in book + report current_line'path_name; + -- end not in book + end procedure read_line; + + begin -- load_array + -- . . . + -- not in book + report mem_pkg'path_name; + report words'path_name; + report load_file'path_name; + report read_line'path_name; + read_line; + -- end not in book + end procedure load_array; + +end package body mem_pkg; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/mem_read.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/mem_read.vhd new file mode 100644 index 000000000..a320a42a0 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/mem_read.vhd @@ -0,0 +1,71 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity mem_read is +end entity mem_read; + + +architecture test of mem_read is + + attribute trace : string; + + subtype byte is bit_vector(7 downto 0); + type byte_vector is array (natural range <>) of byte; + + type ram_bus is record + d : byte; + cmd, status, clk : bit; + end record ram_bus; + + -- code from book + + procedure mem_read ( address : in natural; + result : out byte_vector; + signal memory_bus : inout ram_bus ) is + + attribute trace of address : constant is "integer/hex"; + attribute trace of result : variable is "byte/multiple/hex"; + attribute trace of memory_bus : signal is + "custom/command=rambus.cmd"; + -- . . . + + begin + -- . . . + -- not in book + report address'trace; + report result'trace; + report memory_bus'trace; + -- end not in book + end procedure mem_read; + + -- end code from book + + signal memory_bus : ram_bus; + +begin + + process is + variable address : natural; + variable result : byte_vector(0 to 3); + begin + mem_read ( address, result, memory_bus ); + wait; + end process; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/sequencer.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/sequencer.vhd new file mode 100644 index 000000000..f35a75a02 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/sequencer.vhd @@ -0,0 +1,59 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +package timing_attributes is + + attribute max_wire_delay : delay_length; + +end package timing_attributes; + + +entity sequencer is +end entity sequencer; + + +-- code from book + +library ieee; use ieee.std_logic_1164.all; +use work.timing_attributes.all; + +architecture structural of sequencer is + + signal recovered_clk1, recovered_clk2 : std_logic; + signal test_enable : std_logic; + signal test_data : std_logic_vector(0 to 15); + + attribute max_wire_delay of + recovered_clk1, recovered_clk2 : signal is 100 ps; + + attribute max_wire_delay of others : signal is 200 ps; + + -- . . . + +begin + -- . . . + -- not in book + assert false report time'image(recovered_clk1'max_wire_delay) severity note; + assert false report time'image(recovered_clk2'max_wire_delay) severity note; + assert false report time'image(test_enable'max_wire_delay) severity note; + assert false report time'image(test_data'max_wire_delay) severity note; + -- end not in book +end architecture structural; + +-- code from book diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/tb_flipflop.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/tb_flipflop.vhd new file mode 100644 index 000000000..f1aacab62 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/tb_flipflop.vhd @@ -0,0 +1,39 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + +entity tb_flipflop is +end entity tb_flipflop; + + +architecture test of tb_flipflop is + + signal clk, d, q : bit; + +begin + + dut : entity work.flipflop(behavior) + generic map ( Tsetup => 3 ns ) + port map ( clk => clk, d => d, q => q ); + + clk <= '1' after 10 ns, '0' after 20 ns; + + d <= '1' after 8 ns; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/top.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/top.vhd new file mode 100644 index 000000000..46c69c6bd --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/top.vhd @@ -0,0 +1,86 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity top is +end entity top; + +-------------------------------------------------- + +architecture top_arch of top is + + signal top_sig : -- . . .; -- 1 + -- + bit; + -- + +begin + + stimulus : process is + variable var : -- . . .; -- 2 + -- + bit; + -- + begin + -- . . . + -- + report "--1: " & top'path_name; + report "--1: " & top'instance_name; + report "--1: " & top_sig'path_name; + report "--1: " & top_sig'instance_name; + report "--2: " & stimulus'path_name; + report "--2: " & stimulus'instance_name; + report "--2: " & var'path_name; + report "--2: " & var'instance_name; + wait; + -- + end process stimulus; + + rep_gen : for index in 0 to 7 generate + begin + + end_gen : if index = 7 generate + signal end_sig : -- . . .; -- 3 + -- + bit; + -- + begin + -- . . . + assert false report "--3: " & end_sig'path_name; + assert false report "--3: " & end_sig'instance_name; + -- + end generate end_gen; + + other_gen : if index /= 7 generate + signal other_sig : -- . . .; -- 4 + -- + bit; + -- + begin + other_comp : entity work.bottom(bottom_arch) + port map ( -- . . . ); + -- + port_name => open ); + assert false report "--4: " & other_sig'path_name; + assert false report "--4: " & other_sig'instance_name; + -- + end generate other_gen; + + end generate rep_gen; + +end architecture top_arch; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/voltage_defs.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/voltage_defs.vhd new file mode 100644 index 000000000..e0774e68a --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/voltage_defs.vhd @@ -0,0 +1,37 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +package voltage_defs is + + type voltage is range -2e9 to +2e9 + units + nV; + uV = 1000 nV; + mV = 1000 uV; + V = 1000 mV; + end units voltage; + + attribute resolution : real; + + attribute resolution of nV : units is 1.0; + attribute resolution of uV : units is 0.01; + attribute resolution of mV : units is 0.01; + attribute resolution of V : units is 0.001; + +end package voltage_defs; |