diff options
Diffstat (limited to 'testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling')
70 files changed, 4523 insertions, 0 deletions
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/analog_switch.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/analog_switch.vhd new file mode 100644 index 000000000..7e29c44db --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/analog_switch.vhd @@ -0,0 +1,42 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee; use ieee.std_logic_1164.all; +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity analog_switch is + port ( terminal n1, n2 : electrical; + signal control : in std_ulogic ); +end entity analog_switch; + +---------------------------------------------------------------- + +architecture ideal of analog_switch is + quantity v across i through n1 to n2; +begin + + if control = '1' or control = 'H' use + v == 0.0; + else + i == 0.0; + end use; + + break on control; + +end architecture ideal; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/ball.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/ball.vhd new file mode 100644 index 000000000..a8583af64 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/ball.vhd @@ -0,0 +1,48 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.mechanical_systems.all; + +entity ball is +end entity ball; + +---------------------------------------------------------------- + +architecture bouncer of ball is + quantity v : velocity := 0.0; + quantity s : displacement := 10.0; + constant g : real := 9.81; + constant air_res : real := 0.1; +begin + + if v'above(0.0) use + v'dot == -g - v**2*air_res; + else + v'dot == -g + v**2*air_res; + end use; + + reversal_tester : process is + begin + wait on s'above(0.0); + break v => -v when s < 0.0; + end process reversal_tester; + + s'dot == v; + +end architecture bouncer; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/ball_wa.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/ball_wa.vhd new file mode 100644 index 000000000..27d999548 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/ball_wa.vhd @@ -0,0 +1,56 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +ENTITY ball_wa IS +END ENTITY ball_wa; + +ARCHITECTURE simple OF ball_wa IS + QUANTITY v: real; + QUANTITY s: real; + CONSTANT G: real := 9.81; + CONSTANT Air_Res: real := 0.1; + SIGNAL damping: real := -0.7; + signal v_at_impact : real:= 0.0; + signal impact: boolean; +BEGIN + if domain = quiescent_domain use + v == 0.0; + s == 30.0; + elsif impact use + v == damping*v_at_impact; + s == 0.0; + else + s'dot == v; + v'dot == -G; + end use; + process begin + wait until not s'above(0.0); + if v < -1.0e-9 then + v_at_impact <= v; + impact <= true, false after 1 us; + else + damping <= 0.0; + impact <= true; + end if; + end process; + break on impact; +END architecture simple; + + + diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/bit_to_analog.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/bit_to_analog.vhd new file mode 100644 index 000000000..94e7d9e90 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/bit_to_analog.vhd @@ -0,0 +1,39 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity bit_to_analog is + port ( d : in bit; + terminal a : electrical ); +end entity bit_to_analog; + +---------------------------------------------------------------- + +architecture ideal of bit_to_analog is + constant v_low : real := 0.0; + constant v_high : real := 5.0; + signal v_in : real := 0.0; + quantity v_out across i_out through a to electrical_ref; +begin + + v_in <= v_high when d = '1' else v_low; + v_out == v_in'ramp(1.0e-9); + +end architecture ideal; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/capacitor.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/capacitor.vhd new file mode 100644 index 000000000..06c375461 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/capacitor.vhd @@ -0,0 +1,33 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity capacitor is + port ( terminal node1, node2 : electrical ); +end entity capacitor; + +architecture leakage of capacitor is + constant c : real := 1.0E-6; + constant r_leak : real := 10.0E6; + quantity v_cap across i_cap, i_leak through node1 to node2; +begin + i_cap == c * v_cap'dot; + i_leak == v_cap / r_leak; +end architecture leakage; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/comparator-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/comparator-1.vhd new file mode 100644 index 000000000..c2cba718e --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/comparator-1.vhd @@ -0,0 +1,50 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee; use ieee.std_logic_1164.all; +library IEEE_proposed; use IEEE_proposed.electrical_systems.all; + +entity comparator is + port ( terminal plus_in, minus_in : electrical; + signal output : out std_ulogic ); +end entity comparator; + +---------------------------------------------------------------- + +architecture hysteresis of comparator is + + constant threshold_margin : real := 0.2; + quantity v_in across plus_in to minus_in; + +begin + + comp_behavior : process is + variable threshold : real := threshold_margin; + begin + if v_in > threshold then + output <= '1' after 10 ns; + threshold := -threshold_margin; + else + output <= '0' after 10 ns; + threshold := threshold_margin; + end if; + wait on v_in'above(threshold); + end process comp_behavior; + +end architecture hysteresis; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/comparator.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/comparator.vhd new file mode 100644 index 000000000..3f5437f75 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/comparator.vhd @@ -0,0 +1,45 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee; use ieee.std_logic_1164.all; +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity comparator is + port ( terminal a : electrical; + signal d : out std_ulogic ); +end entity comparator; + +---------------------------------------------------------------- + +architecture ideal of comparator is + constant ref_voltage : real := 5.0; + quantity vin across a; +begin + + comparator_behavior : process is + begin + if vin > ref_voltage / 2.0 then + d <= '1' after 5 ns; + else + d <= '0' after 5 ns; + end if; + wait on vin'above(ref_voltage / 2.0); + end process comparator_behavior; + +end architecture ideal; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/control_system.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/control_system.vhd new file mode 100644 index 000000000..b4fa8b7ec --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/control_system.vhd @@ -0,0 +1,33 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity control_system is + port ( quantity feedback, target : in voltage; + quantity output : out voltage ); +end entity control_system; + +---------------------------------------------------------------- + +architecture simple_feedback of control_system is + constant gain : real := 2.0; +begin + output == gain * ( target - feedback ); +end architecture simple_feedback; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/dac_12_bit.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/dac_12_bit.vhd new file mode 100644 index 000000000..5d762e85e --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/dac_12_bit.vhd @@ -0,0 +1,50 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee; use ieee.std_logic_1164.all; +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity dac_12_bit is + port ( signal bus_in : in std_ulogic_vector (11 downto 0); + terminal analog_out : electrical ); +end entity dac_12_bit; + +---------------------------------------------------------------- + +architecture behavioral of dac_12_bit is + + constant v_max : real := 3.3; + signal s_out : real := 0.0; + quantity v_out across i_out through analog_out to electrical_ref; + +begin + + convert : process ( bus_in ) is + variable sum : natural; + begin + sum := 0; + for i in bus_in'range loop + sum := sum * 2 + boolean'pos( bus_in(i) = '1' or bus_in(i) = 'H' ); + end loop; + s_out <= v_max * real(sum) / real(2**12 - 1); + end process convert; + + v_out == s_out'ramp(1.0E-6); + +end architecture behavioral; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/diode.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/diode.vhd new file mode 100644 index 000000000..aeb24de0b --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/diode.vhd @@ -0,0 +1,54 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee, ieee_proposed; +use ieee.math_real.all; +use ieee_proposed.energy_systems.all; +use ieee_proposed.electrical_systems.all; +use ieee_proposed.thermal_systems.all; + +entity diode is + port ( terminal p, m : electrical; + terminal j : thermal ); +end entity diode; + +---------------------------------------------------------------- + +architecture one of diode is + + constant area : real := 1.0e-3; + constant Dn : real := 30.0; -- electron diffusion coefficient + constant Dp : real := 15.0; -- hole diffusion coefficient + constant np : real := 6.77e-5; -- minority charge density + constant pn : real := 6.77e-6; -- minority charge density + constant Ln : real := 5.47e-6; -- diffusion length for electrons + constant Lp : real := 12.25e-6; -- diffusion length for holes + quantity v across id through p to m; + quantity vt : voltage := 1.0; -- threshold voltage + quantity temp across power through j; + +begin + + vt == temp * K / Q; + + id == Q * area * (Dp * (pn / Lp) + Dn * (np / Ln)) * (exp(v / vt) - 1.0); + + power == v * id; + +end architecture one; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/index-ams.txt new file mode 100644 index 000000000..887fe94cb --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/index-ams.txt @@ -0,0 +1,84 @@ +--------------------------------------------------------------------------------------------------------------------------------------------- +-- Chapter 6 - Analog Modeling Constructs +--------------------------------------------------------------------------------------------------------------------------------------------- +-- Filename Primary Unit Secondary Unit Figure/Section +----------- ------------ -------------- -------------- +control_system.vhd entity control_system simple_feedback Figure 6-2 +comparator.vhd entity comparator ideal Figure 6-9 +variable_comparator.vhd entity variable_comparator ideal Figure 6-10 +transmission_line.vhd entity transmission_line abstract Figure 6-11 +transmission_line_wa.vhd entity transmission_line_wa abstract -- +inductor.vhd entity inductor ideal Figure 6-12 +piston.vhd entity piston simple Figure 6-13 +inductor-1.vhd entity inductor integral_form Figure 6-14 +moving_mass.vhd entity moving_mass behavioral Figure 6-15 +moving_mass_wa.vhd entity moving_mass_wa behavioral -- +opamp.vhd entity opamp slew_limited Figure 6-17 +quad_opamp.vhd entity quad_opamp slew_limited Figure 6-19 +quad_opamp_wa.vhd entity quad_opamp_wa slew_limited -- +bit_to_analog.vhd entity bit_to_analog ideal Figure 6-21 +std_logic_to_analog.vhd entity std_logic_to_analog ideal Figure 6-23 +opamp-1.vhd entity opamp saturating Figure 6-24 +opamp_wa-1.vhd entity opamp_wa saturating -- +resistor.vhd entity resistor ideal Figure 6-26 +capacitor.vhd entity capacitor leakage Figure 6-26 +inverting_integrator.vhd entity inverting_integrator structural Figure 6-27 +timer.vhd entity timer behavioral Figure 6-29 +ball.vhd entity ball bouncer Figure 6-30 +ball_wa.vhd entity ball_wa simple -- +analog_switch.vhd entity analog_switch ideal Figure 6-31 +pendulum.vhd entity pendulum constrained Figure 6-33 +pendulum_wa.vhd entity pendulum_wa constrained -- +triangle_waveform.vhd entity triangle_waveform ideal Figure 6-34 +triangle_waveform_wa.vhd entity triangle_waveform_wa ideal -- +comparator-1.vhd entity comparator hysteresis Figure 6-35 +dac_12_bit.vhd entity dac_12_bit behavioral Figure 6-36 +diode.vhd entity diode one Figure 6-38 +inline_01a.vhd entity inline_01a test Section 6.1 +inline_02a.vhd entity inline_02a test Section 6.1 +inline_03a.vhd entity temperature_dependent_resistor linear_approx Section 6.1 +inline_04a.vhd entity inline_04a test Section 6.2 +inline_05a.vhd entity inline_05a test Section 6.2 +inline_06a.vhd entity inline_06a test Section 6.2 +inline_07a.vhd entity battery -- Section 6.2 +-- entity ADC -- Section 6.2 +-- entity diode_thermal -- Section 6.2 +inline_08a.vhd entity inline_08a test Section 6.3 +inline_09a.vhd entity inline_09a test Section 6.4 +inline_10a.vhd entity inline_10a test Section 6.4 +inline_11a.vhd entity inline_11a test Section 6.4 +inline_12a.vhd entity inline_12a test Section 6.4 +inline_13a.vhd entity inline_13a test Section 6.4 +inline_14a.vhd entity inline_14a test Section 6.4 +inline_15a.vhd entity inline_15a test Section 6.5 +inline_16a.vhd package inline_16a_types -- Section 6.5 +-- entity seven_segment_led basic_optics Section 6.5 +-- entity inline_16a test Section 6.5 +inline_17a.vhd entity adc_with_ref signal_flow Section 6.5 +-- entity inline_17a test Section 6.5 +inline_18a.vhd entity inline_18a test Section 6.6 +inline_19a.vhd entity inline_19a test Section 6.6 +inline_20a.vhd entity inline_20a test Section 6.6 +inline_21a.vhd entity inline_21a test Section 6.7 +inline_22a.vhd entity inline_22a test Section 6.8 +inline_23a.vhd entity inline_23a test Section 6.8 +inline_24a.vhd entity inline_24a test Section 6.9 +--------------------------------------------------------------------------------------------------------------------------------------------- +-- TestBenches +--------------------------------------------------------------------------------------------------------------------------------------------- +-- Filename Primary Unit Secondary Unit Tested Model +------------ ------------ -------------- ------------ +tb_control_system.vhd entity tb_control_system TB_control_system control_system.vhd +tb_comparator.vhd entity tb_comparator TB_comparator comparator.vhd +tb_variable_comparator.vhd entity tb_variable_comparator TB_variable_comparator variable_comparator.vhd +tb_transmission_line.vhd entity tb_transmission_line TB_transmission_line transmission_line_wa.vhd +tb_piston.vhd entity tb_piston TB_piston piston.vhd +tb_moving_mass.vhd entity tb_moving_mass TB_moving_mass moving_mass_wa.vhd +tb_quad_opamp.vhd entity tb_quad_opamp TB_quad_opamp quad_opamp_wa.vhd +tb_bit_to_analog.vhd entity tb_bit_to_analog TB_bit2analog bit_to_analog.vhd +tb_std_logic_to_analog.vhd entity tb_std_logic_to_analog TB_std_logic2analog std_logic_to_analog.vhd +tb_inv_integrator.vhd entity tb_inv_integrator TB_inv_integrator inverting_integrator.vhd +tb_analog_switch.vhd entity tb_analog_switch TB_analog_switch analog_switch.vhd +tb_triangle_waveform.vhd entity tb_triangle_waveform TB_triangle_waveform triangle_waveform.vhd +tb_comparator-1.vhd entity tb_comparator TB_comparator comparator-1.vhd +tb_diode.vhd entity tb_diode TB_diode diode.vhd diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inductor-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inductor-1.vhd new file mode 100644 index 000000000..15d12f215 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inductor-1.vhd @@ -0,0 +1,33 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity inductor is + port (terminal n1, n2: electrical); +end entity inductor; + +---------------------------------------------------------------- + +architecture integral_form of inductor is + constant L: inductance := 0.5; + quantity branch_voltage across branch_current through n1 to n2; +begin + branch_current == branch_voltage'integ / L; +end architecture integral_form; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inductor.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inductor.vhd new file mode 100644 index 000000000..9f3fbd258 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inductor.vhd @@ -0,0 +1,33 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity inductor is + port (terminal n1, n2: electrical); +end entity inductor; + +---------------------------------------------------------------- + +architecture ideal of inductor is + constant L: inductance := 0.5; + quantity branch_voltage across branch_current through n1 to n2; +begin + branch_voltage == L* branch_current'dot; +end architecture ideal; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_01a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_01a.vhd new file mode 100644 index 000000000..d6b0709b8 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_01a.vhd @@ -0,0 +1,59 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_01a is + +end entity inline_01a; + + +architecture test of inline_01a is + + quantity capacitor_voltage : real; + constant capacitance : real := 1.0e-9; + + subtype current is real; + + -- code from book + + subtype charge is real tolerance "default_charge"; + quantity capacitor_charge : charge; + + -- + + quantity engine_power : real tolerance "approximate_power"; + + -- + + quantity I_sense : current := 0.15; -- initial value is 150mA + + -- + + quantity amplifier_gains : real_vector (3 downto 0) := (1.0, 1.0, 1.0, 0.5); + + -- end code from book + +begin + + -- code from book + + capacitor_charge == capacitor_voltage * capacitance; + + -- end code from book + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_02a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_02a.vhd new file mode 100644 index 000000000..c46a6a0f0 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_02a.vhd @@ -0,0 +1,71 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_02a is + +end entity inline_02a; + + +architecture test of inline_02a is +begin + + block_1 : block is + + -- code from book + + quantity input1, input2, output : real; + quantity amplified_input1, amplified_input2 : real; + + constant gain1 : real := 2.0; + constant gain2 : real := 4.0; + + -- end code from book + + begin + + -- code from book + + amplified_input1 == input1 * gain1; + amplified_input2 == input2 * gain2; + output == amplified_input1 * amplified_input2; + + -- end code from book + + end block block_1; + + + block_2 : block is + + quantity input1, input2, output : real; + + constant gain1 : real := 2.0; + constant gain2 : real := 4.0; + + begin + + -- code from book + + output == input1 * gain1 * input2 * gain2; + + -- end code from book + + end block block_2; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_03a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_03a.vhd new file mode 100644 index 000000000..b73e207eb --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_03a.vhd @@ -0,0 +1,37 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; +use ieee_proposed.electrical_systems.all; +use ieee_proposed.thermal_systems.all; + +entity temperature_dependent_resistor is + port ( terminal n1, n2 : electrical; + quantity temp : in temperature ); +end entity temperature_dependent_resistor; + +architecture linear_approx of temperature_dependent_resistor is + constant resistance_at_0 : real := 1.0E6; + constant resistance_drop_per_kelvin : real := 100.0; + quantity resistance : real; + quantity V across I through n1 to n2; +begin + resistance == resistance_at_0 - temp * resistance_drop_per_kelvin; + V == I * resistance; +end architecture linear_approx; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_04a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_04a.vhd new file mode 100644 index 000000000..9050b0de6 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_04a.vhd @@ -0,0 +1,91 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_04a is + +end entity inline_04a; + + +architecture test of inline_04a is +begin + + block_1 : block is + + -- code from book + + subtype voltage is real tolerance "low_voltage"; + subtype current is real tolerance "low_current"; + nature electrical is voltage across current through electrical_ref reference; + terminal anode, cathode : electrical; + + -- + + subtype illuminance is real tolerance "default_illuminance"; + subtype optic_flux is real tolerance "default_optic_flux"; + nature radiant is illuminance across optic_flux through radiant_ref reference; + terminal light_bulb, light_emitting_diode : radiant; + + -- + + nature electrical_vector is array (natural range <>) of electrical; + terminal a_bus : electrical_vector(1 to 8); + + -- + + quantity light_illuminance across light_bulb; + quantity LED_flux through light_emitting_diode; + + -- end code from book + + terminal n1, n2 : electrical; + + -- code from book + + quantity voltage_drop across + inductive_current, capacitive_current, resistive_current through + n1 to n2; + + -- end code from book + + begin + end block block_1; + + + + block_2 : block is + + subtype voltage is real tolerance "low_voltage"; + subtype current is real tolerance "low_current"; + nature electrical is voltage across current through electrical_ref reference; + + -- code from book + + terminal anode, cathode : electrical; + + -- + + quantity battery_voltage across battery_current through anode to cathode; + quantity leakage_voltage across leakage_current through anode; + + -- end code from book + + begin + end block block_2; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_05a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_05a.vhd new file mode 100644 index 000000000..f0ed183a0 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_05a.vhd @@ -0,0 +1,102 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity inline_05a is + +end entity inline_05a; + + +architecture test of inline_05a is + +begin + + block_1 : block is + + constant cap : real := 1.0e-9; + constant rleak : real := 1.0E6; + + -- code from book + + terminal p1, p2 : electrical; + quantity vcap across icap, ileak through p1 to p2; + + -- end code from book + + begin + + -- code from book + + icap == cap * vcap'dot; + + ileak == vcap / rleak; + + -- end code from book + + end block block_1; + + + block_2 : block is + + -- code from book + + nature electrical_vector is array (natural range <>) of electrical; + terminal a_bus : electrical_vector(1 to 8); + terminal signal_ground : electrical; + + -- + + quantity bus_drops across bus_currents through a_bus to signal_ground; + + -- + + terminal p1 : electrical_vector(0 to 3); + terminal p2 : electrical; + + quantity v across i through p1 to p2; + + -- + + constant tc1 : real := 1.0e-3; -- Linear temperature coefficient + constant tc2 : real := 1.0e-6; -- Second-order temperature coefficient + constant temp : real := 27.0; -- Ambient temperature + constant tnom : real := 50.0; -- Nominal temperature + constant res : real_vector := (1.0e3, 2.0e3, 4.0e3, 8.0e3); -- Nominal resistances + + -- + + constant res_factor : real := (1.0 + tc1*(temp-tnom) + tc2*(temp-tnom)**2); + + -- end code from book + + begin + + -- code from book + + v(0) == i(0) * res(0) * res_factor; + v(1) == i(1) * res(1) * res_factor; + v(2) == i(2) * res(2) * res_factor; + v(3) == i(3) * res(3) * res_factor; + + -- end code from book + + end block block_2; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_06a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_06a.vhd new file mode 100644 index 000000000..0c69a05ba --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_06a.vhd @@ -0,0 +1,94 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity inline_06a is + +end entity inline_06a; + + +architecture test of inline_06a is + + -- code from book + + terminal a_bus : electrical_vector(1 to 8); + terminal b_bus : electrical_vector(8 downto 1); + + -- + + quantity a_to_b_drops across a_to_b_currents through a_bus to b_bus; + + -- + + nature electrical_bus is + record + strobe: electrical; + databus : electrical_vector(0 to 7); + end record; + + terminal t1, t2 : electrical_bus; + + -- + + quantity bus_voltages across t1 to t2; + + -- + + terminal p1, p2 : electrical_vector(0 to 3); + + quantity v across i through p1 to p2; + + -- end code from book + + +begin + + block_1 : block is + + terminal anode, cathode : electrical; + + -- code from book + + quantity battery_voltage tolerance "battery_tolerance" across + battery_current tolerance "battery_tolerance" through anode to cathode; + + -- end code from book + + begin + end block block_1; + + + block_2 : block is + + terminal anode, cathode : electrical; + + -- code from book + + quantity battery_volts := 5.0 across + battery_amps := 0.0 through + anode to cathode; + + -- end code from book + + begin + end block block_2; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_07a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_07a.vhd new file mode 100644 index 000000000..e126536d3 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_07a.vhd @@ -0,0 +1,44 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity battery is + port ( terminal anode, cathode : electrical ); +end entity battery; + + + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity ADC is + port ( terminal a : electrical; + signal d : out bit ); +end entity ADC; + + + + +library ieee_proposed; +use ieee_proposed.electrical_systems.all, ieee_proposed.thermal_systems.all; + +entity diode_thermal is + port ( terminal p, m : electrical; + terminal j : thermal ); +end entity diode_thermal; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_08a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_08a.vhd new file mode 100644 index 000000000..9915d4fc6 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_08a.vhd @@ -0,0 +1,66 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity inline_08a is + +end entity inline_08a; + + +architecture test of inline_08a is + + -- code from book + + terminal bias_node : electrical; + + -- + + subnature accurate_electrical is electrical + tolerance "accurate_voltage" across "accurate_current" through; + + -- + + terminal n1, n2 : accurate_electrical; + + -- + + quantity n1_n2_voltage across n1_n2_current through n1 to n2; + + -- + + quantity internal_voltage : voltage tolerance n1_n2_voltage'tolerance; + quantity internal_current : current tolerance n1_n2_current'tolerance; + + -- + + terminal bus_a_end, bus_b_end : electrical_vector(15 downto 0); + quantity bus_currents through bus_a_end to bus_b_end; + + -- end code from book + +begin + + -- code from book + + bias_node'reference == 0.5; + + -- end code from book + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_09a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_09a.vhd new file mode 100644 index 000000000..fc3e334b6 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_09a.vhd @@ -0,0 +1,59 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; +use ieee_proposed.electrical_systems.all; +use ieee_proposed.mechanical_systems.all; + +entity inline_09a is + +end entity inline_09a; + + +architecture test of inline_09a is + + + constant R : real := 1.0e3; + constant k : real := 10.0; + + -- code from book + + terminal p, m : electrical; + quantity v across i through p to m; + + -- + + terminal node1, node2 : translational; + quantity d across f through node1 to node2; + + -- end code from book + +begin + + -- code from book + + v == i * R; + + -- + + f == d * k; + + -- end code from book + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_10a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_10a.vhd new file mode 100644 index 000000000..a6c3191c0 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_10a.vhd @@ -0,0 +1,217 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity inline_10a is + +end entity inline_10a; + + +architecture test of inline_10a is + + constant R : real := 10_000.0; + constant R1 : real := 10_000.0; + constant R2 : real := 10_000.0; + + -- code from book + + nature electrical_bus is + record + strobe: electrical; + databus : electrical_vector(0 to 7); + end record; + + -- end code from book + +begin + + block_1 : block is + + -- code from book + + terminal bus_end1, bus_end2 : electrical_bus; + quantity bus_v across bus_i through bus_end1 to bus_end2; + + -- end code from book + + begin + + -- code from book + + bus_v == bus_i * R; + + -- end code from book + + end block block_1; + + + block_2 : block is + + terminal bus_end1, bus_end2 : electrical_bus; + quantity bus_v across bus_i through bus_end1 to bus_end2; + + begin + + -- code from book + + bus_v.strobe == bus_i.strobe * R; + bus_v.databus(0) == bus_i.databus(0) * R; + bus_v.databus(1) == bus_i.databus(1) * R; + -- ... + -- not in book + bus_v.databus(2) == bus_i.databus(2) * R; + bus_v.databus(3) == bus_i.databus(3) * R; + bus_v.databus(4) == bus_i.databus(4) * R; + bus_v.databus(5) == bus_i.databus(5) * R; + bus_v.databus(6) == bus_i.databus(6) * R; + -- end not in book + bus_v.databus(7) == bus_i.databus(7) * R; + + -- end code from book + + end block block_2; + + + block_3 : block is + + terminal p, m : electrical; + quantity v across i through p to m; + + begin + + -- code from book + + v == i * R; + + -- end code from book + + end block block_3; + + + block_4 : block is + + terminal p, m : electrical; + quantity v across i through p to m; + + begin + + -- code from book + + v / R == i; + + -- end code from book + + end block block_4; + + + block_5 : block is + + terminal bus_end1, bus_end2 : electrical_bus; + quantity bus_v across bus_i through bus_end1 to bus_end2; + + begin + + -- code from book + + bus_v.strobe == bus_i.strobe * R; + bus_v.databus(0) == bus_i.databus(0) * R; + + -- end code from book + + bus_v.databus(1) == bus_i.databus(1) * R; + bus_v.databus(2) == bus_i.databus(2) * R; + bus_v.databus(3) == bus_i.databus(3) * R; + bus_v.databus(4) == bus_i.databus(4) * R; + bus_v.databus(5) == bus_i.databus(5) * R; + bus_v.databus(6) == bus_i.databus(6) * R; + bus_v.databus(7) == bus_i.databus(7) * R; + + end block block_5; + + + block_6 : block is + + terminal p1, m1, p2, m2 : electrical; + quantity v1 across i1 through p1 to m1; + quantity v2 across i2 through p2 to m2; + + begin + + -- code from book + + i1 * R1 == i2 * R2; -- illegal + + -- end code from book + + end block block_6; + + + block_7 : block is + + terminal p1, m1, p2, m2 : electrical; + quantity v1 across i1 through p1 to m1; + quantity v2 across i2 through p2 to m2; + + begin + + -- code from book + + i1 * R1 == i2 * R2 tolerance "current_tolerance"; + + -- end code from book + + end block block_7; + + + block_8 : block is + + terminal p1, m1, p2, m2 : electrical; + quantity v1 across i1 through p1 to m1; + quantity v2 across i2 through p2 to m2; + + begin + + -- code from book + + i1 * R1 == i2 * R2 tolerance i2'tolerance; + + -- end code from book + + end block block_8; + + + block_9 : block is + + terminal p, m : electrical; + quantity v across i through p to m; + + begin + + -- code from book + + v == i * R tolerance i'tolerance; + + -- end code from book + + end block block_9; + + +begin +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_11a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_11a.vhd new file mode 100644 index 000000000..67589bce6 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_11a.vhd @@ -0,0 +1,98 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity inline_11a is + +end entity inline_11a; + + +architecture test of inline_11a is + + constant v_pos : voltage := 15.0; + constant v_neg : voltage := -15.0; + terminal input : electrical; + quantity v_in across input; + quantity v_amplified : voltage; + constant gain : real := 1.0; + + constant threshold_voltage : voltage := 0.6; + constant k : real := 0.0125; + terminal gate, source, drain : electrical; + quantity vds across ids through drain to source; + quantity vsd across source to drain; + quantity vgs across gate to source; + quantity vgd across gate to drain; + + constant r_charge : resistance := 10_000.0; + constant r_discharge : resistance := 10_000.0; + constant charging : boolean := true; + terminal cap, plus, minus : electrical; + quantity v_plus := 10.0 across plus; + quantity v_minus := 0.0 across minus; + quantity v_cap across cap; + quantity i_charge through plus to cap; + quantity i_discharge through cap to minus; + +begin + + -- code from book + + if v_in * gain > v_pos use -- incorrect + v_amplified == v_pos; + elsif v_in * gain < v_neg use -- incorrect + v_amplified == v_neg; + else + v_amplified == gain * v_in; + end use; + + -- + + if vds'above(0.0) use -- transistor is forward biased + if not vgs'above(threshold_voltage) use -- cutoff region + ids == 0.0; + elsif vds'above(vgs - threshold_voltage) use -- saturation region + ids == 0.5 * k * (vgs - threshold_voltage)**2; + else -- linear/triode region + ids == k * (vgs - threshold_voltage - 0.5*vds) * vds; + end use; + else -- transistor is reverse biased + if not vgd 'above(threshold_voltage) use -- cutoff region + ids == 0.0; + elsif vsd'above(vgd - threshold_voltage) use -- saturation region + ids == -0.5 * k * (vgd - threshold_voltage)**2; + else -- linear/triode region + ids == -k * (vgd - threshold_voltage - 0.5*vsd) * vsd; + end use; + end use; + + -- + + if charging use + i_charge == ( v_plus - v_cap ) / r_charge; + i_discharge == 0.0; + else + i_charge == 0.0; + i_discharge == ( v_cap - v_minus ) / r_discharge; + end use; + + -- end code from book + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_12a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_12a.vhd new file mode 100644 index 000000000..a9c08e45d --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_12a.vhd @@ -0,0 +1,74 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity inline_12a is + +end entity inline_12a; + + +architecture test of inline_12a is + + -- code from book + + type biases is (forward, reverse); + type regions is (cutoff, saturation, linear); + + signal bias : biases; + signal region : regions; + + -- end code from book + + constant threshold_voltage : voltage := 0.6; + constant k : real := 0.0125; + terminal gate, source, drain : electrical; + quantity vds across ids through drain to source; + quantity vsd across source to drain; + quantity vgs across gate to source; + quantity vgd across gate to drain; + +begin + + -- code from book + + case bias use + when forward => + case region use + when cutoff => + ids == 0.0; + when saturation => + ids == 0.5 * k * (vgs - threshold_voltage)**2; + when linear => + ids == k * (vgs - threshold_voltage - 0.5*vds) * vds; + end case; + when reverse => + case region use + when cutoff => + ids == 0.0; + when saturation => + ids == -0.5 * k * (vgd - threshold_voltage)**2; + when linear => + ids == -k * (vgd - threshold_voltage - 0.5*vsd) * vsd; + end case; + end case; + + -- end code from book + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_13a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_13a.vhd new file mode 100644 index 000000000..d2a9c792f --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_13a.vhd @@ -0,0 +1,61 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity inline_13a is + +end entity inline_13a; + + +architecture test of inline_13a is + + -- code from book + + quantity v : voltage; + -- ... + + -- end code from book + +begin + + -- code from book + + if v'above(0.0) and not v'above(0.6) use + -- ... + elsif v'above(0.6) and not v'above(2.7) use + -- ... + else + -- ... + end use; + + -- + + case v use -- illegal + when 0.0 to 0.6 => + -- ...; + when 0.6 to 2.7 => + --...; + when others => + --...; + end case; + + -- end code from book + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_14a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_14a.vhd new file mode 100644 index 000000000..db70d94e4 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_14a.vhd @@ -0,0 +1,48 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity inline_14a is + +end entity inline_14a; + + +architecture test of inline_14a is + + terminal p : electrical; + quantity v across i through p; + constant R : resistance := 10_000.0; + + type modeling_mode_type is (ideal, non_ideal); + constant modeling_mode : modeling_mode_type := ideal; + +begin + + -- code from book + + if modeling_mode = ideal use + v == i * R; + else + null; -- still need to include resistor with thermal effects! + end use; + + -- end code from book + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_15a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_15a.vhd new file mode 100644 index 000000000..639e7a4db --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_15a.vhd @@ -0,0 +1,49 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; +use ieee_proposed.electrical_systems.all; +use ieee_proposed.thermal_systems.all; + +entity inline_15a is + +end entity inline_15a; + + +architecture test of inline_15a is + + -- code from book + + terminal bridge1, bridge2 : electrical; + quantity ambient : temperature; + + -- end code from book + +begin + + ambient == 300.0; + + -- code from book + + resistor1 : entity work.temperature_dependent_resistor(linear_approx) + port map ( n1 => bridge1, n2 => bridge2, temp => ambient ); + + -- end code from book + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_16a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_16a.vhd new file mode 100644 index 000000000..7cb180104 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_16a.vhd @@ -0,0 +1,106 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +package inline_16a_types is + + subtype ILLUMINANCE is REAL tolerance "DEFAULT_ILLUMINANCE"; + subtype OPTIC_FLUX is REAL tolerance "DEFAULT_OPTIC_FLUX"; + + nature RADIANT is + ILLUMINANCE across + OPTIC_FLUX through + RADIANT_REF reference; + + subtype VOLTAGE is REAL tolerance "DEFAULT_VOLTAGE"; + subtype CURRENT is REAL tolerance "DEFAULT_CURRENT"; + + nature ELECTRICAL is + VOLTAGE across + CURRENT through + ELECTRICAL_REF reference; + + -- code from book + + type illuminance_vector is array ( natural range <> ) of illuminance; + nature electrical_vector is array ( natural range <> ) of electrical; + + -- end code from book + +end package inline_16a_types; + + + +use work.inline_16a_types.all; + +-- code from book + +entity seven_segment_led is + port ( terminal segment_anodes : electrical_vector ( 1 to 7 ); + terminal common_cathode : electrical; + quantity segment_illuminances : out illuminance_vector ( 1 to 7 ) ); +end entity seven_segment_led; + +-- end code from book + + + +architecture basic_optics of seven_segment_led is +begin +end architecture basic_optics; + + + +use work.inline_16a_types.all; + +entity inline_16a is + +end entity inline_16a; + + +architecture test of inline_16a is + + -- code from book + + terminal hour_anode_2, hour_anode_3 : electrical; + terminal anodes_unused : electrical_vector(1 to 5); + terminal hour_display_source_2, hour_display_source_3 : radiant; + quantity hour_illuminance_2 across hour_display_source_2; + quantity hour_illuminance_3 across hour_display_source_3; + quantity illuminances_unused : illuminance_vector(1 to 5); + + -- end code from book + +begin + + -- code from book + + hour_digit : entity work.seven_segment_led(basic_optics) + port map ( segment_anodes(2) => hour_anode_2, + segment_anodes(3) => hour_anode_3, + segment_anodes(1) => anodes_unused(1), + segment_anodes(4 to 7) => anodes_unused(2 to 5), + common_cathode => electrical_ref, + segment_illuminances(2) => hour_illuminance_2, + segment_illuminances(3) => hour_illuminance_3, + segment_illuminances(1) => illuminances_unused(1), + segment_illuminances(4 to 7) => illuminances_unused(2 to 5) ); + + -- end code from book + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_17a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_17a.vhd new file mode 100644 index 000000000..08dbf5dfa --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_17a.vhd @@ -0,0 +1,88 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- code from book + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity adc_with_ref is + port ( quantity v_in : in voltage; + signal d_out : out bit; + quantity v_ref : in voltage := 1.0 ); +end entity adc_with_ref; + +-- end code from book + + +architecture signal_flow of adc_with_ref is +begin +end architecture signal_flow; + + + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity inline_17a is + +end entity inline_17a; + + +architecture test of inline_17a is + +begin + + block_1 : block is + + quantity sensor_in : voltage; + signal sensor_data_out : bit; + + begin + + sensor_in == 5.0; + + -- code from book + + default_adc : entity work.adc_with_ref(signal_flow) + port map ( sensor_in, sensor_data_out ); + + -- end code from book + + end block block_1; + + + block_2 : block is + + quantity sensor_in : voltage; + signal sensor_data_out : bit; + constant v_supply : voltage := 10.0; + + begin + + sensor_in == 5.0; + + -- code from book + + fixed_adc : entity work.adc_with_ref(signal_flow) + port map ( sensor_in, sensor_data_out, v_ref => v_supply / 2.0 ); + + -- end code from book + + end block block_2; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_18a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_18a.vhd new file mode 100644 index 000000000..00d73909b --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_18a.vhd @@ -0,0 +1,43 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity inline_18a is + +end entity inline_18a; + + +architecture test of inline_18a is + +begin + + process is + begin + + -- code from book + + break; + + -- end code from book + + wait; + end process; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_19a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_19a.vhd new file mode 100644 index 000000000..2e959007e --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_19a.vhd @@ -0,0 +1,110 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee; use ieee.std_logic_1164.all; +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity inline_19a is + +end entity inline_19a; + + +architecture test of inline_19a is + + signal reset, trigger_n : std_ulogic; + terminal rc_ext : electrical; + quantity v_rc_ext across rc_ext; + constant half_vdd : voltage := 2.5; + +begin + + block_1 : block is + + signal q, q_n : std_ulogic; + + begin + + process is + begin + + -- code from book + + -- ... + if reset = '1' or reset = 'H' or v_rc_ext > half_vdd then + q <= '0'; q_n <= '1'; + break; + elsif trigger_n = '0' or trigger_n = 'L' then + q <= '1'; q_n <= '0'; + break; + end if; + -- ... + + -- end code from book + + wait; + end process; + + end block block_1; + + + block_2 : block is + + signal q, q_n : std_ulogic; + + begin + + process is + begin + + -- code from book + + q_n <= '1' after 20 ns; + break; + + -- end code from book + + wait; + end process; + + end block block_2; + + + block_3 : block is + + signal q, q_n : std_ulogic; + + begin + + process is + begin + + -- code from book + + q_n <= '1'; + break; + + -- end code from book + + wait; + end process; + + end block block_3; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_20a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_20a.vhd new file mode 100644 index 000000000..8b6b66cbf --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_20a.vhd @@ -0,0 +1,315 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; +use ieee_proposed.electrical_systems.all; +use ieee_proposed.mechanical_systems.all; + +entity inline_20a is + +end entity inline_20a; + + +architecture test of inline_20a is + + signal trigger, discharge, clk : bit; + constant capacitance : real := 1.0e-9; + +begin + + + block_1 : block is + + terminal cap : electrical; + quantity v_cap across i_cap through cap; + + begin + + -- code from book + + i_cap == capacitance * v_cap'dot; + + -- + + trigger_reset : process (trigger) is + begin + if trigger = '1' then + break v_cap => 0.0; + end if; + end process trigger_reset; + + -- end code from book + + end block block_1; + + + block_2 : block is + + constant mass : real := 1.0; + terminal n : translational_v; + quantity v across n; + quantity applied_force : real; + quantity acceleration : real; + + quantity vx, vy : real; + + begin + + acceleration == v'dot; + + -- code from book + + applied_force == mass * acceleration; + + -- end code from book + + process is + begin + + -- code from book + + break acceleration'integ => - acceleration'integ; + + -- + + break vx => 0.0, vy => 0.0; + + -- end code from book + + wait; + end process; + + end block block_2; + + + block_3 : block is + + terminal cap : electrical; + quantity v_cap across i_cap through cap; + + begin + + i_cap == capacitance * v_cap'dot; + + -- code from book + + trigger_reset : process (trigger) is + begin + break v_cap => 0.0 when trigger = '1'; + end process trigger_reset; + + -- end code from book + + end block block_3; + + + block_4 : block is + + terminal cap : electrical; + quantity v_cap across i_cap through cap; + quantity charge : real; + + begin + + -- code from book + + charge == capacitance * v_cap; + + i_cap == charge'dot; + + -- + + trigger_reset : process (trigger) is + begin + if trigger = '1' then + break for charge use v_cap => 0.0; + end if; + end process trigger_reset; + + -- end code from book + + end block block_4; + + + block_5 : block is + + terminal cap : electrical; + quantity v_cap across i_cap through cap; + quantity charge : real; + + begin + + charge == capacitance * v_cap; + i_cap == charge'dot; + + -- code from book + + trigger_reset : process (trigger) is + begin + break for charge use v_cap => 0.0 when trigger = '1'; + end process trigger_reset; + + -- end code from book + + end block block_5; + + + block_6 : block is + + terminal cap : electrical; + quantity v_cap across i_cap through cap; + quantity cap_charge : real; + + begin + + cap_charge == capacitance * v_cap; + i_cap == cap_charge'dot; + + -- code from book + + discharge_cap : break cap_charge => 0.0 + on clk when discharge = '1' and clk = '1'; + + -- end code from book + + end block block_6; + + + block_7 : block is + + terminal cap : electrical; + quantity v_cap across i_cap through cap; + quantity cap_charge : real; + + begin + + cap_charge == capacitance * v_cap; + i_cap == cap_charge'dot; + + -- code from book + + discharge_cap : process is + begin + break cap_charge => 0.0 when discharge = '1' and clk = '1'; + wait on clk; + end process discharge_cap; + + -- end code from book + + end block block_7; + + + block_8 : block is + + terminal cap : electrical; + quantity v_cap across i_cap through cap; + quantity charge : real; + + begin + + charge == capacitance * v_cap; + i_cap == charge'dot; + + -- code from book + + trigger_reset : break for charge use v_cap => 0.0 when trigger = '1'; + + -- end code from book + + end block block_8; + + + block_9 : block is + + terminal cap : electrical; + quantity v_cap across i_cap through cap; + quantity charge : real; + + begin + + charge == capacitance * v_cap; + i_cap == charge'dot; + + -- code from book + + trigger_reset : process is + begin + break for charge use v_cap => 0.0 when trigger = '1'; + wait on trigger; + end process trigger_reset; + + -- end code from book + + end block block_9; + + + block_10 : block is + + quantity q : real; + constant new_q : real := 0.0; + + begin + + -- code from book + + useless_break : break q => new_q when q < 0.0 or q > 3.0; + + -- end code from book + + end block block_10; + + + block_11 : block is + + quantity q : real; + constant new_q : real := 0.0; + + begin + + -- code from book + + useless_break : process is + begin + break q => new_q when q < 0.0 or q > 3.0; + wait; + end process useless_break; + + -- end code from book + + end block block_11; + + + block_12 : block is + + quantity q : real; + constant new_q : real := 0.0; + + begin + + -- code from book + + correct_break : break q => new_q on q'above(0.0), q'above(3.0) + when q < 0.0 or q > 3.0; + + -- end code from book + + end block block_12; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_21a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_21a.vhd new file mode 100644 index 000000000..81f5e4fe3 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_21a.vhd @@ -0,0 +1,67 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; +use ieee_proposed.electrical_systems.all; +use ieee_proposed.mechanical_systems.all; + +entity inline_21a is + +end entity inline_21a; + + +architecture test of inline_21a is + + -- code from book + + quantity d : displacement; + + limit d : displacement with 0.001; + + -- + + quantity drive_shaft_av, axle_av, wheel_av : angular_velocity; + + -- + + limit drive_shaft_av, axle_av, wheel_av : angular_velocity with 0.01; + + -- + + limit all : angular_velocity with 0.01; + + -- + + quantity input, preamp_out, mixer_out, agc_out : voltage; + + limit input, preamp_out : voltage with 1.0E-9; + limit others : voltage with 1.0E-7; + + -- + + terminal bus1 : electrical_vector(1 to 8); + terminal bus2 : electrical_vector(1 to 8); + quantity v_bus across bus1 to bus2; + limit v_bus : voltage_vector with 1.0E-3; + + -- end code from book + +begin + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_22a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_22a.vhd new file mode 100644 index 000000000..e53a30cc5 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_22a.vhd @@ -0,0 +1,83 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee; use ieee.std_logic_1164.all; +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity inline_22a is + +end entity inline_22a; + + +architecture test of inline_22a is + + signal clock : bit; + quantity q : real; + signal sample : integer; + signal average : real; + + quantity v_in : real; + constant v_il : real := 0.8; + constant v_ih : real := 2.0; + signal data : std_ulogic; + +begin + + -- code from book + + sampler : process ( clock ) is + constant num_levels : real := 64.0; + constant max_val : real := 5.0; + begin + if clock = '1' then + sample <= integer(q * num_levels / max_val) after 5 ns; + end if; + end process sampler; + + -- + + compute_running_average : process (clock) is + variable num_samples : integer := 0; + variable total : real := 0.0; + variable running_average : real := 0.0; + begin + if clock = '1' then + total := total + q; + num_samples := num_samples + 1; + running_average := total / real(num_samples); + average <= running_average after 5 ns; + end if; + end process compute_running_average; + + -- + + analog_to_std_logic : process (v_in'above(v_il), v_in'above(v_ih)) is + begin + if not v_in'above(v_il) then + data <= '0'; + elsif v_in'above(v_ih) then + data <= '1'; + else + data <= 'X'; + end if; + end process analog_to_std_logic; + + -- end code from book + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_23a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_23a.vhd new file mode 100644 index 000000000..88a8025c6 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_23a.vhd @@ -0,0 +1,67 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity inline_23a is + +end entity inline_23a; + + +architecture test of inline_23a is + + signal digital_level : integer; + constant num_levels : integer := 63; + constant max_voltage : real := 10.0; + +begin + + block_1 : block is + + quantity analog_voltage : real; + + begin + + -- code from book + + analog_voltage == real(digital_level) / real(num_levels) * max_voltage; + + -- end code from book + + end block block_1; + + + block_2 : block is + + signal real_digital_level : real; + quantity analog_voltage : real; + + begin + + -- code from book + + real_digital_level <= real(digital_level); + analog_voltage == real_digital_level'ramp(1.0E-6) / real(num_levels) * max_voltage; + + -- end code from book + + end block block_2; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_24a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_24a.vhd new file mode 100644 index 000000000..66f0030fa --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_24a.vhd @@ -0,0 +1,49 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; +use ieee_proposed.electrical_systems.all; +use ieee_proposed.mechanical_systems.all; + +entity inline_24a is + +end entity inline_24a; + + +architecture test of inline_24a is + + -- code from book + + terminal plus, minus : electrical; + quantity v across i through plus to minus; + + terminal shaft : rotational_v; + quantity applied_torque through shaft; + + -- end code from book + +begin + + -- code from book + + applied_torque == v * i; + + -- end code from book + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inverting_integrator.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inverting_integrator.vhd new file mode 100644 index 000000000..3edb97525 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inverting_integrator.vhd @@ -0,0 +1,42 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity inverting_integrator is + port ( terminal input, output : electrical ); +end entity inverting_integrator; + +---------------------------------------------------------------- + +architecture structural of inverting_integrator is + terminal internal : electrical; +begin + + r1 : entity work.resistor(ideal) + port map ( node1 => input, node2 => internal ) ; + + c1 : entity work.capacitor(leakage) + port map ( node1 => internal, node2 => output ); + + amp : entity work.opamp(slew_limited) + port map ( plus_in => electrical_ref, minus_in => internal, + output => output ); + +end architecture structural; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/moving_mass.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/moving_mass.vhd new file mode 100644 index 000000000..586eaef48 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/moving_mass.vhd @@ -0,0 +1,38 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.mechanical_systems.all; + +entity moving_mass is + port ( terminal external_attachment : translational ); +end entity moving_mass; + +---------------------------------------------------------------- + +architecture behavioral of moving_mass is + constant mass : real := 10.0; + constant stiffness : real := 2.0; + constant damping : real := 5.0; + quantity position across driving_force through external_attachment; + quantity velocity : real; +begin + position == velocity'integ; + mass * velocity'dot == driving_force - stiffness * velocity'integ - damping * velocity + tolerance velocity'tolerance; +end architecture behavioral; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/moving_mass_wa.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/moving_mass_wa.vhd new file mode 100644 index 000000000..fc897f5be --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/moving_mass_wa.vhd @@ -0,0 +1,37 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.mechanical_systems.all; + +entity moving_mass_wa is + port ( terminal external_attachment : translational ); +end entity moving_mass_wa; + +---------------------------------------------------------------- + +architecture behavioral of moving_mass_wa is + constant mass : real := 10.0; + constant stiffness : real := 2.0; + constant damping : real := 5.0; + quantity position across driving_force through external_attachment; + quantity velocity : real; +begin + velocity == position'dot; + driving_force == mass*velocity'dot + damping*velocity + stiffness*position; +end architecture behavioral; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/opamp-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/opamp-1.vhd new file mode 100644 index 000000000..a2a26fe2c --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/opamp-1.vhd @@ -0,0 +1,52 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity opamp is + port ( terminal positive_supply, negative_supply : electrical; + terminal plus_in, minus_in, output : electrical ); +end entity opamp; + +---------------------------------------------------------------- + +architecture saturating of opamp is + + constant gain : real := 50.0; + quantity v_pos across positive_supply; + quantity v_neg across negative_supply; + quantity v_in across plus_in to minus_in; + quantity v_out across i_out through output; + quantity v_amplified : voltage; + +begin + + if v_in'above(v_pos / gain) use + v_amplified == v_pos; + elsif not v_in'above(v_neg / gain) use + v_amplified == v_neg; + else + v_amplified == gain * v_in; + end use; + + break on v_in'above(v_pos/gain), v_in'above(v_neg/gain); + + v_out == v_amplified'slew(1.0e6,-1.0e6); + +end architecture saturating; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/opamp.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/opamp.vhd new file mode 100644 index 000000000..009e061ba --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/opamp.vhd @@ -0,0 +1,41 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity opamp is + port ( terminal plus_in, minus_in, output : electrical ); +end entity opamp; + +---------------------------------------------------------------- + +architecture slew_limited of opamp is + + constant gain : real := 50.0; + quantity v_in across plus_in to minus_in; + quantity v_out across i_out through output; + quantity v_amplified : voltage; + +begin + + v_amplified == gain * v_in; + + v_out == v_amplified'slew(1.0e6,-1.0e6); + +end architecture slew_limited; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/opamp_wa-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/opamp_wa-1.vhd new file mode 100644 index 000000000..b5e7aa759 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/opamp_wa-1.vhd @@ -0,0 +1,52 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity opamp_wa is + port ( terminal positive_supply, negative_supply : electrical; + terminal plus_in, minus_in, output : electrical ); +end entity opamp_wa; + +---------------------------------------------------------------- + +architecture saturating of opamp_wa is + + constant gain : real := 50.0; + quantity v_pos := 15.0 across positive_supply; + quantity v_neg := -15.0 across negative_supply; + quantity v_in across plus_in to minus_in; + quantity v_out across i_out through output; + quantity v_amplified : voltage; + +begin + + if v_in'above(v_pos / gain) use + v_amplified == v_pos; + elsif not v_in'above(v_neg / gain) use + v_amplified == v_neg; + else + v_amplified == gain * v_in; + end use; + + break on v_in'above(v_pos/gain), v_in'above(v_neg/gain); + + v_out == v_amplified; -- 'slew(1.0e6,-1.0e6); + +end architecture saturating; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/pendulum.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/pendulum.vhd new file mode 100644 index 000000000..e78288068 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/pendulum.vhd @@ -0,0 +1,56 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee; use ieee.math_real.all; + +entity pendulum is +end entity pendulum; + +---------------------------------------------------------------- + +architecture constrained of pendulum is + + constant mass : real := 10.0; + constant arm_length : real := 5.0; + constant pin_angle : real := 0.25 * math_pi; + constant pin_distance : real := 2.5; + constant damping : real := 1.0; + constant gravity : real := 9.81; + constant short_length : real := arm_length - pin_distance; + quantity phi : real := -0.5*math_pi; + quantity current_length : real := arm_length; + +begin + + if phi'above(pin_angle) use + current_length == short_length; + else + current_length == arm_length; + end use; + + break phi'dot => phi'dot * arm_length/short_length + when phi'above(pin_angle); + + break phi'dot => phi'dot * short_length/arm_length + when not phi'above(pin_angle); + + mass * current_length * phi'dot'dot + == - mass * gravity * sin(phi) - damping * current_length * phi'dot; + +end architecture constrained; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/pendulum_wa.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/pendulum_wa.vhd new file mode 100644 index 000000000..bf3381127 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/pendulum_wa.vhd @@ -0,0 +1,90 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- Pendulum example. Look at velocity quantity, phi_dot, to see effects of +-- discontinuity. Run simulation for about 20 sec. + +library IEEE_proposed; +use IEEE_proposed.mechanical_systems.all; + +library ieee; use ieee.math_real.all; + +entity pendulum_wa is +end entity pendulum_wa; + +-- ====================================================================================== +-- constrained architecture +-- ====================================================================================== +architecture constrained of pendulum_wa is + constant mass : real := 10.0; + constant arm_length : real := 5.0; + constant pin_angle : real := 0.25*math_pi; + constant pin_distance : real := 2.5; + constant damping : real := 1.0; + constant gravity : real := 9.81; + constant short_length : real := arm_length-pin_distance; + quantity phi : real := -0.5*math_pi; + signal current_length : real := arm_length; + quantity acceleration, velocity : real; + quantity phi_dot : real; + signal pin_thresh : boolean; + signal phi_dot_at_pin_thresh : real := 0.0; + signal transition : boolean := false; + +begin + if domain = quiescent_domain use + phi == -0.5*math_pi; + phi'dot == 0.0; + elsif transition and pin_thresh use + phi == pin_angle; + phi'dot == phi_dot_at_pin_thresh*arm_length/short_length; + elsif transition and not pin_thresh use + phi == pin_angle; + phi'dot == phi_dot_at_pin_thresh*short_length/arm_length; + else + mass*acceleration == -mass*gravity*sin(phi)-damping*velocity; + velocity == current_length*phi'dot; + end use; + + acceleration == velocity'dot; + phi_dot == phi'dot; + + pin_thresh <= phi'above(pin_angle); + + process + begin + wait on pin_thresh; + phi_dot_at_pin_thresh <= phi_dot; + if pin_thresh = true then + current_length <= short_length; + transition <= true; + else + current_length <= arm_length; + transition <= true; + end if; + wait for 1 us; + transition <= false; + end process; + break on pin_thresh; + break on transition; + +end architecture constrained; + + + diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/piston.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/piston.vhd new file mode 100644 index 000000000..50f9db8c4 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/piston.vhd @@ -0,0 +1,33 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.mechanical_systems.all; + +entity piston is + port ( terminal motion : translational ); +end entity piston; + +-------------------------------------------------------------- + +architecture simple of piston is + constant mass : real := 10.0; + quantity resultant_displacement across applied_force through motion; +begin + applied_force == mass * resultant_displacement'dot'dot; +end architecture simple; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/quad_opamp.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/quad_opamp.vhd new file mode 100644 index 000000000..0bf267f9c --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/quad_opamp.vhd @@ -0,0 +1,44 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity quad_opamp is + port ( terminal plus_in, minus_in, output : electrical_vector(1 to 4) ); +end entity quad_opamp; + +---------------------------------------------------------------- + +architecture slew_limited of quad_opamp is + + constant gain : real := 50.0; + quantity v_in across plus_in to minus_in; + quantity v_out across i_out through output; + quantity v_amplified : real_vector(1 to 4); + +begin + + v_amplified(1) == gain * v_in(1); + v_amplified(2) == gain * v_in(2); + v_amplified(3) == gain * v_in(3); + v_amplified(4) == gain * v_in(4); + + real_vector(v_out) == v_amplified'slew(1.0e6,-1.0e6); + +end architecture slew_limited; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/quad_opamp_wa.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/quad_opamp_wa.vhd new file mode 100644 index 000000000..221b3e97f --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/quad_opamp_wa.vhd @@ -0,0 +1,50 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity quad_opamp_wa is + port (terminal n1, n2, output : electrical_vector(1 to 4)); +end entity quad_opamp_wa ; + +---------------------------------------------------------------- + +architecture slew_limited of quad_opamp_wa is + + quantity vin across n1 to n2; + quantity vout across iout through output; + quantity vamp1 : real; + quantity vamp2 : real; + quantity vamp3 : real; + quantity vamp4 : real; + constant gain : real := 50.0; + +begin + + vamp1 == gain*vin(1); + vamp2 == gain*vin(2); + vamp3 == gain*vin(3); + vamp4 == gain*vin(4); + + vout(1) == vamp1'slew(1.0e6,-1.0e6); + vout(2) == vamp2'slew(1.0e6,-1.0e6); + vout(3) == vamp3'slew(1.0e6,-1.0e6); + vout(4) == vamp4'slew(1.0e6,-1.0e6); + +end architecture slew_limited ; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/resistor.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/resistor.vhd new file mode 100644 index 000000000..2339f3344 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/resistor.vhd @@ -0,0 +1,31 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity resistor is + port ( terminal node1, node2 : electrical ); +end entity resistor; + +architecture ideal of resistor is + constant R : real := 1000.0; + quantity v across i through node1 to node2; +begin + v == i * R; +end architecture ideal; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/std_logic_to_analog.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/std_logic_to_analog.vhd new file mode 100644 index 000000000..a469e16a2 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/std_logic_to_analog.vhd @@ -0,0 +1,44 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee; use ieee.std_logic_1164.all; +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity std_logic_to_analog is + port ( d : in std_logic; + terminal a : electrical ); +end entity std_logic_to_analog; + +---------------------------------------------------------------- + +architecture ideal of std_logic_to_analog is + constant v_low : real := 0.0; + constant v_high : real := 5.0; + constant v_unknown : real := 2.0; + signal v_in : real := 0.0; + quantity v_out across i_out through a to electrical_ref; +begin + + v_in <= v_high when d = '1' or d = 'H' else + v_low when d = '0' or d = 'L' else + v_unknown; + + v_out == v_in'slew(2.0e+9, -1.0e+9); + +end architecture ideal; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_analog_switch.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_analog_switch.vhd new file mode 100644 index 000000000..08cc1b7d6 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_analog_switch.vhd @@ -0,0 +1,65 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library IEEE; +use IEEE.std_logic_1164.all; +library IEEE_proposed; +use IEEE_proposed.electrical_systems.all; +entity tb_analog_switch is +end tb_analog_switch; + +architecture TB_analog_switch of tb_analog_switch is + -- Component declarations + -- Signal declarations + terminal in_ana_src : electrical; + terminal in_switch : electrical; + signal clock_out : std_logic; +begin + -- Signal assignments + -- Component instances + vdc1 : entity work.v_constant(ideal) + generic map( + level => 1.0 + ) + port map( + pos => in_ana_src, + neg => ELECTRICAL_REF + ); + Clk1 : entity work.clock(ideal) + generic map( + period => 10.0ms + ) + port map( + clk_out => clock_out + ); + R1 : entity work.resistor(ideal) + generic map( + res => 100.0 + ) + port map( + p1 => in_ana_src, + p2 => in_switch + ); + swtch : entity work.analog_switch(ideal) + port map( + n1 => in_switch, + n2 => ELECTRICAL_REF, + control => clock_out + ); +end TB_analog_switch; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_bit_to_analog.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_bit_to_analog.vhd new file mode 100644 index 000000000..2c3cb18ef --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_bit_to_analog.vhd @@ -0,0 +1,58 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; +library IEEE_proposed; use IEEE_proposed.electrical_systems.all; + +entity tb_bit_to_analog is +end tb_bit_to_analog; + +architecture TB_bit2analog of tb_bit_to_analog is + -- Component declarations + -- Signal declarations + terminal ana_out : electrical; + signal ina : bit; + signal ina_tmp : std_logic; + +begin + -- Signal assignments + ina <= To_bit(ina_tmp); -- convert std_logic to bit + -- Component instances + d2a1 : entity work.bit_to_analog(ideal) + port map( + d => ina, -- bit type pin + a => ana_out + ); + clk1 : entity work.clock_duty(ideal) + generic map( + off_time => 2 ms, + on_time => 1 ms + ) + port map( + CLOCK_OUT => ina_tmp -- std_logic type pin + ); + R1 : entity work.resistor(ideal) + generic map( + res => 10.0e3 + ) + port map( + p1 => ana_out, + p2 => electrical_ref + ); +end TB_bit2analog; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_comparator-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_comparator-1.vhd new file mode 100644 index 000000000..b3e3ef248 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_comparator-1.vhd @@ -0,0 +1,51 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library IEEE; +use IEEE.std_logic_1164.all; +library IEEE_proposed; +use IEEE_proposed.electrical_systems.all; + +entity tb_comparator is +end tb_comparator; + +architecture TB_comparator of tb_comparator is + -- Component declarations + -- Signal declarations + terminal in_src : electrical; + signal cmp_out : std_logic; +begin + -- Signal assignments + -- Component instances + vio : entity work.v_sine(ideal) + generic map( + freq => 100.0, + amplitude => 5.0 + ) + port map( + pos => in_src, + neg => ELECTRICAL_REF + ); + C1 : entity work.comparator(hysteresis) + port map( + plus_in => in_src, + minus_in => electrical_ref, + output => cmp_out + ); +end TB_comparator; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_comparator.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_comparator.vhd new file mode 100644 index 000000000..33d8194df --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_comparator.vhd @@ -0,0 +1,49 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library IEEE; +use IEEE.std_logic_1164.all; +library IEEE_proposed; +use IEEE_proposed.electrical_systems.all; +entity tb_comparator is +end tb_comparator; + +architecture TB_comparator of tb_comparator is + -- Component declarations + -- Signal declarations + terminal in_src : electrical; + signal cmp_out : std_logic; +begin + -- Signal assignments + -- Component instances + vio : entity work.v_sine(ideal) + generic map( + freq => 100.0, + amplitude => 5.0 + ) + port map( + pos => in_src, + neg => ELECTRICAL_REF + ); + C1 : entity work.comparator(ideal) + port map( + a => in_src, + d => cmp_out + ); +end TB_comparator; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_control_system.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_control_system.vhd new file mode 100644 index 000000000..a4da70d2e --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_control_system.vhd @@ -0,0 +1,55 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library IEEE_proposed; + +entity tb_control_system is +end tb_control_system; + +architecture TB_control_system of tb_control_system is + -- Component declarations + -- Signal declarations + quantity in_src, fb : real; + quantity output : real; +begin + -- Signal assignments + -- Component instances + src3 : entity work.src_sine(ideal) + generic map( + freq => 100.0, + amplitude => 1.0 + ) + port map( + output => in_src + ); + XCMP12 : entity work.control_system(simple_feedback) + port map( + target => in_src, + output => output, + feedback => fb + ); + gain1 : entity work.gain(simple) + generic map( + k => 1.0 + ) + port map ( + input => output, + output => fb + ); +end TB_control_system; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_diode.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_diode.vhd new file mode 100644 index 000000000..05c20a95b --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_diode.vhd @@ -0,0 +1,68 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library IEEE; +use IEEE.std_logic_1164.all; +library IEEE_proposed; +use IEEE_proposed.electrical_systems.all; +use IEEE_proposed.thermal_systems.all; +entity tb_diode is +end tb_diode; + +architecture TB_diode of tb_diode is + -- Component declarations + -- Signal declarations + terminal in_src : electrical; + terminal r1_d1 : electrical; + terminal temp_in : thermal; +begin + -- Signal assignments + -- Component instances + vio : entity work.v_sine(ideal) + generic map( + freq => 100.0, + amplitude => 5.0 + ) + port map( + pos => in_src, + neg => ELECTRICAL_REF + ); + tmp : entity work.TempConstant(ideal) + generic map( + level => 100.0 + ) + port map( + th1 => temp_in, + th2 => thermal_REF + ); + R1 : entity work.resistor(ideal) + generic map( + res => 100.0 + ) + port map( + p1 => in_src, + p2 => r1_d1 + ); + D1 : entity work.diode(one) + port map( + p => r1_d1, + m => electrical_ref, + j => temp_in + ); +end TB_diode; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_inv_integrator.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_inv_integrator.vhd new file mode 100644 index 000000000..bcc236dc7 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_inv_integrator.vhd @@ -0,0 +1,56 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library IEEE_proposed; +use IEEE_proposed.electrical_systems.all; + +entity tb_inv_integrator is +end tb_inv_integrator; + +architecture TB_inv_integrator of tb_inv_integrator is + -- Component declarations + -- Signal declarations + terminal vin : electrical; + terminal vout : electrical; +begin + -- Signal assignments + -- Component instances + v1 : entity work.v_sine(ideal) + generic map( + amplitude => 0.2, + freq => 1.0e3 + ) + port map( + pos => vin, + neg => ELECTRICAL_REF + ); + inverting_integ1 : entity work.inverting_integrator(structural) + port map( + output => vout, + input => vin + ); + RLoad : entity work.load_res(ideal) + generic map( + R => 100.0 + ) + port map( + node1 => vout, + node2 => ELECTRICAL_REF + ); +end TB_inv_integrator; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_moving_mass.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_moving_mass.vhd new file mode 100644 index 000000000..8a44b78bb --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_moving_mass.vhd @@ -0,0 +1,88 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library IEEE_proposed; +use IEEE_proposed.mechanical_systems.all; + +entity tb_moving_mass is +end tb_moving_mass; + +architecture TB_moving_mass of tb_moving_mass is + -- Component declarations + -- Signal declarations + terminal msd_discrete, msd_mdl : translational; +begin + -- Signal assignments + -- Component instances + mass1 : entity work.mass_t(ideal) + generic map( + m => 10.0 + ) + port map( + trans1 => msd_discrete + ); + spring2 : entity work.spring_t(linear) + generic map( + k => 2.0 + ) + port map( + trans1 => msd_discrete, + trans2 => TRANSLATIONAL_REF + ); + damper1 : entity work.damper_t(ideal) + generic map( + d => 5.0 + ) + port map( + trans1 => msd_discrete, + trans2 => TRANSLATIONAL_REF + ); + Force1 : entity work.ForcePulse_t(ideal) + generic map( + initial => 0.0, + pulse => 20.0e-3, + ti2p => 1 ms, + tp2i => 1 ms, + delay => 1 ms, + width => 1 sec, + period => 3 sec + ) + port map( + trans_pos => msd_discrete, + trans_neg => TRANSLATIONAL_REF + ); + Force2 : entity work.ForcePulse_t(ideal) + generic map( + initial => 0.0, + pulse => 20.0e-3, + ti2p => 1 ms, + tp2i => 1 ms, + delay => 1 ms, + width => 1 sec, + period => 3 sec + ) + port map( + trans_pos => msd_mdl, + trans_neg => TRANSLATIONAL_REF + ); + moving_mass4 : entity work.moving_mass_wa(behavioral) + port map( + external_attachment => msd_mdl + ); +end TB_moving_mass; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_piston.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_piston.vhd new file mode 100644 index 000000000..5f238e443 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_piston.vhd @@ -0,0 +1,72 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library IEEE_proposed; +use IEEE_proposed.mechanical_systems.all; + +entity tb_piston is +end tb_piston; + +architecture TB_piston of tb_piston is + -- Component declarations + -- Signal declarations + terminal n1, n2 : translational; +begin + -- Signal assignments + -- Component instances + Force1 : entity work.ForcePulse_t(ideal) + generic map( + initial => 0.0, + pulse => 20.0e-3, + ti2p => 1 ms, + tp2i => 1 ms, + delay => 1 ms, + width => 1 sec, + period => 3 sec + ) + port map( + trans_pos => n1, + trans_neg => TRANSLATIONAL_REF + ); + mass1 : entity work.piston(simple) + port map( + motion => n1 + ); + Force2 : entity work.ForcePulse_t(ideal) + generic map( + initial => 0.0, + pulse => 20.0e-3, + ti2p => 1 ms, + tp2i => 1 ms, + delay => 1 ms, + width => 1 sec, + period => 3 sec + ) + port map( + trans_pos => n2, + trans_neg => TRANSLATIONAL_REF + ); + mass2 : entity work.mass_t(ideal) + generic map( + m => 10.0 + ) + port map( + trans1 => n2 + ); +end TB_piston; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_quad_opamp.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_quad_opamp.vhd new file mode 100644 index 000000000..dc55ca3d7 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_quad_opamp.vhd @@ -0,0 +1,162 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; + +library IEEE_proposed; +use IEEE_proposed.electrical_systems.all; + +entity tb_quad_opamp is +end tb_quad_opamp ; + +architecture TB_quad_opamp of tb_quad_opamp is + -- Component declarations + -- Signal declarations + terminal amp_out : electrical_vector(1 to 4); + terminal inm : electrical_vector(1 to 4); + terminal inp : electrical_vector(1 to 4); +begin + -- Signal assignments + -- Component instances + opamp_quad_slew1 : entity work.quad_opamp_wa(slew_limited) + port map( + n1 => inp, + n2 => inm, + output => amp_out + ); + R4 : entity work.resistor(ideal) + generic map( + res => 10.0e3 + ) + port map( + p1 => ELECTRICAL_REF, + p2 => amp_out(4) + ); + v4 : entity work.v_pulse(ideal) + generic map( + period => 200 us, + width => 100 us, + delay => 10 us, + tp2i => 0.9 us, + ti2p => 0.70 us, + pulse => 5.0 + ) + port map( + pos => inm(1), + neg => ELECTRICAL_REF + ); + R5 : entity work.resistor(ideal) + generic map( + res => 10.0e3 + ) + port map( + p1 => ELECTRICAL_REF, + p2 => amp_out(3) + ); + R6 : entity work.resistor(ideal) + generic map( + res => 10.0e3 + ) + port map( + p1 => ELECTRICAL_REF, + p2 => amp_out(2) + ); + R7 : entity work.resistor(ideal) + generic map( + res => 10.0e3 + ) + port map( + p1 => ELECTRICAL_REF, + p2 => amp_out(1) + ); + v5 : entity work.v_pulse(ideal) + generic map( + pulse => 5.0, + ti2p => 0.70 us, + tp2i => 0.9 us, + delay => 10 us, + width => 100 us, + period => 200 us + ) + port map( + pos => inm(2), + neg => ELECTRICAL_REF + ); + v6 : entity work.v_pulse(ideal) + generic map( + pulse => 5.0, + ti2p => 0.70 us, + tp2i => 0.9 us, + delay => 10 us, + width => 100 us, + period => 200 us + ) + port map( + pos => inm(3), + neg => ELECTRICAL_REF + ); + v7 : entity work.v_pulse(ideal) + generic map( + pulse => 5.0, + ti2p => 0.70 us, + tp2i => 0.9 us, + delay => 10 us, + width => 100 us, + period => 200 us + ) + port map( + pos => inm(4), + neg => ELECTRICAL_REF + ); + R8 : entity work.resistor(ideal) + generic map( + res => 10.0e-3 + ) + port map( + p1 => ELECTRICAL_REF, + p2 => inp(1) + ); + R9 : entity work.resistor(ideal) + generic map( + res => 10.0e-3 + ) + port map( + p1 => ELECTRICAL_REF, + p2 => inp(2) + ); + R10 : entity work.resistor(ideal) + generic map( + res => 10.0e-3 + ) + port map( + p1 => ELECTRICAL_REF, + p2 => inp(3) + ); + R11 : entity work.resistor(ideal) + generic map( + res => 10.0e-3 + ) + port map( + p1 => ELECTRICAL_REF, + p2 => inp(4) + ); +end TB_quad_opamp ; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_std_logic_to_analog.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_std_logic_to_analog.vhd new file mode 100644 index 000000000..1059d6c15 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_std_logic_to_analog.vhd @@ -0,0 +1,56 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; +library IEEE_proposed; use IEEE_proposed.electrical_systems.all; + +entity tb_std_logic_to_analog is +end tb_std_logic_to_analog; + +architecture TB_std_logic2analog of tb_std_logic_to_analog is + -- Component declarations + -- Signal declarations + terminal ana_out : electrical ; + signal ina : std_logic ; + +begin + -- Signal assignments + -- Component instances + d2a1 : entity work.std_logic_to_analog(ideal) + port map( + d => ina, -- bit type pin + a => ana_out + ); + clk1 : entity work.clock_duty(ideal) + generic map( + off_time => 2 ms, + on_time => 1 ms + ) + port map( + CLOCK_OUT => ina -- std_logic type pin + ); + R1 : entity work.resistor(ideal) + generic map( + res => 10.0e3 + ) + port map( + p1 => ana_out, + p2 => electrical_ref + ); +end TB_std_logic2analog; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_transmission_line.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_transmission_line.vhd new file mode 100644 index 000000000..c535fd771 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_transmission_line.vhd @@ -0,0 +1,56 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library IEEE_proposed; +use IEEE_proposed.electrical_systems.all; + +entity tb_transmission_line is + +end tb_transmission_line; + +architecture TB_transmission_line of tb_transmission_line is + quantity in_src, line_out : voltage; + -- Component declarations + -- Signal declarations +begin + -- Signal assignments + -- Component instances + q1 : entity work.src_pulse(ideal) + generic map( + initial => 0.0, + pulse => 1.0e1, + ti2p => 1.0e-12, + tp2i => 1.0e-12, + delay => 1 ps, + width => 20 ns, + period => 50 ns + ) + port map( + output => in_src + ); + + T1 : entity work.transmission_line_wa(abstract) + port map( + vin => in_src, + vout => line_out + ); + +end TB_transmission_line; + + diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_triangle_waveform.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_triangle_waveform.vhd new file mode 100644 index 000000000..ce33af878 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_triangle_waveform.vhd @@ -0,0 +1,45 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library IEEE_proposed; +use IEEE_proposed.electrical_systems.all; +entity tb_triangle_waveform is +end tb_triangle_waveform; + +architecture TB_triangle_waveform of tb_triangle_waveform is + -- Component declarations + -- Signal declarations + terminal in_src : electrical; +begin + -- Signal assignments + -- Component instances + vio : entity work.triangle_waveform_wa(ideal) + port map( + pos => in_src, + neg => ELECTRICAL_REF + ); + R1 : entity work.resistor(ideal) + generic map( + res => 10.0e9 + ) + port map( + p1 => in_src, + p2 => ELECTRICAL_REF + ); +end TB_triangle_waveform; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_variable_comparator.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_variable_comparator.vhd new file mode 100644 index 000000000..9dc43671a --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_variable_comparator.vhd @@ -0,0 +1,50 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library IEEE; +use IEEE.std_logic_1164.all; +library IEEE_proposed; +use IEEE_proposed.electrical_systems.all; +entity tb_variable_comparator is +end tb_variable_comparator; + +architecture TB_variable_comparator of tb_variable_comparator is + -- Component declarations + -- Signal declarations + terminal in_src, v_ref : electrical; + signal cmp_out : std_logic; +begin + -- Signal assignments + -- Component instances + vio : entity work.v_sine(ideal) + generic map( + freq => 100.0, + amplitude => 5.0 + ) + port map( + pos => in_src, + neg => ELECTRICAL_REF + ); + C1 : entity work.variable_comparator(ideal) + port map( + a => in_src, + ref => electrical_ref, + d => cmp_out + ); +end TB_variable_comparator; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/timer.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/timer.vhd new file mode 100644 index 000000000..8b151da24 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/timer.vhd @@ -0,0 +1,60 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee; use ieee.std_logic_1164.all; +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity timer is + port ( signal trigger_n, reset : in std_ulogic; signal q : out std_ulogic; + terminal rc_ext : electrical ); +end entity timer; + +---------------------------------------------------------------- + +architecture behavioral of timer is + + constant half_vdd : real := 2.5; + constant clamp_on_resistance : real := 0.01; + constant clamp_off_resistance : real := 10.0E6; + quantity v_rc_ext across i_clamp through rc_ext to electrical_ref; + signal q_n : std_ulogic := '1'; + +begin + + if q_n = '1' use + i_clamp == v_rc_ext / clamp_on_resistance; + else + i_clamp == v_rc_ext / clamp_off_resistance; + end use; + + timer_state : process ( trigger_n, reset, v_rc_ext'above(half_vdd) ) is + begin + if reset = '1' or reset = 'H' or v_rc_ext > half_vdd then + q <= '0'; q_n <= '1'; + elsif trigger_n = '0' or trigger_n = 'L' then + q <= '1'; q_n <= '0'; + end if; + end process timer_state; + + clamp_change : process ( q_n ) is + begin + break; + end process clamp_change; + +end architecture behavioral; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/transmission_line.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/transmission_line.vhd new file mode 100644 index 000000000..0206b7738 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/transmission_line.vhd @@ -0,0 +1,34 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity transmission_line is + port ( quantity vin : in voltage; + quantity vout : out voltage); +end entity transmission_line; + +---------------------------------------------------------------- + +architecture abstract of transmission_line is + constant propagation_time : real := 2.5E-9; + constant attenuation : real := 0.8; +begin + vout == attenuation * vin'delayed(propagation_time); +end architecture abstract; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/transmission_line_wa.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/transmission_line_wa.vhd new file mode 100644 index 000000000..accb3937b --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/transmission_line_wa.vhd @@ -0,0 +1,36 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity transmission_line_wa is + port ( quantity vin : in voltage; + quantity vout : out voltage); +end entity transmission_line_wa; + +---------------------------------------------------------------- + +architecture abstract of transmission_line_wa is + constant propagation_time : real := 2.5E-9; + constant attenuation : real := 0.8; + quantity vin_temp : real; +begin + vin_temp == vin; + vout == attenuation * vin_temp'delayed(propagation_time); +end architecture abstract; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/triangle_waveform.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/triangle_waveform.vhd new file mode 100644 index 000000000..6a7b82d2a --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/triangle_waveform.vhd @@ -0,0 +1,54 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity triangle_waveform is + port ( terminal pos, neg : electrical ); +end entity triangle_waveform; + +---------------------------------------------------------------- + +architecture ideal of triangle_waveform is + + constant freq : real := 10_000.0; -- in Hz + constant period : real := 1.0 / freq; + constant amplitude : voltage := 5.0; + constant offset : voltage := 0.0; + signal square_wave : real := 0.0; + quantity v across i through pos to neg; + limit v : voltage with period / 10.0; + +begin + + process is + variable state : bit := '0'; + begin + if state = '1' then + square_wave <= 1.0; + else + square_wave <= 0.0; + end if; + state := not state; + wait for period / 2.0; + end process; + + v == offset + amplitude * square_wave'ramp(period / 2.0); + +end architecture ideal; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/triangle_waveform_wa.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/triangle_waveform_wa.vhd new file mode 100644 index 000000000..bebc5ae38 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/triangle_waveform_wa.vhd @@ -0,0 +1,54 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity triangle_waveform_wa is + port ( terminal pos, neg : electrical ); +end entity triangle_waveform_wa; + +---------------------------------------------------------------- + +architecture ideal of triangle_waveform_wa is + + constant freq : real := 10_000.0; -- in Hz + constant period : real := 1.0 / freq; + constant amplitude : voltage := 5.0; + constant offset : voltage := 0.0; + signal square_wave : real := 0.0; + quantity v across i through pos to neg; +-- limit v : voltage with period / 10.0; + +begin + + process is + variable state : bit := '0'; + begin + if state = '1' then + square_wave <= 1.0; + else + square_wave <= 0.0; + end if; + state := not state; + wait for period / 2.0; + end process; + + v == offset + amplitude * square_wave'ramp(period / 2.0); + +end architecture ideal; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/variable_comparator.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/variable_comparator.vhd new file mode 100644 index 000000000..fb26e8711 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/variable_comparator.vhd @@ -0,0 +1,46 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee; use ieee.std_logic_1164.all; +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity variable_comparator is + port ( terminal a : electrical; + terminal ref : electrical; + signal d : out std_ulogic ); +end entity variable_comparator; + +---------------------------------------------------------------- + +architecture ideal of variable_comparator is + quantity v_ref across ref; + quantity vin across a; +begin + + comparator_behavior : process is + begin + if vin > v_ref then + d <= '1' after 5 ns; + else + d <= '0' after 5 ns; + end if; + wait on vin'above(v_ref / 2.0); + end process comparator_behavior; + +end architecture ideal; |