1 files changed, 49 insertions, 0 deletions
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_comparator.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_comparator.vhd
new file mode 100644
index 000000000..33d8194df
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_comparator.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+entity tb_comparator is
+end tb_comparator;
+
+architecture TB_comparator of tb_comparator is
+    -- Component declarations
+    -- Signal declarations
+    terminal in_src : electrical;
+    signal cmp_out : std_logic;
+begin
+    -- Signal assignments
+    -- Component instances
+    vio : entity work.v_sine(ideal)
+        generic map(
+            freq => 100.0,
+            amplitude => 5.0
+        )
+        port map(
+            pos => in_src,
+            neg => ELECTRICAL_REF
+        );
+    C1 : entity work.comparator(ideal)
+        port map(
+            a => in_src,
+            d => cmp_out
+        );
+end TB_comparator;