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Diffstat (limited to 'testsuite/vests/vhdl-ams/ashenden/compliant/aliases')
13 files changed, 753 insertions, 0 deletions
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/DMA_controller.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/DMA_controller.vhd new file mode 100644 index 000000000..532d65c5e --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/DMA_controller.vhd @@ -0,0 +1,47 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- not in book + +entity DMA_controller is +end entity DMA_controller; + +-- end not in book + + + +architecture behavioral of DMA_controller is + + use work.DMA_controller_types_and_utilities.all; + +begin + + behavior : process is + + variable address_reg0, address_reg1 : word; + variable count_reg0, count_reg1 : word; + -- . . . + + begin + -- . . . + address_reg0 := address_reg0 + X"0000_0004"; + -- . . . + end process behavior; + +end architecture behavioral; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/DMA_controller_types_and_utilities.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/DMA_controller_types_and_utilities.vhd new file mode 100644 index 000000000..95d300ed0 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/DMA_controller_types_and_utilities.vhd @@ -0,0 +1,83 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +package cpu_types is + + constant word_size : positive := 16; + + subtype word is bit_vector(word_size - 1 downto 0); + + type status_value is ( halted, idle, fetch, mem_read, mem_write, + io_read, io_write, int_ack ); + +end package cpu_types; + + + +package bit_vector_unsigned_arithmetic is + + function "+" ( bv1, bv2 : bit_vector ) return bit_vector; + +end package bit_vector_unsigned_arithmetic; + + +package body bit_vector_unsigned_arithmetic is + + function "+" ( bv1, bv2 : bit_vector ) return bit_vector is + + alias norm1 : bit_vector(1 to bv1'length) is bv1; + alias norm2 : bit_vector(1 to bv2'length) is bv2; + + variable result : bit_vector(1 to bv1'length); + variable carry : bit := '0'; + + begin + if bv1'length /= bv2'length then + report "arguments of different length" severity failure; + else + for index in norm1'reverse_range loop + result(index) := norm1(index) xor norm2(index) xor carry; + carry := ( norm1(index) and norm2(index) ) + or ( carry and ( norm1(index) or norm2(index) ) ); + end loop; + end if; + return result; + end function "+"; + +end package body bit_vector_unsigned_arithmetic; + + + + +-- code from book + +package DMA_controller_types_and_utilities is + + alias word is work.cpu_types.word; + alias status_value is work.cpu_types.status_value; + + alias "+" is work.bit_vector_unsigned_arithmetic."+" + [ bit_vector, bit_vector return bit_vector ]; + + -- . . . + +end package DMA_controller_types_and_utilities; + +-- end code from book + diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/controller_system.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/controller_system.vhd new file mode 100644 index 000000000..87f5d99ef --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/controller_system.vhd @@ -0,0 +1,65 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- not in book + +package alu_types is + + constant data_width : positive := 32; + +end package alu_types; + + +package io_types is + + constant data_width : positive := 32; + +end package io_types; + + +entity controller_system is +end entity controller_system; + +-- end not in book + + + +library ieee; use ieee.std_logic_1164.all; +use work.alu_types.all, work.io_types.all; + +architecture structural of controller_system is + + alias alu_data_width is work.alu_types.data_width; + alias io_data_width is work.io_types.data_width; + + signal alu_in1, alu_in2, + alu_result : std_logic_vector(0 to alu_data_width - 1); + signal io_data : std_logic_vector(0 to io_data_width - 1); + -- . . . + + -- not in book + -- following should not analyze: data_width not directly visible + -- constant test : positive := data_width; + -- end not in book + +begin + + -- . . . + +end architecture structural; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/function_plus.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/function_plus.vhd new file mode 100644 index 000000000..ddf330d0f --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/function_plus.vhd @@ -0,0 +1,59 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +package function_plus is + + -- code from book (in text) + + function "+" ( bv1, bv2 : bit_vector ) return bit_vector; + + -- end code from book + +end package function_plus; + + + +package body function_plus is + + -- code from book + + function "+" ( bv1, bv2 : bit_vector ) return bit_vector is + + alias norm1 : bit_vector(1 to bv1'length) is bv1; + alias norm2 : bit_vector(1 to bv2'length) is bv2; + + variable result : bit_vector(1 to bv1'length); + variable carry : bit := '0'; + + begin + if bv1'length /= bv2'length then + report "arguments of different length" severity failure; + else + for index in norm1'reverse_range loop + result(index) := norm1(index) xor norm2(index) xor carry; + carry := ( norm1(index) and norm2(index) ) + or ( carry and ( norm1(index) or norm2(index) ) ); + end loop; + end if; + return result; + end function "+"; + + -- end code from book + +end package body function_plus; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/index-ams.txt new file mode 100644 index 000000000..9d6e7557b --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/index-ams.txt @@ -0,0 +1,28 @@ +--------------------------------------------------------------------------------------------------------------------------------------------- +-- Chapter 11 - Aliases +--------------------------------------------------------------------------------------------------------------------------------------------- +-- Filename Primary Unit Secondary Unit Figure/Section +----------- ------------ -------------- -------------- +controller_system.vhd package alu_types -- -- +-- package io_types -- -- +-- entity controller_system structural Figure 11-1 +safety_switch.vhd entity safety_switch basic Figure 11-2 +function_plus.vhd package function_plus body Figure 11-3 +DMA_controller_types_and_utilities.vhd package cpu_types -- -- +-- package bit_vector_unsigned_arithmetic body -- +-- package DMA_controller_types_and_utilities -- Figure 11-4 +DMA_controller.vhd entity DMA_controller behavioral Figure 11-5 +inline_01a.vhd entity inline_01a test Section 11.1 +inline_02.vhd entity inline_02 test Section 11.1 +inline_03a.vhd entity inline_03a test Section 11.1 +inline_04.vhd entity inline_04 test Section 11.2 +inline_05.vhd package system_types -- Section 11.2 +-- entity inline_05 test Section 11.2 +inline_06.vhd package arithmetic_ops body Section 11.2 +-- entity inline_06 test Section 11.2 +--------------------------------------------------------------------------------------------------------------------------------------------- +-- TestBenches +--------------------------------------------------------------------------------------------------------------------------------------------- +-- Filename Primary Unit Secondary Unit Tested Model +------------ ------------ -------------- ------------ +tb_function_plus.vhd entity tb_function_plus test tb_function_plus.vhd diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_01a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_01a.vhd new file mode 100644 index 000000000..e2cda9e03 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_01a.vhd @@ -0,0 +1,42 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; +use ieee_proposed.electrical_systems.all; +use ieee_proposed.mechanical_systems.all; + +entity inline_01a is + +end entity inline_01a; + + +architecture test of inline_01a is + + -- code from book + + alias ground is electrical_ref; + + -- + + alias anchor is translational_ref; + + -- end code from book + +begin +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_02.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_02.vhd new file mode 100644 index 000000000..40c3f5441 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_02.vhd @@ -0,0 +1,74 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_02 is + +end entity inline_02; + + +---------------------------------------------------------------- + + +architecture test of inline_02 is +begin + + + process_1_a : process is + + -- code from book: + + type register_array is array (0 to 15) of bit_vector(31 downto 0); + + type register_set is record + general_purpose_registers : register_array; + program_counter : bit_vector(31 downto 0); + program_status : bit_vector(31 downto 0); + end record; + + variable CPU_registers : register_set; + + alias PSW is CPU_registers.program_status; + alias PC is CPU_registers.program_counter; + alias GPR is CPU_registers.general_purpose_registers; + + alias SP is CPU_registers.general_purpose_registers(15); + + alias interrupt_level is PSW(30 downto 26); + + -- end of code from book + + procedure procedure_1_b is + + -- code from book: + + alias SP is GPR(15); + + alias interrupt_level : bit_vector(4 downto 0) is PSW(30 downto 26); + + -- end of code from book + + begin + end procedure procedure_1_b; + + begin + wait; + end process process_1_a; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_03a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_03a.vhd new file mode 100644 index 000000000..ce51a86a7 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_03a.vhd @@ -0,0 +1,48 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; use ieee_proposed.electrical_systems.all; + +entity inline_03a is + +end entity inline_03a; + + +architecture test of inline_03a is + + -- code from book + + nature electrical_bus is + record + strobe : electrical; + databus : electrical_vector(0 to 7); + end record; + terminal ebus : electrical_bus; + quantity bus_voltages across ebus to ground; + + -- + + alias e_strobe is bus_voltages.strobe; + alias e_data is bus_voltages.databus; + + -- end code from book + +begin + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_04.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_04.vhd new file mode 100644 index 000000000..a17356cc0 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_04.vhd @@ -0,0 +1,58 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity inline_04 is + +end entity inline_04; + + +---------------------------------------------------------------- + + +architecture test of inline_04 is +begin + + + process_2_a : process is + + -- code from book: + + alias binary_string is bit_vector; + + variable s1, s2 : binary_string(0 to 7); + -- . . . + + -- end of code from book + + begin + + s1 := "10101010"; + s2 := "11110000"; + + -- code from book: + + s1 := s1 and not s2; + + -- end of code from book + + wait; + end process process_2_a; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_05.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_05.vhd new file mode 100644 index 000000000..8480a9555 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_05.vhd @@ -0,0 +1,66 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +package system_types is + + -- code from book + + type system_status is (idle, active, overloaded); + + -- end code from book + +end package system_types; + + + + +entity inline_05 is + +end entity inline_05; + + +---------------------------------------------------------------- + + +architecture test of inline_05 is + + -- code from book + + alias status_type is work.system_types.system_status; + + -- end code from book + +begin + + + process_2_b : process is + + variable status : status_type := idle; + + begin + wait for 10 ns; + status := active; + wait for 10 ns; + status := overloaded; + + wait; + end process process_2_b; + + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_06.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_06.vhd new file mode 100644 index 000000000..70b2c2bb2 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_06.vhd @@ -0,0 +1,96 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +package arithmetic_ops is + + -- code from book + + procedure increment ( bv : inout bit_vector; by : in integer := 1 ); + + procedure increment ( int : inout integer; by : in integer := 1 ); + + -- end code from book + +end package arithmetic_ops; + + + +package body arithmetic_ops is + + procedure increment ( bv : inout bit_vector; by : in integer := 1 ) is + begin + end procedure increment; + + procedure increment ( int : inout integer; by : in integer := 1 ) is + begin + end procedure increment; + +end package body arithmetic_ops; + + + +---------------------------------------------------------------- + + +entity inline_06 is + +end entity inline_06; + + +---------------------------------------------------------------- + + +library util; use util.stimulus_generators.all; + +architecture test of inline_06 is + + -- code from book + + alias bv_increment is work.arithmetic_ops.increment [ bit_vector, integer ]; + + alias int_increment is work.arithmetic_ops.increment [ integer, integer ]; + + alias "*" is "and" [ bit, bit return bit ]; + + alias "+" is "or" [ bit, bit return bit ]; + + alias "-" is "not" [ bit return bit ]; + + alias high is std.standard.'1' [ return bit ]; + + -- end code from book + + signal a, b, c, s : bit := '0'; + signal test_vector : bit_vector(1 to 3); + signal test_high : bit := high; + +begin + + -- code from book + + s <= a * b + (-a) * c; + + -- end code from book + + stimulus : all_possible_values ( bv => test_vector, + delay_between_values => 10 ns ); + + (a, b, c) <= test_vector; + +end architecture test; diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/safety_switch.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/safety_switch.vhd new file mode 100644 index 000000000..fb3caad5b --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/safety_switch.vhd @@ -0,0 +1,43 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +library ieee_proposed; +use ieee_proposed.electrical_systems.all, ieee_proposed.mechanical_systems.all; + +entity safety_switch is + port ( terminal neutral : electrical; + terminal relay_actuator : translational ); +end entity safety_switch; + +-- code from book + +library ieee_proposed; +use ieee_proposed.electrical_systems.all, ieee_proposed.mechanical_systems.all; + +architecture basic of safety_switch is + + quantity neutral_potential across neutral to ground; + quantity relay_position across relay_actuator to anchor; + -- ... + +begin + -- ... +end architecture basic; + +-- end code from book diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/tb_function_plus.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/tb_function_plus.vhd new file mode 100644 index 000000000..4acb94814 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/tb_function_plus.vhd @@ -0,0 +1,44 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity tb_function_plus is +end entity tb_function_plus; + + +architecture test of tb_function_plus is + + use work.function_plus.all; + +begin + + stimulus : process is + use std.textio.all; + variable L : line; + begin + write(L, X"0002" + X"0000"); + writeline(output, L); + write(L, X"0002" + X"0005"); + writeline(output, L); + write(L, X"0002" + X"FFFE"); + writeline(output, L); + + wait; + end process stimulus; + +end architecture test; |