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Diffstat (limited to 'testsuite/vests/vhdl-ams/ad-hoc')
204 files changed, 20160 insertions, 0 deletions
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/compliant.exp b/testsuite/vests/vhdl-ams/ad-hoc/compliant.exp new file mode 100644 index 000000000..6ad511efb --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/compliant.exp @@ -0,0 +1,31 @@ + +# Copyright (C) Clifton Labs, Inc All rights reserved. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + +# Please email any bugs, comments, and/or additions to this file to: +# vests@cliftonlabs.com + +setup_test_group "Ad-hoc:VHDL-AMS Compliant Cases" "vhdl-ams" + +set dir_prefix_length [expr [string length ${subdir}] + 3] + +foreach local_test_name [find ${subdir} *.ams] { + verbose "Running test at ./[string range ${local_test_name} [expr ${dir_prefix_length} - 2] end]" 2 + run_compliant_test ./[string range ${local_test_name} [expr [${dir_prefix_length} - 2] end] + delete_lib work +} + +end_test_group diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/analog_models/bjt_npn_gen.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/analog_models/bjt_npn_gen.ams new file mode 100644 index 000000000..c00e10506 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/analog_models/bjt_npn_gen.ams @@ -0,0 +1,143 @@ + +-- Copyright (C) 1999-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: bjt_npn_gen.ams,v 1.1 2002-03-27 22:11:16 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +-------------------------------------------------------------------- +-- Ebers-moll Model for a transistor -- +-- VHDL-AMS Implementation -- +-- Developed at the Distributed Processing Lab at the University -- +-- of Cincinnati -- +-- by VishwaShanth Kasula on May 10, 1999 -- +-------------------------------------------------------------------- +-- Circuit Topology -- +-- BJT Ebers-Moll static model +-- Testbench Ckt to evaluate the DC operatioing point of an npn BJT, +-- Sedra smith page no. 152, fig 4.9 +-------------------------------------------------------------------- +-- Three regions are simulated +-- Active region, vbb = 4.0 V +-- Saturation region, vbb = 6.0 V +-- Cutoff region, vbb = 0.0; + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; + + +use work.electricalsystem.all; + +entity bjt_npn is + generic(isat : real := 1.0e-16; -- Saturation Current + bf : real := 100.0; -- Ideal maximus forward current + br : real := 1.0; -- ideal maximum reverse current + rb : real := 1.0e-5; -- Base resistance + rc : real := 1.0e-5; -- collector resistance + re : real := 1.0e-5; -- emmiter resistance + vaf : real := 100.0); -- Forward Early Voltage + port(terminal e,b,c : electrical); +end bjt_npn; + +architecture structure of bjt_npn is + terminal b1, c1, e1 : electrical; + quantity vbo across ib through b to b1; + quantity vco across ic through c to c1; + quantity veo across ie through e to e1; + quantity vct across Ict through c1 to e1;--current source + quantity vbe across ibe through b1 to e1; + quantity vbc across ibc through b1 to c1; + quantity vce : real := 1.0; -- used to calculate VCE + constant gmin : real := 1.0e-12; -- condutsnce in parallel with every pn junction + constant vt : real := 0.02589; -- thermal voltage + +begin + brk : break vbe => 1.0, vbc => -1.0; + + diodecond1 : if(vbe > -5.0*vt) use + diodebef : ibe == ((isat*(exp(vbe/vt) - 1.0)) + (gmin*vbe))/bf; + elsif(vbe <= -5.0*vt ) use + diodeber: ibe == ((-1.0*isat) + (gmin*vbe))/bf; + end use; + diodecond2 : if(vbc > -5.0*vt) use + diodebcf : ibc == ((isat*(exp(vbc/vt) - 1.0)) + (gmin*vbc))/br; + elsif(vbc <= -5.0*vt) use + diodebcr : ibc == ((-1.0*isat) + (gmin*vbc))/br; + end use; + bres : vbo == ib * 1.0e-6; + cres : vco == ic * 1.0e-6; + eres : veo == ie * 1.0e-6; + kcl_eqn : ie == -1.0*(ib + ic); + vcevolt : vce == vbe - vbc; + ictdep : Ict == ((Ibe*bf) - (Ibc*br)) * (1.0 -(vbc/vaf)); + +end architecture structure; + + +--***************************************************** +--TEST BENCH +use std.textio.all; +use work.electricalsystem.all; + +entity bjt_testbench is +end bjt_testbench; + +architecture structure of bjt_testbench is + terminal t1, t2, t3, t4 : electrical ; + component bjt_npn_comp + generic(isat : real := 1.0e-16; -- Saturation Current + bf : real := 100.0; -- Ideal maximus forward current + br : real := 1.0; -- ideal maximum reverse current + rb : real := 1.0e-5; -- Base resistance + rc : real := 1.0e-5; -- collector resistance + re : real := 1.0e-5; -- emmiter resistance + vaf : real := 100.0); -- Forward Early Voltage + port(terminal e,b,c : electrical); + end component; + for all : bjt_npn_comp use entity work.bjt_npn(structure); + + quantity vcc across icc through t1 to electrical'reference; + quantity vrc across irc through t1 to t2; + quantity vbb across ibb through t3 to electrical'reference; + quantity vre across ire through t4 to electrical'reference; + +begin + + bjt : bjt_npn_comp + generic map (isat => 1.8104e-15, vaf => 100.0) + port map(t4,t3,t2); + emres : vre == ire * 3.3e3; + ccurr : vcc == 10.0; + ecurr : vbb == 6.0; + cores : vrc == irc * 4.7e3; + +end architecture structure; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/analog_models/bjt_pnp_gen.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/analog_models/bjt_pnp_gen.ams new file mode 100644 index 000000000..a6a97c5a6 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/analog_models/bjt_pnp_gen.ams @@ -0,0 +1,139 @@ + +-- Copyright (C) 1999-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: bjt_pnp_gen.ams,v 1.1 2002-03-27 22:11:16 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +----------------------------------------------------------------------------- +-- Ebers-moll Model for a transistor -- +-- VHDL-AMS Implementation -- +-- Developed at the Distributed Processing Lab at the University -- +-- of Cincinnati -- +-- by VishwaShanth Kasula on May 10, 1999 -- +-------------------------------------------------------------------- +-- Circuit Topology -- +-- BJT Ebers-Moll static model +-- Testbench Ckt to evaluate the DC operatioing point of an pnp BJT, +-- Sedra smith page no. 155, fig 4.11 +-------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; + + +use work.electricalsystem.all; + +entity bjt_pnp is + generic(isat : real := 1.0e-16; -- Saturation Current + bf : real := 100.0; -- Ideal maximus forward current + br : real := 1.0; -- ideal maximum reverse current + rb : real := 1.0e-5; -- Base resistance + rc : real := 1.0e-5; -- collector resistance + re : real := 1.0e-5; -- emmiter resistance + vaf : real := 100.0); -- Forward Early Voltage + port(terminal e,b,c : electrical); +end bjt_pnp; + +architecture structure of bjt_pnp is + terminal b1, c1, e1 : electrical; + quantity vbo across ib through b1 to b; + quantity vco across ic through c1 to c; + quantity veo across ie through e1 to e; + quantity vct across Ict through e1 to c1;--current source + quantity vbe across ibe through e1 to b1; + quantity vbc across ibc through c1 to b1; + quantity vce : real := 1.0; -- used to calculate VCE + constant gmin : real := 1.0e-12; -- condutsnce in parallel with every pn junction + constant vt : real := 0.02589; -- thermal voltage + +begin + brk : break vbe => 1.0, vbc => -1.0; + + diodecond1 : if(vbe > -5.0*vt) use + diodebef : ibe == ((isat*(exp(vbe/vt) - 1.0)) + (gmin*vbe))/bf; + elsif(vbe <= -5.0*vt ) use + diodeber: ibe == ((-1.0*isat) + (gmin*vbe))/bf; + end use; + diodecond2 : if(vbc > -5.0*vt) use + diodebcf : ibc == ((isat*(exp(vbc/vt) - 1.0)) + (gmin*vbc))/br; + elsif(vbc <= -5.0*vt) use + diodebcr : ibc == ((-1.0*isat) + (gmin*vbc))/br; + end use; + bres : vbo == ib * 1.0e-6; + cres : vco == ic * 1.0e-6; + eres : veo == ie * 1.0e-6; + kcl_eqn : ie == -1.0*(ib + ic); + vcevolt : vce == vbe - vbc; + ictdep : Ict == ((Ibe*bf) - (Ibc*br)) * (1.0 -(vbc/vaf)); + +end architecture structure; + + +--***************************************************** +--TEST BENCH +use std.textio.all; +use work.electricalsystem.all; + +entity bjt_testbench is +end bjt_testbench; + +architecture structure of bjt_testbench is + terminal t1, t2, t3, t4 : electrical ; + component bjt_pnp_comp + generic(isat : real := 1.0e-16; -- Saturation Current + bf : real := 100.0; -- Ideal maximus forward current + br : real := 1.0; -- ideal maximum reverse current + rb : real := 1.0e-5; -- Base resistance + rc : real := 1.0e-5; -- collector resistance + re : real := 1.0e-5; -- emmiter resistance + vaf : real := 100.0); -- Forward Early Voltage + port(terminal e,b,c : electrical); + end component; + for all : bjt_pnp_comp use entity work.bjt_pnp(structure); + + quantity vcc across icc through t4 to electrical'reference; + quantity vrc across irc through t3 to t4; + quantity vee across iee through t1 to electrical'reference; + quantity vre across ire through t1 to t2; + +begin + + bjt : bjt_pnp_comp + generic map (isat => 1.8104e-15) + port map(t2,ground,t3); + emres : vre == ire * 2.0e3; + ccurr : vcc == -10.0; + ecurr : vee == 10.0; + cores : vrc == irc * 1.0e3; + +end architecture structure; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/analog_models/static_cmos_inv_ramp.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/analog_models/static_cmos_inv_ramp.ams new file mode 100644 index 000000000..5aeb07ba0 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/analog_models/static_cmos_inv_ramp.ams @@ -0,0 +1,516 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: static_cmos_inv_ramp.ams,v 1.1 2002-03-27 22:11:16 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +-- This ckt is used to find the output characteristics of a cmos inverter +-- The ckt used here is from sedra and smith's page no. 565, fig 13.13 +-- The mos W/L are according to the model specified in spice using the deck +-- provided in the book. +-- The vgs, resistance is now removed, to avoid the RC effect on the imput. +-- the ramp input is used + + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH; + FUNCTION POW(X,Y: real) RETURN real; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; +END PACKAGE electricalSystem; + + +----------------------------------------------------------------------- +-- G B D1 1.0 ohm D +-- o o-----|>|--o---o----/\/\---------o /\ +-- | | | | |+ +-- Vgs < - Idsg( ) > Vdso +-- > V | < |- +-- | - | | | +-- S1 o------o--o------------------------------o S1V +-- | +-- > +-- < rs= 1.0 ohm +-- | +-- 0 S +----------------------------------------------------------------------- + +----- NMOS +--use std.textio.all; +use work.electricalsystem.all; + +entity nmos is + generic(mos_type : real := 1.0; -- +1.0 for nmos , -1.0 for pmos + T : real := 300.0; + W : real := 1.0; + L : real := 1.0; + vto : real := 1.0; -- Zero-bais threshold voltage + kp : real := 2.0e-5; -- transcondiuctanec parameter + gamma : real := 0.0; -- body-effect parameter + phi : real := 0.6; -- surface inversion potential + lambda : real := 0.02; -- channel lenght modulation + tox : real := 1.0e-7; -- thin oxide thickness + nsub : real := 0.0; -- Substrate doping + nss : real := 0.0; -- Surface STate density + ld : real := 0.0; -- lateral diffusion; + tpg : real := 1.0; -- Type of Gate material + uo : real := 600.0; -- Surface mobility + af : real := 1.0; -- flicker noise exponent + kf : real := 0.0; -- fliccker noise coefficient + iss : real := 1.0e-14; -- bulk junction saturation current + js : real := 0.0; -- bulk junctioin saturatioin current/ sqr meter + pb : real := 0.80; -- bulk junction potential + cj : real := 0.0; -- Zero-bias bulk capacitance/ sqr meter + mj : real := 0.5; -- bulk junctioin grading coefficient + cjsw : real := 0.0; -- Zero bias perimeter capacitance / sqr meter + mjsw : real := 0.33; -- Perimiter capacitance rading coefficient + fc : real := 0.5; -- forward-bais depletion capacitance coeff +-- cgbo : real := 4.0e-10; -- gate-bulk overlap cap / meter +-- cgdo : real := 1.5e-10; -- gate-drain overlap cap / meter +-- cgso : real := 1.5e-10; -- gate-source overlap cap / meter + cgbo : real := 2.0e-10; -- gate-bulk overlap cap / meter + cgdo : real := 4.0e-11; -- gate-drain overlap cap / meter + cgso : real := 4.0e-11; -- gate-source overlap cap / meter + rd : real := 1.0; -- drain ohmic resistance + rs : real := 1.0; -- source ohmic resistance + rsh : real := 0.0); -- source and drain sheet resistance + port (terminal g,s,d,b : electrical); +end entity nmos; + +architecture behav of nmos is + terminal d1, s1 : electrical; + quantity vds across idsg through d1 to s1; + quantity vdsr across idsr through d1 to d; + quantity vgs across igs through g to s1; + quantity vbs across ibs through b to s1; + quantity vbd across ibd through b to d1; +-- new quantities added for source resistance + quantity vsr across isr through s1 to s; + quantity iss, isd : real := 1.0e-12; + quantity beta : real := 8.85e-05; -- gain + quantity leff : real := 1.0; -- effective length + constant gmin : real := 1.0e-12; + quantity vth : real := 0.5; -- threshold voltage + quantity ktq : real := 2.586e-2; -- (kT/q) thermal voltage at T=300K + --constant k : real := 1.38e-23; -- J/K ..... boltzman constant + -- T = 300 K ............ Absolute temperature + --constant q : real := 1.60e-19; -- C ....... magnitude of electron charge + constant cox_prime : real := 3.4515e-8; -- oxide capacitance per unit area F/cm2. cox_prime = EOX/TOX + quantity cox : real := 3.4515e-8; + quantity vds_free : real := 5.0; + quantity vgs_free : real := 0.0; + constant as : real := 15.0e-12; -- source area + constant ad : real := 15.0e-12; -- drain area + +begin + ------ Setting initial conditions + initreg : break vgs => 0.0, vds => 5.0, vth => 0.5; + + thres_volt : vth == vto + (gamma *(sqrt((2.0*phi)-vbs) - sqrt(phi))); + eff_length : leff == L - (2.0*ld); + therm_volt : ktq == 2.586e-2 * (T/300.0); + sat_scurr : iss == js*as; + sat_dcurr : isd == js*ad; +-- gn : beta == 8.85e-05 * (W/L); + gn : beta == kp * ( w/leff); +-- opn : vdsg == 1.0e9 * idsgi; -- almost open + d12_res : vdsr == idsr * rd; +-- g12res : vgsr == igsr * rs; +-- g_oup : vgs == igs * 1.0e9; +-- oup_res : vds == ids * 1.0e9; + oup_res : vds_free == vds; + inp_res : vgs_free == vgs; + gre : vgs == igs * 1.0e9; + capeqn : cox == cox_prime * W * Leff; -- cox_prime * W * Leff + src_res : isr == vsr * rs; + +---- Current is in Micro Amps. +-- Normal mode + ------ Cut off Region + regions : if((vgs < vth) and (vds >= 0.0))use + gncn : idsg == 1.0e-9 * vds; + ------ Linear Region + elsif((vds <= (vgs-vth)) and (vgs >= vth) and (vds >= 0.0)) use + gnln : idsg == vds*beta*((vgs_free-vth) - (vds_free/2.0))*(1.0 + lambda*vds_free); + ------ Saturation Region + elsif((vds > vgs-vth) and (vgs >= vth) and (vds >= 0.0)) use + gnsn : idsg == (beta/2.0)*(pow((vgs_free-vth),2.0))*(1.0 + lambda*vds_free); + +-- Inversion mode + ------ Cut off Region + elsif((vgs < vth) and (vds < 0.0))use + gnci : idsg == 1.0e-9 * vds; + ------ Linear Region + elsif(((-1.0*vds) <= (vgs-vth)) and (vgs >= vth) and (vds < 0.0)) use + gnli : idsg == vds*beta*((vgs_free-vth) + (vds_free/2.0))*(1.0 - lambda*vds_free); + ------ Saturation Region + elsif(((-1.0*vds) > vgs-vth) and (vgs >= vth) and (vds < 0.0)) use + gnsi : idsg == -1.0*(beta/2.0)*(pow((vgs_free-vth),2.0))*(1.0 - lambda*vds_free); + end use; + +----- Substrate diode equations + initsub : break vbd => 0.0, vbs => 0.0, ibs => 0.0, ibd => 0.0; + + ----- Substrate to source + subcond1 : if(vbs > 0.0) use + bulk1 : ibs == ((iss*(exp(vbs/ktq) - 1.0)) + (gmin*vbs)); + elsif(vbs <= 0.0 ) use + bulk2 : ibs == ((iss*(vbs/ktq)) + (gmin*vbs)); + end use; + ----- Substrate to drain + subcond2 : if(vbd > 0.0) use + bulk3 : ibd == ((isd*(exp(vbd/ktq) - 1.0)) + (gmin*vbd)); + elsif(vbd <= 0.0 ) use + bulk4 : ibd == ((isd*(vbd/ktq)) + (gmin*vbd)); + end use; + +end architecture behav; --- of nmos; + + +----------------------------------------------------------------------- +-- G B D1 1.0 ohm D +-- o o-----|>|--o---o----/\/\---------o /\ +-- | | | | |+ +-- Vgs < - Idsg( ) > Vdso +-- > V | < |- +-- | - | | | +-- S1 o------o--o------------------------------o S1V +-- | +-- > +-- < rs= 1.0 ohm +-- | +-- 0 S +----------------------------------------------------------------------- + +----- PMOS +--use std.textio.all; +use work.electricalsystem.all; + +entity pmos is + generic(mos_type : real := 1.0; -- +1.0 for nmos , -1.0 for pmos + T : real := 300.0; + W : real := 1.0; + L : real := 1.0; + vto : real := 1.0; -- Zero-bais threshold voltage + kp : real := 2.0e-5; -- transcondiuctanec parameter + gamma : real := 0.0; -- body-effect parameter + phi : real := 0.6; -- surface inversion potential + lambda : real := 0.02; -- channel lenght modulation + tox : real := 1.0e-7; -- thin oxide thickness + nsub : real := 0.0; -- Substrate doping + nss : real := 0.0; -- Surface STate density + ld : real := 0.0; -- lateral diffusion; + tpg : real := 1.0; -- Type of Gate material + uo : real := 600.0; -- Surface mobility + af : real := 1.0; -- flicker noise exponent + kf : real := 0.0; -- fliccker noise coefficient + iss : real := 1.0e-14; -- bulk junction saturation current + js : real := 0.0; -- bulk junctioin saturatioin current/ sqr meter + pb : real := 0.80; -- bulk junction potential + cj : real := 0.0; -- Zero-bias bulk capacitance/ sqr meter + mj : real := 0.5; -- bulk junctioin grading coefficient + cjsw : real := 0.0; -- Zero bias perimeter capacitance / sqr meter + mjsw : real := 0.33; -- Perimiter capacitance rading coefficient + fc : real := 0.5; -- forward-bais depletion capacitance coeff +-- cgbo : real := 4.0e-10; -- gate-bulk overlap cap / meter +-- cgdo : real := 1.5e-10; -- gate-drain overlap cap / meter +-- cgso : real := 1.5e-10; -- gate-source overlap cap / meter + cgbo : real := 2.0e-10; -- gate-bulk overlap cap / meter + cgdo : real := 4.0e-11; -- gate-drain overlap cap / meter + cgso : real := 4.0e-11; -- gate-source overlap cap / meter + rd : real := 1.0; -- drain ohmic resistance + rs : real := 1.0; -- source ohmic resistance + rsh : real := 0.0); -- source and drain sheet resistance + port (terminal g,s,d,b : electrical); +end entity pmos; + +architecture behav of pmos is + terminal d1, s1 : electrical; + quantity vds across idsg through d1 to s1; + quantity vdsr across idsr through d1 to d; + quantity vgs across igs through g to s1; + quantity vbs across ibs through s1 to b; + quantity vbd across ibd through d1 to b; +-- new quantities added for source resistance + quantity vsr across isr through s1 to s; + quantity iss, isd : real := 1.0e-12; + quantity beta : real := 8.85e-05; -- gain + quantity leff : real := 1.0; -- effective length + constant gmin : real := 1.0e-12; + quantity vth : real := 0.5; -- threshold voltage + quantity ktq : real := 2.586e-2; -- (kT/q) thermal voltage at T=300K + --constant k : real := 1.38e-23; -- J/K ..... boltzman constant + -- T = 300 K ............ Absolute temperature + --constant q : real := 1.60e-19; -- C ....... magnitude of electron charge + constant cox_prime : real := 3.4515e-8; -- oxide capacitance per unit area F/cm2. cox_prime = EOX/TOX + quantity cox : real := 3.4515e-8; + quantity vds_free : real := 5.0; + quantity vgs_free : real := 0.0; + constant as : real := 15.0e-12; -- source area + constant ad : real := 15.0e-12; -- drain area + +begin + ------ Setting initial conditions + initreg : break vgs => 0.0, vds => 0.0, vth => 0.5; + + thres_volt : vth == vto + (gamma *(sqrt((2.0*phi)-vbs) - sqrt(phi))); + eff_length : leff == L - (2.0*ld); + therm_volt : ktq == 2.586e-2 * (T/300.0); + sat_scurr : iss == js*as; + sat_dcurr : isd == js*ad; +-- gn : beta == 8.85e-05 * (W/L); + gn : beta == kp * ( w/leff); +-- opn : vdsg == 1.0e9 * idsgi; -- almost open + d12_res : vdsr == idsr * rd; +-- g12res : vgsr == igsr * rs; +-- g_oup : vgs == igs * 1.0e9; +-- oup_res : vds == ids * 1.0e9; + oup_res : vds_free == vds; + inp_res : vgs_free == vgs; + gre : vgs == igs * 1.0e9; + capeqn : cox == cox_prime * W * Leff; -- cox_prime * W * Leff + src_res : isr == vsr * rs; + +---- Current is in Micro Amps. +-- Normal mode + ------ Cut off Region + regions : if((vgs > vth) and (vds <= 0.0))use + gncn : idsg == 1.0e-8 * vds; + ------ Linear Region + elsif((vds >= (vgs-vth)) and (vgs <= vth) and (vds <= 0.0)) use + gnln : idsg == -1.0*vds*beta*((vgs_free-vth) - (vds_free/2.0))*(1.0 - lambda*vds_free); + ------ Saturation Region + elsif((vds < vgs-vth) and (vgs <= vth) and (vds <= 0.0)) use + gnsn : idsg == -1.0*(beta/2.0)*(pow((vgs_free-vth),2.0))*(1.0 - lambda*vds_free); + +-- Inversion mode + ------ Cut off Region + elsif((vgs > vth) and (vds > 0.0))use + gnci : idsg == 1.0e-9 * vds; + ------ Linear Region + elsif(((-1.0*vds) >= (vgs-vth)) and (vgs <= vth) and (vds > 0.0)) use + gnli : idsg == -1.0*vds*beta*((vgs_free-vth) + (vds_free/2.0))*(1.0 + lambda*vds_free); + ------ Saturation Region + elsif(((-1.0*vds) < vgs-vth) and (vgs >= vth) and (vds > 0.0)) use + gnsi : idsg == (beta/2.0)*(pow((vgs_free-vth),2.0))*(1.0 + lambda*vds_free); + end use; + +----- Substrate diode equations + initsub : break vbd => 0.0, vbs => 0.0, ibs => 0.0, ibd => 0.0; + + ----- Substrate to source + subcond1 : if(vbs > 0.0) use + bulk1 : ibs == ((iss*(exp(vbs/ktq) - 1.0)) + (gmin*vbs)); + elsif(vbs <= 0.0 ) use + bulk2 : ibs == ((iss*(vbs/ktq)) + (gmin*vbs)); + end use; + ----- Substrate to drain + subcond2 : if(vbd > 0.0) use + bulk3 : ibd == ((isd*(exp(vbd/ktq) - 1.0)) + (gmin*vbd)); + elsif(vbd <= 0.0 ) use + bulk4 : ibd == ((isd*(vbd/ktq)) + (gmin*vbd)); + end use; + +end architecture behav; --- of pmos; + + +---- DC Voltage source + +use work.electricalsystem.all; + +entity DCVSrc is + generic (v : real := 10.0); -- voltage + port (terminal pos, neg : electrical); +end entity DCVSrc; + +architecture behav of DCVSrc is + terminal temp : electrical; + quantity vdc across idc through temp to neg; + quantity vtemp across itemp through pos to temp; + +begin + + VSrc : vdc == v; + temp_volt : vtemp == itemp * 1.0e-03; + +end architecture behav; --- of DCVSrc + +--- ramp source + +use work.electricalSystem.all; + +ENTITY rampSource IS + GENERIC( amp : real := 1.0); + PORT( TERMINAL ta2,tb2 : electrical);--Interface ports. +END rampSource; + +--architecture declaration. +ARCHITECTURE rampbehavior OF rampSource IS +--quantity declarations. + quantity Vramp across Iramp through ta2 to tb2; + +BEGIN + + -- The sinusoidal voltage source equation. + vsource: Vramp == (amp * real(time'pos(now)) * 1.0e-15) ; + +END ARCHITECTURE rampbehavior; + + +------ inverter circuit + +use std.textio.all; +use work.electricalsystem.all; + +entity inv is +end entity; + +architecture test of inv is + terminal inv_in, inv_src, inv_out : electrical; + quantity vrout across irout through inv_out to electrical'reference; + quantity icout through inv_out to electrical'reference; +-- quantity vin across iin through inv_in to electrical'reference; +-- signal vgs_sig : real := 0.0; +--quantity vdd across asource to electrical'reference; + + component nmos_comp is + generic(mos_type : real := 1.0; -- +1.0 for nmos , -1.0 for pmos + T : real := 300.0; + W : real := 1.0; + L : real := 1.0; + vto : real := 1.0; -- Zero-bais threshold voltage + kp : real := 2.0e-5; -- transcondiuctanec parameter + gamma : real := 0.0; -- body-effect parameter + phi : real := 0.6; -- surface inversion potential + lambda : real := 0.02; -- channel lenght modulation + tox : real := 1.0e-7; -- thin oxide thickness + nsub : real := 0.0; -- Substrate doping + nss : real := 0.0; -- Surface STate density + ld : real := 0.0; -- lateral diffusion; + tpg : real := 1.0; -- Type of Gate material + uo : real := 600.0; -- Surface mobility + af : real := 1.0; -- flicker noise exponent + kf : real := 0.0; -- fliccker noise coefficient + iss : real := 1.0e-14; -- bulk junction saturation current + js : real := 0.0; -- bulk junctioin saturatioin current/ sqr meter + pb : real := 0.80; -- bulk junction potential + cj : real := 0.0; -- Zero-bias bulk capacitance/ sqr meter + mj : real := 0.5; -- bulk junctioin grading coefficient + cjsw : real := 0.0; -- Zero bias perimeter capacitance / sqr meter + mjsw : real := 0.33; -- Perimiter capacitance rading coefficient + fc : real := 0.5; -- forward-bais depletion capacitance coeff +-- cgbo : real := 4.0e-10; -- gate-bulk overlap cap / meter +-- cgdo : real := 1.5e-10; -- gate-drain overlap cap / meter +-- cgso : real := 1.5e-10; -- gate-source overlap cap / meter + cgbo : real := 2.0e-10; -- gate-bulk overlap cap / meter + cgdo : real := 4.0e-11; -- gate-drain overlap cap / meter + cgso : real := 4.0e-11; -- gate-source overlap cap / meter + rd : real := 1.0; -- drain ohmic resistance + rs : real := 1.0; -- source ohmic resistance + rsh : real := 0.0); -- source and drain sheet resistance + port (terminal g,s,d,b : electrical); + end component; + for all :nmos_comp use entity work.nmos(behav); + + component pmos_comp is + generic(mos_type : real := 1.0; -- +1.0 for nmos , -1.0 for pmos + T : real := 300.0; + W : real := 1.0; + L : real := 1.0; + vto : real := 1.0; -- Zero-bais threshold voltage + kp : real := 2.0e-5; -- transcondiuctanec parameter + gamma : real := 0.0; -- body-effect parameter + phi : real := 0.6; -- surface inversion potential + lambda : real := 0.02; -- channel lenght modulation + tox : real := 1.0e-7; -- thin oxide thickness + nsub : real := 0.0; -- Substrate doping + nss : real := 0.0; -- Surface STate density + ld : real := 0.0; -- lateral diffusion; + tpg : real := 1.0; -- Type of Gate material + uo : real := 600.0; -- Surface mobility + af : real := 1.0; -- flicker noise exponent + kf : real := 0.0; -- fliccker noise coefficient + iss : real := 1.0e-14; -- bulk junction saturation current + js : real := 0.0; -- bulk junctioin saturatioin current/ sqr meter + pb : real := 0.80; -- bulk junction potential + cj : real := 0.0; -- Zero-bias bulk capacitance/ sqr meter + mj : real := 0.5; -- bulk junctioin grading coefficient + cjsw : real := 0.0; -- Zero bias perimeter capacitance / sqr meter + mjsw : real := 0.33; -- Perimiter capacitance rading coefficient + fc : real := 0.5; -- forward-bais depletion capacitance coeff +-- cgbo : real := 4.0e-10; -- gate-bulk overlap cap / meter +-- cgdo : real := 1.5e-10; -- gate-drain overlap cap / meter +-- cgso : real := 1.5e-10; -- gate-source overlap cap / meter + cgbo : real := 2.0e-10; -- gate-bulk overlap cap / meter + cgdo : real := 4.0e-11; -- gate-drain overlap cap / meter + cgso : real := 4.0e-11; -- gate-source overlap cap / meter + rd : real := 1.0; -- drain ohmic resistance + rs : real := 1.0; -- source ohmic resistance + rsh : real := 0.0); -- source and drain sheet resistance + port (terminal g,s,d,b : electrical); + end component; + for all :pmos_comp use entity work.pmos(behav); + + component DCVSrc + generic (v : real := 10.0); -- voltage + port (terminal pos, neg : electrical); + end component; + for all : DCVSrc + use entity work.DCVSrc(behav); + + component rampSource + GENERIC( amp : real := 1.0); + PORT( TERMINAL ta2,tb2 : electrical);--Interface ports. + END component; + for all : rampsource use entity work.rampsource(rampbehavior); + +begin + inpramp : rampsource generic map(5.0e+7) + port map(inv_in, electrical'reference); + + inpdc : DCVSrc generic map (5.0) + port map(inv_src, electrical'reference); + + + nm : nmos_comp + generic map(vto => 0.7, w => 3.0e-6, l => 3.0e-6, cj => 0.00044, cjsw => 4.0e-4, mj => 0.5, mjsw => 0.3, pb => 0.7, js => 1.0e-5) +-- generic map(mos_type => 1.0, vto => 0.7, w => 3.0e-6, l => 3.0e-6, kp => 4.0e-5, gamma => 1.1, phi => 0.6, lambda => 0.01, cgso => 3.0e-10, cgdo => 3.0e-10, cgbo => 5.0e-10, cj => 0.00044, cjsw => 4.0e-4, mj => 0.5, mjsw => 0.3, pb => 0.7, js => 1.0e-5, ld => 3.5e-7) + port map(inv_in, electrical'reference, inv_out, electrical'reference); + + pm : pmos_comp + generic map(vto => -0.7, w => 9.0e-6, l => 3.0e-6, cj => 0.00015, cjsw => 4.0e-4, mj => 0.6, mjsw => 0.6, pb => 0.6, js => 1.0e-5) +-- generic map(mos_type => -1.0, vto => -0.8, w => 9.0e-6, l => 3.0e-6, kp => 1.2e-5, gamma => 0.6, phi => 0.6, lambda => 0.03, cgso => 2.5e-10, cgdo => 2.5e-10, cgbo => 5.0e-10, cj => 0.00015, cjsw => 4.0e-4, mj => 0.6, mjsw => 0.6, pb => 0.6, js => 1.0e-5, ld => 2.5e-7) + port map(inv_in, inv_src, inv_out, inv_src); + + oupres : vrout == irout * 1.0e9; + oupcap : icout == 1.0e-13 * vrout'dot; + brkcap : break vrout => 5.0; +end architecture test; -- inv diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/analog_models/static_cmos_inv_sqr.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/analog_models/static_cmos_inv_sqr.ams new file mode 100644 index 000000000..ad3fdca4d --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/analog_models/static_cmos_inv_sqr.ams @@ -0,0 +1,531 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: static_cmos_inv_sqr.ams,v 1.1 2002-03-27 22:11:16 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +-- This ckt is used to find the output characteristics of a cmos inverter +-- The ckt used here is from sedra and smith's page no. 565, fig 13.13 +-- The mos W/L are according to the model specified in spice using the deck +-- provided in the book. +-- The vgs, resistance is now removed, to avoid the RC effect on the imput. +-- the square input is used + + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH; + FUNCTION POW(X,Y: real) RETURN real; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; +END PACKAGE electricalSystem; + + +----------------------------------------------------------------------- +-- G B D1 1.0 ohm D +-- o o-----|>|--o---o----/\/\---------o /\ +-- | | | | |+ +-- Vgs < - Idsg( ) > Vdso +-- > V | < |- +-- | - | | | +-- S1 o------o--o------------------------------o S1V +-- | +-- > +-- < rs= 1.0 ohm +-- | +-- 0 S +----------------------------------------------------------------------- + +----- NMOS +--use std.textio.all; +use work.electricalsystem.all; + +entity nmos is + generic(mos_type : real := 1.0; -- +1.0 for nmos , -1.0 for pmos + T : real := 300.0; + W : real := 1.0; + L : real := 1.0; + vto : real := 1.0; -- Zero-bais threshold voltage + kp : real := 2.0e-5; -- transcondiuctanec parameter + gamma : real := 0.0; -- body-effect parameter + phi : real := 0.6; -- surface inversion potential + lambda : real := 0.02; -- channel lenght modulation + tox : real := 1.0e-7; -- thin oxide thickness + nsub : real := 0.0; -- Substrate doping + nss : real := 0.0; -- Surface STate density + ld : real := 0.0; -- lateral diffusion; + tpg : real := 1.0; -- Type of Gate material + uo : real := 600.0; -- Surface mobility + af : real := 1.0; -- flicker noise exponent + kf : real := 0.0; -- fliccker noise coefficient + iss : real := 1.0e-14; -- bulk junction saturation current + js : real := 0.0; -- bulk junctioin saturatioin current/ sqr meter + pb : real := 0.80; -- bulk junction potential + cj : real := 0.0; -- Zero-bias bulk capacitance/ sqr meter + mj : real := 0.5; -- bulk junctioin grading coefficient + cjsw : real := 0.0; -- Zero bias perimeter capacitance / sqr meter + mjsw : real := 0.33; -- Perimiter capacitance rading coefficient + fc : real := 0.5; -- forward-bais depletion capacitance coeff +-- cgbo : real := 4.0e-10; -- gate-bulk overlap cap / meter +-- cgdo : real := 1.5e-10; -- gate-drain overlap cap / meter +-- cgso : real := 1.5e-10; -- gate-source overlap cap / meter + cgbo : real := 2.0e-10; -- gate-bulk overlap cap / meter + cgdo : real := 4.0e-11; -- gate-drain overlap cap / meter + cgso : real := 4.0e-11; -- gate-source overlap cap / meter + rd : real := 1.0; -- drain ohmic resistance + rs : real := 1.0; -- source ohmic resistance + rsh : real := 0.0); -- source and drain sheet resistance + port (terminal g,s,d,b : electrical); +end entity nmos; + +architecture behav of nmos is + terminal d1, s1 : electrical; + quantity vds across idsg through d1 to s1; + quantity vdsr across idsr through d1 to d; + quantity vgs across igs through g to s1; + quantity vbs across ibs through b to s1; + quantity vbd across ibd through b to d1; +-- new quantities added for source resistance + quantity vsr across isr through s1 to s; + quantity iss, isd : real := 1.0e-12; + quantity beta : real := 8.85e-05; -- gain + quantity leff : real := 1.0; -- effective length + constant gmin : real := 1.0e-12; + quantity vth : real := 0.5; -- threshold voltage + quantity ktq : real := 2.586e-2; -- (kT/q) thermal voltage at T=300K + --constant k : real := 1.38e-23; -- J/K ..... boltzman constant + -- T = 300 K ............ Absolute temperature + --constant q : real := 1.60e-19; -- C ....... magnitude of electron charge + constant cox_prime : real := 3.4515e-8; -- oxide capacitance per unit area F/cm2. cox_prime = EOX/TOX + quantity cox : real := 3.4515e-8; + quantity vds_free : real := 5.0; + quantity vgs_free : real := 0.0; + constant as : real := 15.0e-12; -- source area + constant ad : real := 15.0e-12; -- drain area + +begin + ------ Setting initial conditions + initreg : break vgs => 0.0, vds => 5.0, vth => 0.5; + + thres_volt : vth == vto + (gamma *(sqrt((2.0*phi)-vbs) - sqrt(phi))); + eff_length : leff == L - (2.0*ld); + therm_volt : ktq == 2.586e-2 * (T/300.0); + sat_scurr : iss == js*as; + sat_dcurr : isd == js*ad; +-- gn : beta == 8.85e-05 * (W/L); + gn : beta == kp * ( w/leff); +-- opn : vdsg == 1.0e9 * idsgi; -- almost open + d12_res : vdsr == idsr * rd; +-- g12res : vgsr == igsr * rs; +-- g_oup : vgs == igs * 1.0e9; +-- oup_res : vds == ids * 1.0e9; + oup_res : vds_free == vds; + inp_res : vgs_free == vgs; + gre : vgs == igs * 1.0e9; + capeqn : cox == cox_prime * W * Leff; -- cox_prime * W * Leff + src_res : isr == vsr * rs; + +---- Current is in Micro Amps. +-- Normal mode + ------ Cut off Region + regions : if((vgs < vth) and (vds >= 0.0))use + gncn : idsg == 1.0e-9 * vds; + ------ Linear Region + elsif((vds <= (vgs-vth)) and (vgs >= vth) and (vds >= 0.0)) use + gnln : idsg == vds*beta*((vgs_free-vth) - (vds_free/2.0))*(1.0 + lambda*vds_free); + ------ Saturation Region + elsif((vds > vgs-vth) and (vgs >= vth) and (vds >= 0.0)) use + gnsn : idsg == (beta/2.0)*(pow((vgs_free-vth),2.0))*(1.0 + lambda*vds_free); + +-- Inversion mode + ------ Cut off Region + elsif((vgs < vth) and (vds < 0.0))use + gnci : idsg == 1.0e-9 * vds; + ------ Linear Region + elsif(((-1.0*vds) <= (vgs-vth)) and (vgs >= vth) and (vds < 0.0)) use + gnli : idsg == vds*beta*((vgs_free-vth) + (vds_free/2.0))*(1.0 - lambda*vds_free); + ------ Saturation Region + elsif(((-1.0*vds) > vgs-vth) and (vgs >= vth) and (vds < 0.0)) use + gnsi : idsg == -1.0*(beta/2.0)*(pow((vgs_free-vth),2.0))*(1.0 - lambda*vds_free); + end use; + +----- Substrate diode equations + initsub : break vbd => 0.0, vbs => 0.0, ibs => 0.0, ibd => 0.0; + + ----- Substrate to source + subcond1 : if(vbs > 0.0) use + bulk1 : ibs == ((iss*(exp(vbs/ktq) - 1.0)) + (gmin*vbs)); + elsif(vbs <= 0.0 ) use + bulk2 : ibs == ((iss*(vbs/ktq)) + (gmin*vbs)); + end use; + ----- Substrate to drain + subcond2 : if(vbd > 0.0) use + bulk3 : ibd == ((isd*(exp(vbd/ktq) - 1.0)) + (gmin*vbd)); + elsif(vbd <= 0.0 ) use + bulk4 : ibd == ((isd*(vbd/ktq)) + (gmin*vbd)); + end use; + +end architecture behav; --- of nmos; + + +----------------------------------------------------------------------- +-- G B D1 1.0 ohm D +-- o o-----|>|--o---o----/\/\---------o /\ +-- | | | | |+ +-- Vgs < - Idsg( ) > Vdso +-- > V | < |- +-- | - | | | +-- S1 o------o--o------------------------------o S1V +-- | +-- > +-- < rs= 1.0 ohm +-- | +-- 0 S +----------------------------------------------------------------------- + +----- PMOS +--use std.textio.all; +use work.electricalsystem.all; + +entity pmos is + generic(mos_type : real := 1.0; -- +1.0 for nmos , -1.0 for pmos + T : real := 300.0; + W : real := 1.0; + L : real := 1.0; + vto : real := 1.0; -- Zero-bais threshold voltage + kp : real := 2.0e-5; -- transcondiuctanec parameter + gamma : real := 0.0; -- body-effect parameter + phi : real := 0.6; -- surface inversion potential + lambda : real := 0.02; -- channel lenght modulation + tox : real := 1.0e-7; -- thin oxide thickness + nsub : real := 0.0; -- Substrate doping + nss : real := 0.0; -- Surface STate density + ld : real := 0.0; -- lateral diffusion; + tpg : real := 1.0; -- Type of Gate material + uo : real := 600.0; -- Surface mobility + af : real := 1.0; -- flicker noise exponent + kf : real := 0.0; -- fliccker noise coefficient + iss : real := 1.0e-14; -- bulk junction saturation current + js : real := 0.0; -- bulk junctioin saturatioin current/ sqr meter + pb : real := 0.80; -- bulk junction potential + cj : real := 0.0; -- Zero-bias bulk capacitance/ sqr meter + mj : real := 0.5; -- bulk junctioin grading coefficient + cjsw : real := 0.0; -- Zero bias perimeter capacitance / sqr meter + mjsw : real := 0.33; -- Perimiter capacitance rading coefficient + fc : real := 0.5; -- forward-bais depletion capacitance coeff + cgbo : real := 2.0e-10; -- gate-bulk overlap cap / meter + cgdo : real := 4.0e-11; -- gate-drain overlap cap / meter + cgso : real := 4.0e-11; -- gate-source overlap cap / meter + rd : real := 1.0; -- drain ohmic resistance + rs : real := 1.0; -- source ohmic resistance + rsh : real := 0.0); -- source and drain sheet resistance + port (terminal g,s,d,b : electrical); +end entity pmos; + +architecture behav of pmos is + terminal d1, s1 : electrical; + quantity vds across idsg through d1 to s1; + quantity vdsr across idsr through d1 to d; + quantity vgs across igs through g to s1; + quantity vbs across ibs through s1 to b; + quantity vbd across ibd through d1 to b; +-- new quantities added for source resistance + quantity vsr across isr through s1 to s; + quantity iss, isd : real := 1.0e-12; + quantity beta : real := 8.85e-05; -- gain + quantity leff : real := 1.0; -- effective length + constant gmin : real := 1.0e-12; + quantity vth : real := 0.5; -- threshold voltage + quantity ktq : real := 2.586e-2; -- (kT/q) thermal voltage at T=300K + --constant k : real := 1.38e-23; -- J/K ..... boltzman constant + -- T = 300 K ............ Absolute temperature + --constant q : real := 1.60e-19; -- C ....... magnitude of electron charge + constant cox_prime : real := 3.4515e-8; -- oxide capacitance per unit area F/cm2. cox_prime = EOX/TOX + quantity cox : real := 3.4515e-8; + quantity vds_free : real := 5.0; + quantity vgs_free : real := 0.0; + constant as : real := 15.0e-12; -- source area + constant ad : real := 15.0e-12; -- drain area + +begin + ------ Setting initial conditions + initreg : break vgs => 0.0, vds => 0.0, vth => 0.5; + + thres_volt : vth == vto + (gamma *(sqrt((2.0*phi)-vbs) - sqrt(phi))); + eff_length : leff == L - (2.0*ld); + therm_volt : ktq == 2.586e-2 * (T/300.0); + sat_scurr : iss == js*as; + sat_dcurr : isd == js*ad; + gn : beta == kp * ( w/leff); + d12_res : vdsr == idsr * rd; + oup_res : vds_free == vds; + inp_res : vgs_free == vgs; + gre : vgs == igs * 1.0e9; + capeqn : cox == cox_prime * W * Leff; -- cox_prime * W * Leff + src_res : isr == vsr * rs; + +---- Current is in Micro Amps. +-- Normal mode + ------ Cut off Region + regions : if((vgs > vth) and (vds <= 0.0))use + gncn : idsg == 1.0e-9 * vds; + ------ Linear Region + elsif((vds >= (vgs-vth)) and (vgs <= vth) and (vds <= 0.0)) use + gnln : idsg == -1.0*vds*beta*((vgs_free-vth) - (vds_free/2.0))*(1.0 - lambda*vds_free); + ------ Saturation Region + elsif((vds < vgs-vth) and (vgs <= vth) and (vds <= 0.0)) use + gnsn : idsg == -1.0*(beta/2.0)*(pow((vgs_free-vth),2.0))*(1.0 - lambda*vds_free); + +-- Inversion mode + ------ Cut off Region + elsif((vgs > vth) and (vds > 0.0))use + gnci : idsg == 1.0e-9 * vds; + ------ Linear Region + elsif(((-1.0*vds) >= (vgs-vth)) and (vgs <= vth) and (vds > 0.0)) use + gnli : idsg == -1.0*vds*beta*((vgs_free-vth) + (vds_free/2.0))*(1.0 + lambda*vds_free); + ------ Saturation Region + elsif(((-1.0*vds) < vgs-vth) and (vgs >= vth) and (vds > 0.0)) use + gnsi : idsg == (beta/2.0)*(pow((vgs_free-vth),2.0))*(1.0 + lambda*vds_free); + end use; + +----- Substrate diode equations + initsub : break vbd => 0.0, vbs => 0.0, ibs => 0.0, ibd => 0.0; + + ----- Substrate to source + subcond1 : if(vbs > 0.0) use + bulk1 : ibs == ((iss*(exp(vbs/ktq) - 1.0)) + (gmin*vbs)); + elsif(vbs <= 0.0 ) use + bulk2 : ibs == ((iss*(vbs/ktq)) + (gmin*vbs)); + end use; + ----- Substrate to drain + subcond2 : if(vbd > 0.0) use + bulk3 : ibd == ((isd*(exp(vbd/ktq) - 1.0)) + (gmin*vbd)); + elsif(vbd <= 0.0 ) use + bulk4 : ibd == ((isd*(vbd/ktq)) + (gmin*vbd)); + end use; + +end architecture behav; --- of pmos; + + +---- DC Voltage source + +use work.electricalsystem.all; + +entity DCVSrc is + generic (v : real := 10.0); -- voltage + port (terminal pos, neg : electrical); +end entity DCVSrc; + +architecture behav of DCVSrc is + terminal temp : electrical; + quantity vdc across idc through temp to neg; + quantity vtemp across itemp through pos to temp; + +begin + + VSrc : vdc == v; + temp_volt : vtemp == itemp * 1.0e-03; + +end architecture behav; --- of DCVSrc + +------- Square wave generator + +use work.electricalsystem.all; + +entity sqr_gen is + generic (vlo : real := 0.0; + vhi : real := 10.0; + ped : time := 1 ns); + port (terminal pos, neg : electrical); +end entity sqr_gen; + +architecture behav of sqr_gen is + quantity vsqr across isqr through pos to neg; + signal vsig : real := 0.0; + signal clk : bit := '0'; +begin + + vsqr == vsig; + break on vsig; + + clock : process + begin + clk <= '0'; + wait for ped; + clk <= '1'; + wait for ped; + end process; --- clock + + + generator : process + variable xv : real := 0.0; + begin + if(clk = '1') then + xv := vhi; + elsif(clk = '0') then + xv := vlo; + end if; + vsig <= xv; + wait on clk; + end process; --- generator; + +end architecture behav; --- of sqr_gen + + +------ inverter circuit + +use std.textio.all; +use work.electricalsystem.all; + +entity inv is +end entity; + +architecture test of inv is + terminal inv_in1, inv_in2, inv_src, inv_out : electrical; + quantity vrin across irin through inv_in1 to inv_in2; + quantity vcin across icin through inv_in2 to electrical'reference; + quantity vrout across irout through inv_out to electrical'reference; + quantity icout through inv_out to electrical'reference; + + component nmos_comp is + generic(mos_type : real := 1.0; -- +1.0 for nmos , -1.0 for pmos + T : real := 300.0; + W : real := 1.0; + L : real := 1.0; + vto : real := 1.0; -- Zero-bais threshold voltage + kp : real := 2.0e-5; -- transcondiuctanec parameter + gamma : real := 0.0; -- body-effect parameter + phi : real := 0.6; -- surface inversion potential + lambda : real := 0.02; -- channel lenght modulation + tox : real := 1.0e-7; -- thin oxide thickness + nsub : real := 0.0; -- Substrate doping + nss : real := 0.0; -- Surface STate density + ld : real := 0.0; -- lateral diffusion; + tpg : real := 1.0; -- Type of Gate material + uo : real := 600.0; -- Surface mobility + af : real := 1.0; -- flicker noise exponent + kf : real := 0.0; -- fliccker noise coefficient + iss : real := 1.0e-14; -- bulk junction saturation current + js : real := 0.0; -- bulk junctioin saturatioin current/ sqr meter + pb : real := 0.80; -- bulk junction potential + cj : real := 0.0; -- Zero-bias bulk capacitance/ sqr meter + mj : real := 0.5; -- bulk junctioin grading coefficient + cjsw : real := 0.0; -- Zero bias perimeter capacitance / sqr meter + mjsw : real := 0.33; -- Perimiter capacitance rading coefficient + fc : real := 0.5; -- forward-bais depletion capacitance coeff +-- cgbo : real := 4.0e-10; -- gate-bulk overlap cap / meter +-- cgdo : real := 1.5e-10; -- gate-drain overlap cap / meter +-- cgso : real := 1.5e-10; -- gate-source overlap cap / meter + cgbo : real := 2.0e-10; -- gate-bulk overlap cap / meter + cgdo : real := 4.0e-11; -- gate-drain overlap cap / meter + cgso : real := 4.0e-11; -- gate-source overlap cap / meter + rd : real := 1.0; -- drain ohmic resistance + rs : real := 1.0; -- source ohmic resistance + rsh : real := 0.0); -- source and drain sheet resistance + port (terminal g,s,d,b : electrical); + end component; + for all :nmos_comp use entity work.nmos(behav); + + component pmos_comp is + generic(mos_type : real := 1.0; -- +1.0 for nmos , -1.0 for pmos + T : real := 300.0; + W : real := 1.0; + L : real := 1.0; + vto : real := 1.0; -- Zero-bais threshold voltage + kp : real := 2.0e-5; -- transcondiuctanec parameter + gamma : real := 0.0; -- body-effect parameter + phi : real := 0.6; -- surface inversion potential + lambda : real := 0.02; -- channel lenght modulation + tox : real := 1.0e-7; -- thin oxide thickness + nsub : real := 0.0; -- Substrate doping + nss : real := 0.0; -- Surface STate density + ld : real := 0.0; -- lateral diffusion; + tpg : real := 1.0; -- Type of Gate material + uo : real := 600.0; -- Surface mobility + af : real := 1.0; -- flicker noise exponent + kf : real := 0.0; -- fliccker noise coefficient + iss : real := 1.0e-14; -- bulk junction saturation current + js : real := 0.0; -- bulk junctioin saturatioin current/ sqr meter + pb : real := 0.80; -- bulk junction potential + cj : real := 0.0; -- Zero-bias bulk capacitance/ sqr meter + mj : real := 0.5; -- bulk junctioin grading coefficient + cjsw : real := 0.0; -- Zero bias perimeter capacitance / sqr meter + mjsw : real := 0.33; -- Perimiter capacitance rading coefficient + fc : real := 0.5; -- forward-bais depletion capacitance coeff +-- cgbo : real := 4.0e-10; -- gate-bulk overlap cap / meter +-- cgdo : real := 1.5e-10; -- gate-drain overlap cap / meter +-- cgso : real := 1.5e-10; -- gate-source overlap cap / meter + cgbo : real := 2.0e-10; -- gate-bulk overlap cap / meter + cgdo : real := 4.0e-11; -- gate-drain overlap cap / meter + cgso : real := 4.0e-11; -- gate-source overlap cap / meter + rd : real := 1.0; -- drain ohmic resistance + rs : real := 1.0; -- source ohmic resistance + rsh : real := 0.0); -- source and drain sheet resistance + port (terminal g,s,d,b : electrical); + end component; + for all :pmos_comp use entity work.pmos(behav); + + component DCVSrc + generic (v : real := 10.0); -- voltage + port (terminal pos, neg : electrical); + end component; + for all : DCVSrc + use entity work.DCVSrc(behav); + + component sqr_comp is + generic(vlo : real := 0.0; + vhi : real := 10.0; + ped : time := 1 ns); + port (terminal pos, neg : electrical); + end component; + for all : sqr_comp use entity work.sqr_gen(behav); + +begin + sqr : sqr_comp + generic map(0.0, 5.0, 50 ns) + port map(inv_in1, electrical'reference); + + inpdc : DCVSrc generic map (5.0) + port map(inv_src, electrical'reference); + + resin : vrin == irin * 1.0e3; + capin : icin == 4.0e-12 * vcin'dot; + oup : vrout == irout * 1.0e9; + capbrk : break vcin => 5.0, vrout => 0.0; + capout : icout == 1.0e-13 * vrout'dot; + nm : nmos_comp + generic map(vto => 0.7, w => 3.0e-6, l => 3.0e-6, cj => 0.00044, cjsw => 4.0e-4, mj => 0.5, mjsw => 0.3, pb => 0.7, js => 1.0e-5) + port map(inv_in2, electrical'reference, inv_out, electrical'reference); + + pm : pmos_comp + generic map(vto => -0.7, w => 9.0e-6, l => 3.0e-6, cj => 0.00015, cjsw => 4.0e-4, mj => 0.6, mjsw => 0.6, pb => 0.6, js => 1.0e-5) + port map(inv_in2, inv_src, inv_out, inv_src); + +end architecture test; -- inv diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/analog_models/static_njfet.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/analog_models/static_njfet.ams new file mode 100644 index 000000000..b43318f43 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/analog_models/static_njfet.ams @@ -0,0 +1,219 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: static_njfet.ams,v 1.1 2002-03-27 22:11:16 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +-- This ckt is used to find the output and transfer characteristics of an +-- n-channel JFET model. +-- The model is Spice2 model, taken from the SPICE book, pg 142, fig 3.7 +------------------------------------------------------------------------ +-- The ckt used here is from sedra and smith's page no. 215, fig 5.18 +------------------------------------------------------------------------ + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION POW(X,Y: real) RETURN real; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; +END PACKAGE electricalSystem; + + +----------------------------------------------------------------------- +-- G D1 rd D +-- o-----|>|--o-------/\/\---------o +-- | | +-- - Id ( ) +-- V | +-- - | +-- S1 o----------o +-- | +-- > +-- < rs +-- | +-- 0 S +----------------------------------------------------------------------- + +----- NMOS +--use std.textio.all; +use work.electricalsystem.all; + +entity njfet is + generic(T : real := 300.0; + vto : real := -2.0; -- Zero-bais threshold voltage + beta : real := 1.0e-4; -- transconductance parameter + lambda : real := 0.0; -- channel lenght modulation + af : real := 1.0; -- flicker noise exponent + kf : real := 0.0; -- flicker noise coefficient + iss : real := 1.0e-14; -- gate junction saturation current + pb : real := 1.0; -- gate junction potential + fc : real := 0.5; -- forward-bais depletion capacitance coeff + cgd : real := 4.0e-11; -- zero-bais gate-drain junction cap + cgs : real := 4.0e-11; -- zero-bias gate-source junction cap + rd : real := 1.0e-6; -- drain ohmic resistance + rs : real := 1.0e-6); -- source ohmic resistance + port (terminal g,s,d : electrical); +end entity njfet; + +architecture behav of njfet is + terminal d1, s1 : electrical; + quantity vds across id through d1 to s1; + quantity vrd across ird through d to d1; + quantity vrs across irs through s1 to s; + quantity vgs across igs through g to s1; + quantity vgd across igd through g to d1; + constant gmin : real := 1.0e-12; + quantity ktq : real := 2.586e-2; -- (kT/q) thermal voltage at T=300K + --constant k : real := 1.38e-23; -- J/K ..... boltzman constant + -- T = 300 K ............ Absolute temperature + --constant q : real := 1.60e-19; -- C ....... magnitude of electron charge + quantity vds_free : real := 2.0; + quantity vgs_free : real := 0.0; + quantity vgd_free : real := 2.0; + +begin + ------ Setting initial conditions + initreg : break vgs => 0.0, vds => 2.0, vgd => 2.0; + therm_volt : ktq == 2.586e-2 * (T/300.0); + dres : vrd == ird * rd; + oup_res : vds_free == vds; + inp_res : vgs_free == vgs; + vgdf : vgd_free == vgd; + sres : vrs == irs * rs; + +---- Current is in Amps. +-- Normal mode + ------ Cut off Region + regions : if((vgs <= vto) and (vds >= 0.0))use + gncn : id == 1.0e-9 * vds; + ------ Linear Region + elsif((vds < (vgs-vto)) and (vgs > vto) and (vds >= 0.0)) use + gnln : id == vds*beta*((2.0*(vgs_free-vto)) - vds_free)*(1.0 + lambda*vds_free); + ------ Saturation Region + elsif((vds >= vgs-vto) and (vgs > vto) and (vds >= 0.0)) use + gnsn : id == beta*(pow((vgs_free-vto),2.0))*(1.0 + lambda*vds_free); + +-- Inversted mode + ------ Cut off Region + elsif((vgd <= vto) and (vds < 0.0))use + gnci : id == 1.0e-9 * vds; + ------ Linear Region + elsif(((-1.0*vds) < (vgd-vto)) and (vgd > vto) and (vds < 0.0)) use + gnli : id == vds*beta*((2.0*(vgd_free-vto)) + vds_free)*(1.0 - lambda*vds_free); + ------ Saturation Region + elsif(((-1.0*vds) >= vgd-vto) and (vgd > vto) and (vds < 0.0)) use + gnsi : id == -1.0*(beta)*(pow((vgd_free-vto),2.0))*(1.0 - lambda*vds_free); + end use; + +----- Gate diode equations + initsub : break vgd => 0.0, vgs => 0.0, igs => 0.0, igd => 0.0; + + ----- Gate to source + subcond1 : if(vgs > -5.0*ktq) use + gsf : igs == ((iss*(exp(vgs/ktq) - 1.0)) + (gmin*vgs)); + elsif(vgs <= -5.0*ktq ) use + gsr : igs == -1.0*iss + (gmin*vgs); + end use; + ----- Gate to drain + subcond2 : if(vgd > -5.0*ktq) use + gdf : igd == ((iss*(exp(vgd/ktq) - 1.0)) + (gmin*vgd)); + elsif(vgd <= -5.0*ktq ) use + gdr : igd == -1.0*iss + (gmin*vgd); + end use; + +end architecture behav; --- of njfet; + +---- DC Voltage source + +use work.electricalsystem.all; + +entity DCVSrc is + generic (v : real := 10.0); -- voltage + port (terminal pos, neg : electrical); +end entity DCVSrc; + +architecture behav of DCVSrc is + terminal temp : electrical; + quantity vdc across idc through temp to neg; + quantity vtemp across itemp through pos to temp; + +begin + + VSrc : vdc == v; + temp_volt : vtemp == itemp * 1.0e-03; + +end architecture behav; --- of DCVSrc + + +------ njfet amplifier circuit + +use std.textio.all; +use work.electricalsystem.all; + +entity njfet_ckt is +end entity; + +architecture test of njfet_ckt is + terminal t1, t2, t3: electrical; + quantity vrd1 across ird1 through t1 to t2; + quantity vrs1 across irs1 through t3 to electrical'reference; + quantity vdd across idd through t1 to electrical'reference; + + + component njfet_comp is + generic(T : real := 300.0; + vto : real := -2.0; -- Zero-bais threshold voltage + beta : real := 1.0e-4; -- transconductance parameter + lambda : real := 0.0; -- channel lenght modulation + af : real := 1.0; -- flicker noise exponent + kf : real := 0.0; -- flicker noise coefficient + iss : real := 1.0e-14; -- gate junction saturation current + pb : real := 1.0; -- gate junction potential + fc : real := 0.5; -- forward-bais depletion capacitance coeff + cgd : real := 4.0e-11; -- zero-bais gate-drain junction cap + cgs : real := 4.0e-11; -- zero-bias gate-source junction cap + rd : real := 1.0e-6; -- drain ohmic resistance + rs : real := 1.0e-6); -- source ohmic resistance + port (terminal g,s,d : electrical); + end component; + for all :njfet_comp use entity work.njfet(behav); + +begin + + jn1 : njfet_comp + generic map(vto => -4.0, beta => 1.0e-3, lambda => 0.0) + port map(ground, t3, t2); + + rd1 : vrd1 == ird1 * 1.0e3; + rs1 : vrs1 == irs1 * 0.5e3; + src : vdd == 10.0; + +end architecture test; -- njfet_ckt diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/analog_models/static_pjfet.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/analog_models/static_pjfet.ams new file mode 100644 index 000000000..f707a96d9 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/analog_models/static_pjfet.ams @@ -0,0 +1,250 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: static_pjfet.ams,v 1.1 2002-03-27 22:11:16 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +-- This ckt is used to find the output and transfer characteristics of an +-- p-channel JFET model. +-- The model is Spice2 model, taken from the SPICE book, pg 142, fig 3.7 +------------------------------------------------------------------------ +-- The ckt used here is from sedra and smith's page no. 216, fig 5.20 +------------------------------------------------------------------------ + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION POW(X,Y: real) RETURN real; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; +END PACKAGE electricalSystem; + + +----------------------------------------------------------------------- +-- G D1 rd D +-- o-----|>|--o-------/\/\---------o +-- | | +-- - Id ( ) +-- V | +-- - | +-- S1 o----------o +-- | +-- > +-- < rs +-- | +-- 0 S +----------------------------------------------------------------------- + +----- P-JFET +--use std.textio.all; +use work.electricalsystem.all; + +entity pjfet is + generic(T : real := 300.0; + vto : real := -2.0; -- Zero-bais threshold voltage + beta : real := 1.0e-4; -- transconductance parameter + lambda : real := 0.0; -- channel lenght modulation + af : real := 1.0; -- flicker noise exponent + kf : real := 0.0; -- flicker noise coefficient + iss : real := 1.0e-14; -- gate junction saturation current + pb : real := 1.0; -- gate junction potential + fc : real := 0.5; -- forward-bais depletion capacitance coeff + cgd : real := 4.0e-11; -- zero-bais gate-drain junction cap + cgs : real := 4.0e-11; -- zero-bias gate-source junction cap + rd : real := 1.0e-6; -- drain ohmic resistance + rs : real := 1.0e-6); -- source ohmic resistance + port (terminal g,s,d : electrical); +end entity pjfet; + +architecture behav of pjfet is + terminal d1, s1 : electrical; + quantity vds across id through s1 to d1; + quantity vrd across ird through d1 to d; + quantity vrs across irs through s to s1; + quantity vgs across igs through s1 to g; + quantity vgd across igd through d1 to g; + constant gmin : real := 1.0e-12; + quantity ktq : real := 2.586e-2; -- (kT/q) thermal voltage at T=300K + --constant k : real := 1.38e-23; -- J/K ..... boltzman constant + -- T = 300 K ............ Absolute temperature + --constant q : real := 1.60e-19; -- C ....... magnitude of electron charge + quantity vds_free : real := 2.0; + quantity vgs_free : real := 0.0; + quantity vgd_free : real := 2.0; + +begin + ------ Setting initial conditions + initreg : break vgs => 0.0, vds => 2.0, vgd => 2.0; + therm_volt : ktq == 2.586e-2 * (T/300.0); + dres : vrd == ird * rd; + oup_res : vds_free == vds; + inp_res : vgs_free == vgs; + vgdf : vgd_free == vgd; + sres : vrs == irs * rs; + +---- Current is in Amps. +-- Normal mode + ------ Cut off Region + regions : if((vgs <= vto) and (vds >= 0.0))use + gncn : id == 1.0e-9 * vds; + ------ Linear Region + elsif((vds < (vgs-vto)) and (vgs > vto) and (vds >= 0.0)) use + gnln : id == vds*beta*((2.0*(vgs_free-vto)) - vds_free)*(1.0 + lambda*vds_free); + ------ Saturation Region + elsif((vds >= vgs-vto) and (vgs > vto) and (vds >= 0.0)) use + gnsn : id == beta*(pow((vgs_free-vto),2.0))*(1.0 + lambda*vds_free); + +-- Inversted mode + ------ Cut off Region + elsif((vgd <= vto) and (vds < 0.0))use + gnci : id == 1.0e-9 * vds; + ------ Linear Region + elsif(((-1.0*vds) < (vgd-vto)) and (vgd > vto) and (vds < 0.0)) use + gnli : id == vds*beta*((2.0*(vgd_free-vto)) + vds_free)*(1.0 - lambda*vds_free); + ------ Saturation Region + elsif(((-1.0*vds) >= vgd-vto) and (vgd > vto) and (vds < 0.0)) use + gnsi : id == -1.0*(beta)*(pow((vgd_free-vto),2.0))*(1.0 - lambda*vds_free); + end use; + +----- Gate diode equations + initsub : break vgd => 0.0, vgs => 0.0, igs => 0.0, igd => 0.0; + + ----- Gate to source + subcond1 : if(vgs > -5.0*ktq) use + gsf : igs == ((iss*(exp(vgs/ktq) - 1.0)) + (gmin*vgs)); + elsif(vgs <= -5.0*ktq ) use + gsr : igs == -1.0*iss + (gmin*vgs); + end use; + ----- Gate to drain + subcond2 : if(vgd > -5.0*ktq) use + gdf : igd == ((iss*(exp(vgd/ktq) - 1.0)) + (gmin*vgd)); + elsif(vgd <= -5.0*ktq ) use + gdr : igd == -1.0*iss + (gmin*vgd); + end use; + +end architecture behav; --- of pjfet; + +---- DC Voltage source + +use work.electricalsystem.all; + +entity DCVSrc is + generic (v : real := 10.0); -- voltage + port (terminal pos, neg : electrical); +end entity DCVSrc; + +architecture behav of DCVSrc is + terminal temp : electrical; + quantity vdc across idc through temp to neg; + quantity vtemp across itemp through pos to temp; + +begin + + VSrc : vdc == v; + temp_volt : vtemp == itemp * 1.0e-03; + +end architecture behav; --- of DCVSrc + + +------ pjfet amplifier circuit + +use std.textio.all; +use work.electricalsystem.all; + +entity pjfet_ckt is +end entity; + +architecture test of pjfet_ckt is + terminal t1, t2, t3, t4: electrical; +-- quantity vin across iin through ain to electrical'reference; +-- quantity vout across iout through t2 to electrical'reference; + quantity vb across ib through t1 to t2; +-- quantity ibt through t1 to t2; + quantity vrd1 across ird1 through t3 to t4; + quantity vdd across idd through t1 to electrical'reference; + quantity vss across iss through t4 to electrical'reference; + + + -- signal vds_sig, vgs_sig : real := 0.0; + + component pjfet_comp is + generic(T : real := 300.0; + vto : real := -2.0; -- Zero-bais threshold voltage + beta : real := 1.0e-4; -- transconductance parameter + lambda : real := 0.0; -- channel lenght modulation + af : real := 1.0; -- flicker noise exponent + kf : real := 0.0; -- flicker noise coefficient + iss : real := 1.0e-14; -- gate junction saturation current + pb : real := 1.0; -- gate junction potential + fc : real := 0.5; -- forward-bais depletion capacitance coeff + cgd : real := 4.0e-11; -- zero-bais gate-drain junction cap + cgs : real := 4.0e-11; -- zero-bias gate-source junction cap + rd : real := 1.0e-6; -- drain ohmic resistance + rs : real := 1.0e-6); -- source ohmic resistance + port (terminal g,s,d : electrical); + end component; + for all :pjfet_comp use entity work.pjfet(behav); + +begin + + jn1 : pjfet_comp + generic map(vto => -2.0, beta => 1.0e-3, lambda => 0.04) + port map(ground, t2, t3); + +-- brk : break on vgs_sig,vds_sig; +-- inp : vin == vgs_sig; +-- oup : vout == vds_sig; +-- oup : vout == iout * 1.0e8; +-- cap : icout == 1.0e-13 * vcout'dot; +-- capbrk : break vcout => 0.0; + rd1 : vrd1 == ird1 * 2.0e3; + src1 : vdd == 5.0; + src2 : vss == -5.0; + curr : ib == 1.0e-3; +-- curt : vb == ibt * 1.0e6; + +-- inputtestbench:PROCESS +-- FILE test_IN : text OPEN READ_MODE IS "pjfet_anal.in"; +-- VARIABLE linebuf : line; +-- VARIABLE xds, xgs : real := 0.0; +-- BEGIN + +-- WHILE(NOT(endfile(test_IN))) LOOP +-- readline(test_IN,linebuf); +-- read(linebuf,xgs); +-- read(linebuf,xds); +-- vgs_sig <= xgs; +-- vds_sig <= xds; +-- WAIT FOR 1 ns; +-- END LOOP; +-- WAIT; +-- END process; --- inputtestbench + +end architecture test; -- pjfet_ckt diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_models/cap_array.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_models/cap_array.ams new file mode 100644 index 000000000..6b88cf456 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_models/cap_array.ams @@ -0,0 +1,80 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: cap_array.ams,v 1.2 2003-08-05 15:14:24 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +-- A simple RC circuit but both R & C are in between +-- array terminals. + +PACKAGE electricalSystem IS + subtype voltage is real ; + subtype current is real ; + + NATURE electrical IS real ACROSS real THROUGH ground REFERENCE; + NATURE electrical_vector is array(natural range<>) of electrical ; + subnature el_vect4 is electrical_vector(1 to 2); + FUNCTION SIN(X : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalsystem.all; + +--entity declaration + +ENTITY RLC IS + +END RLC; + +--architecture declaration + +ARCHITECTURE behavior OF RLC IS + + + terminal n1: electrical; + terminal n2: el_vect4; + + quantity vr1 across ir1 through n1 to n2; + quantity vr2 across ir2 through n2; + quantity vs across n1 ; + constant r1 : REAL := 1000.0; + constant cap : REAL := 100.0e-9; + + +BEGIN + +res11 : vr1(1) == ir1(1) * r1; +res12 : vr1(2) == ir1(2) * r1; +cap11 : ir2(1) == vr2(1)'dot * cap; +cap12 : ir2(2) == cap * vr2(2)'dot; + +vsrc : vs == 5.0 * sin(2.0 * 3.1415 * 15.0 --sine source + * real(time'pos(now)) * 1.0e-13); + +END architecture behavior; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_models/res_array.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_models/res_array.ams new file mode 100644 index 000000000..480459015 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_models/res_array.ams @@ -0,0 +1,83 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: res_array.ams,v 1.2 2003-08-05 15:14:24 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +PACKAGE electricalSystem IS + subtype voltage is real ; + subtype current is real ; + + NATURE electrical IS voltage ACROSS current THROUGH Ground reference; + NATURE electrical_vector is array(natural range<>) of electrical ; + subnature el_vect4 is electrical_vector(1 to 4); + FUNCTION SIN(X : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalsystem.all; + +--entity declaration + +ENTITY RLC IS + +END RLC; + +--architecture declaration + +ARCHITECTURE behavior OF RLC IS + + + terminal n1 : electrical; + terminal n2: el_vect4; + + quantity vr1 across ir1 through n1 to n2; + quantity vr2 across ir2 through n2 ; + quantity vs across n1 ; + constant r1 : REAL := 20.0; + constant r2 : REAL := 10.0; + + +BEGIN + +-- this will no longer work +-- * should be overloaded to support such a statement. +--res1 : vr1 == ir1 * r1; +res11 : vr1(1) == ir1(1) * r1; +res12 : vr1(2) == ir1(2) * r1; +res13 : vr1(3) == ir1(3) * r1; +res14 : vr1(4) == ir1(4) * r1; +res21 : vr2(1) == ir2(1) * r2; +res22 : vr2(2) == ir2(2) * r2; +res23 : vr2(3) == ir2(3) * r2; +res24 : vr2(4) == ir2(4) * r2; +vsrc : vs == 5.0 * sin(2.0 * 3.1415 * 10.0 --sine source + * real(time'pos(now)) * 1.0e-9); + +END architecture behavior; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_models/res_index.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_models/res_index.ams new file mode 100644 index 000000000..aaff3aae6 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_models/res_index.ams @@ -0,0 +1,104 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: res_index.ams,v 1.2 2003-08-05 15:14:24 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +PACKAGE electricalSystem IS + subtype voltage is real ; + subtype current is real ; + + NATURE electrical IS voltage ACROSS current THROUGH Ground reference; + NATURE electrical_vector is array(natural range<>) of electrical ; + type real_vector is array(natural range<>) of voltage ; + subtype real_vec4 is real_vector(0 to 3); + subnature el_vect4 is electrical_vector(0 to 3); + FUNCTION SIN(X : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalsystem.all; + +--entity declaration + +ENTITY RLC IS + +END RLC; + +--architecture declaration + +ARCHITECTURE behavior OF RLC IS + + + terminal n1, n4 : electrical; + terminal n2 , n3: el_vect4; + + --quantity V across I through n1(0 to 2) to n1(1 to 3); + quantity V1 across I1 through n1 to n2; + quantity V2 across I2 through n2 to n3; + quantity V3 across I3 through n3 to n4; + quantity Vout across Iout through n4; + --quantity vs across n1(0) ; + quantity vs across n1 ; + constant r1 : REAL := 200.0; + constant r2 : REAL := 200.0; + constant r3 : REAL := 200.0; + constant r4 : REAL := 200.0; + + signal my_sig : real_vec4 ; + +BEGIN +-- the below statement parses but seems like 'delayed is not +-- there in VHDL. +--my_sig(2) <= my_sig(1)'delayed(5 ns) * 10.0; +--my_sig(3) <= my_sig(2) * 10.0; +-- the four statement are equivalent to +-- V == I * r1 ; +-- also the operator * should be overloaded + +--res0: V1 == I1 * r1; +--res1: V == I * r1; +--res1: V(0) == 5.0 ; +res1 : V1(0) == I1(0) * r1; +res2 : V1(1) == I1(1) * r1; +res3 : V1(2) == I1(2) * r1; +res4 : V1(3) == I1(3) * r1; +res11 : V2(0) == I2(0) * r1; +res21 : V2(1) == I2(1) * r1; +res31 : V2(2) == I2(2) * r1; +res41 : V2(3) == I2(3) * r1; +res111 : V3(0) == I3(0) * r1; +res211 : V3(1) == I3(1) * r1; +res311 : V3(2) == I3(2) * r1; +res411 : V3(3) == I3(3) * r1; +res641 : Vout == Iout * r1; +vsrc : vs == 5.0 * sin(2.0 * 3.1415 * 10.0 --sine source + * real(time'pos(now)) * 1.0e-9); + +END architecture behavior; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_tests/test107.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_tests/test107.ams new file mode 100644 index 000000000..1c9b85e58 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_tests/test107.ams @@ -0,0 +1,152 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test107.ams,v 1.1 2002-03-27 22:11:16 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test107.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks for the correct impelmentation of the port terminal +-- decl. signal decl. of type real, type array decl. +-- the test performs a 4 bit digital to analog conversion. +---------------------------------------------------------------------- + +PACKAGE electricalsystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; +END electricalsystem; + +USE work.electricalsystem.all; +ENTITY dac is + port(inputvector : in bit_vector(3 downto 0); --inputvector is an array of 16 bits + terminal T1, T2: electrical); --terminal declarations +END dac; + +ARCHITECTURE behavior OF dac IS + + type temp_array is array(0 to 3) of integer; -- temp to store the array values + quantity vout across T1 to T2; --output of the dac + + signal vout_sig, vcopy : real; +BEGIN + + dac_process: PROCESS(inputvector) + variable a : temp_array := (0,0,0,0); + variable tmp : real; + + BEGIN + for index in 3 downto 0 loop + if inputvector(index) = '0' then + a(index) := 0; --bit to integer conversion done here + else a(index) := 1; + end if; + end loop; + + tmp := real(a(3)*8) + real(a(2)*4) + real(a(1)*2 + a(0)); --find the corresponding value of the binary + vout_sig <= tmp; + + END PROCESS dac_process; + + -- digital to analog conversion is done here + vout == vcopy; + + convert: process(vout_sig) + begin + vcopy <= TRANSPORT vout_sig; + end process; + +END behavior; +use work.electricalsystem.all; +ENTITY tb_dac is +end tb_dac; + +architecture stimuli of tb_dac is + signal myinputvector : bit_vector(3 downto 0); + terminal tout : electrical; + component dac port( inputvector : in bit_vector(3 downto 0); + terminal T1, T2: electrical); + end component; + for all: dac use entity work.dac(behavior); + +BEGIN + + unit:dac port map (myinputvector, tout, electrical'reference); + + stimuli_process: process + BEGIN + + myinputvector <= "0000"; + wait for 10 ns; + + myinputvector <= "0001"; + wait for 10 ns; + + myinputvector <= "0010"; + wait for 10 ns; + + myinputvector <= "0100"; + wait for 10 ns; + + myinputvector <= "1000"; + wait for 10 ns; + + myinputvector <= "1100"; + wait for 10 ns; + + myinputvector <= "1110"; + wait for 10 ns; + + myinputvector <= "1101"; + wait for 10 ns; + + myinputvector <= "1111"; + wait for 10 ns; + myinputvector <= "0000"; + wait for 10 ns; + + myinputvector <= "1100"; + wait for 10 ns; + + myinputvector <= "1010"; + wait for 10 ns; + + wait; + end process; +end stimuli; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_tests/test129.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_tests/test129.ams new file mode 100644 index 000000000..d59b2de7e --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_tests/test129.ams @@ -0,0 +1,97 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test129.ams,v 1.2 2003-08-05 15:14:24 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +package electricalSystem is + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION POW(X,Y: real) RETURN real; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + nature electrical_vector is array(natural range<>) of electrical; + subnature el_vec is electrical_vector(0 to 3); +END PACKAGE electricalSystem; + +use work.electricalSystem.all; + +entity test is +generic( a: real); +port( terminal ip: el_vec; + terminal op:electrical); +end entity; + +architecture atest of test is +variable a:real:=5.0; +variable output:real:=0.0; +quantity vin across ip ; +quantity vout across iout through ip to op; +begin + + for i in 0 to 3 loop + output:=output + vin(i)*a; + end loop; +vout:=output; + +end architecture atest; + +use work.electricalSystem.all; +entity tb is +end entity; + +architecture atb of tb is +quantity myvector : el_vec(0 to 3); +terminal top:electrical; +component test + port(terminal ip, op: electrical); +end component; +for all: test use entity work.test(atest); +begin + +unit: test port map(tip, top, ground); + +a_process: process +begin + +myvector == 1.0; +wait for 10 ns; +myvector == 2.0; +wait for 10 ns; +myvector == 2.0; +wait for 10 ns; +myvector ==1.0; +wait for 10 ns; + +wait; + +end process; + +end atb; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_tests/test130.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_tests/test130.ams new file mode 100644 index 000000000..c92b11b4a --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_tests/test130.ams @@ -0,0 +1,70 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test130.ams,v 1.1 2002-03-27 22:11:16 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +package electricalSystem is + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION POW(X,Y: real) RETURN real; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + nature electrical_vector is array(natural range<>) of electrical; + subnature el_vec is electrical_vector(0 to 3); +END PACKAGE electricalSystem; + +use work.electricalSystem.all; + +entity test is +generic( a: real); +port( terminal ip: el_vec; + terminal op:electrical); +end entity; + +architecture atest of test is +variable a:real:=5.0; +variable output:real:=0.0; +quantity vin0 across ip(0) to op; +quantity vin1 across ip(1) to op; +quantity vin2 across ip(2) to op; +quantity vin3 across ip(3) to op; +quantity vout across iout through op; + +begin + +e1: vin0 == 5.0* sin(2.0*3.14*10.0*real(time'pos(now))*1.0e-9); +e2: vin1 == 5.0* sin(2.0*3.14*10.0*real(time'pos(now))*1.0e-9); +e3: vin2 == 5.0* sin(2.0*3.14*10.0*real(time'pos(now))*1.0e-9); +e4: vin3 == 5.0* sin(2.0*3.14*10.0*real(time'pos(now))*1.0e-9); + +vout == (vin0+vin1+vin2+vin3)*a; + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_tests/test139.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_tests/test139.ams new file mode 100644 index 000000000..8d813451c --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_tests/test139.ams @@ -0,0 +1,123 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test139.ams,v 1.1 2002-03-27 22:11:16 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +----------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +----------------------------------------------------------------------- +-- File : test139.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +----------------------------------------------------------------------- +-- Description : +----------------------------------------------------------------------- +-- this test checks the correctness of the record declaration as a type +-- it also checks for the usage of the record element declarations. +-- the assert statement is also checked. +-- the record is declared within a package +-- the test also checks the correctness of the function impelmentation. +-- the function accepts the record parameters and returns the result of +-- type real. +----------------------------------------------------------------------- + +PACKAGE electricalsystem IS + + SUBTYPE voltage IS real; + SUBTYPE current IS real; + + NATURE electrical IS + voltage ACROSS + current THROUGH ground reference; + +END PACKAGE electricalsystem; + +PACKAGE types IS + + TYPE cmodel IS RECORD + cj : real; + cjsw : real; + defw : real; + narrow : real; + END RECORD; + +END PACKAGE types; + +USE work.electricalsystem.all; +USE work.types.all; + +ENTITY test IS + GENERIC (cnom : real := 0.0; + model : cmodel := (0.0, 0.0, 1.0e-6, 0.0); + l : real := 0.0; + w : real := 0.0; + ic : real := 0.0 ); + PORT (TERMINAL t1,t2 : electrical); +END ENTITY test; + +ARCHITECTURE atest OF test IS + FUNCTION c_init ( cnom : real; + model : cmodel; + l, w : real) + RETURN real IS + VARIABLE ceff : real; -- effective capacitance value + VARIABLE weff : real; -- effective channel width + BEGIN + + IF cnom /= 0.0 THEN + ASSERT (model.cj = 0.0 AND model.cjsw = 0.0) + REPORT "Both cnom and model specified"; + ceff := cnom; + ELSE + ASSERT (l > 0.0) + REPORT "Channel length not specified"; + IF w = 0.0 THEN + weff := model.defw; + ELSE + weff := w; + END IF; + ASSERT (weff > 0.0) + REPORT "Channel width not specified"; + ceff := model.cj*(l-model.narrow)*(weff-model.narrow) + + model.cjsw*(l+weff-2.0*model.narrow); + END IF; + RETURN (ceff); + END FUNCTION c_init; + + CONSTANT ceff : real := c_init(cnom, model, l, w); + QUANTITY v ACROSS i THROUGH t1 TO t2; +BEGIN + i == ceff * v'dot; +END ARCHITECTURE atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_tests/test186.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_tests/test186.ams new file mode 100644 index 000000000..fd22b2a7d --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_tests/test186.ams @@ -0,0 +1,76 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test186.ams,v 1.2 2003-08-05 15:14:24 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +PACKAGE electricalSystem IS + subtype voltage is real ; + subtype current is real ; + + NATURE electrical IS voltage ACROSS current THROUGH Ground reference; + --NATURE electrical IS real ACROSS real THROUGH Ground reference; + NATURE electrical_vector is array(natural range<>) of electrical ; + --type real_vector is array(natural range<>) of voltage ; + subnature el_vec is electrical_vector(0 to 100); + FUNCTION SIN(X : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalsystem.all; + +--entity declaration + +ENTITY RLC IS + +END RLC; + +--architecture declaration + +ARCHITECTURE behavior OF RLC IS + + + terminal n1 : electrical; + terminal n2: el_vec; + + quantity vr1 across ir1 through n1 to n2; + quantity vr2 across ir2 through n2 to ground; + quantity vs across n1 ; + constant r1 : REAL := 20.0; + constant r2 : REAL := 10.0; + + +BEGIN + +res1 : vr1 == ir1 * r1; +res2 : vr2 == ir2 * r2; +vsrc : vs == 5.0 * sin(2.0 * 3.1415 * 10.0 --sine source + * real(time'pos(now)) * 1.0e-9); + +END architecture behavior; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/attribute/across.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/attribute/across.ams new file mode 100644 index 000000000..be1ba8419 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/attribute/across.ams @@ -0,0 +1,72 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: across.ams,v 1.2 2003-08-05 15:14:24 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH Ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalsystem.all; + +--entity declaration + +ENTITY RLC IS + +END RLC; + +--architecture declaration + +ARCHITECTURE behavior OF RLC IS + + terminal n1,n2: electrical; + constant r1 : real := 10.0; + constant r2 : real := 20.0; + constant r3 : real := 20.0; + quantity vr1 across ir1 through n1 to n2; + quantity vr2 across ir2 through Ground; + quantity vr3 across ir3 through n2; + quantity vs across n1 to ground; + quantity contrib: electrical'across; +BEGIN + +v1: vr1 == ir1 *r1; +v2: vr2 == ir2 *r2; +v3: vr3 == ir3 *r3; +fr: contrib == n1'contribution; +vsrc : vs == 5.0 * sin(2.0 * 3.1415 * 10.0 --sine source + * real(time'pos(now)) * 1.0e-9); + +END architecture behavior; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/attribute/step_limit.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/attribute/step_limit.ams new file mode 100644 index 000000000..71f416e3a --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/attribute/step_limit.ams @@ -0,0 +1,65 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: step_limit.ams,v 1.2 2003-08-05 15:14:24 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH Ground reference; + FUNCTION SIN (X : real ) RETURN real; + FUNCTION COS (X : real ) RETURN real; + FUNCTION EXP (X : real ) RETURN real; +END PACKAGE electricalSystem; + +USE work.electricalSystem.all; + +--entity declaration +ENTITY hwr IS +END hwr; + +--architecture declaration +ARCHITECTURE behavior OF hwr IS + + terminal t1, t2 : electrical; + constant step : real := 5.0e12; + quantity v2 across i2 through t1 ; + quantity vs across t1 ; + limit vs:real with step/1000.0; + quantity vikram:real; + limit v2,vs:real with 2.0e9; +BEGIN -- behavior + + eqn1: v2 == 100.0 * i2; + + --voltage source equation + eqn2: vs == 5.0 * sin(2.0 * 3.14 * 100000.0 * + real(time'pos(now)) * 1.0e-12 ); + +END behavior ; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/attribute/through.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/attribute/through.ams new file mode 100644 index 000000000..305b7daf3 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/attribute/through.ams @@ -0,0 +1,72 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: through.ams,v 1.2 2003-08-05 15:14:24 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH Ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalsystem.all; + +--entity declaration + +ENTITY RLC IS + +END RLC; + +--architecture declaration + +ARCHITECTURE behavior OF RLC IS + + terminal n1,n2: electrical; + constant r1 : real := 10.0; + constant r2 : real := 20.0; + constant r3 : real := 20.0; + quantity vr1 across ir1 through n1 to n2; + quantity vr2 across ir2 through ground; + quantity vr3 across ir3 through n2; + quantity vs across n1 to ground; + quantity contrib: electrical'through; +BEGIN + +v1: vr1 == ir1 *r1; +v2: vr2 == ir2 *r2; +v3: vr3 == ir3 *r3; +fr: contrib == n1'reference; +vsrc : vs == 5.0 * sin(2.0 * 3.1415 * 10.0 --sine source + * real(time'pos(now)) * 1.0e-9); + +END architecture behavior; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/attribute/tick_contribution.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/attribute/tick_contribution.ams new file mode 100644 index 000000000..b82427e08 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/attribute/tick_contribution.ams @@ -0,0 +1,72 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: tick_contribution.ams,v 1.1 2002-03-27 22:11:17 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH Ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalsystem.all; + +--entity declaration + +ENTITY RLC IS + +END RLC; + +--architecture declaration + +ARCHITECTURE behavior OF RLC IS + + terminal n1,n2: electrical; + constant r1 : real := 10.0; + constant r2 : real := 20.0; + constant r3 : real := 20.0; + quantity vr1 across ir1 through n1 to n2; + quantity vr2 across ir2 through n2; + quantity vr3 across ir3 through n2; + quantity vs across n1; + quantity contrib:real; +BEGIN + +v1: vr1 == ir1 *r1; +v2: vr2 == ir2 *r2; +v3: vr3 == ir3 *r3; +fr: contrib == n2'contribution; +vsrc : vs == 5.0 * sin(2.0 * 3.1415 * 10.0 --sine source + * real(time'pos(now)) * 1.0e-9); + +END architecture behavior; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/attribute/tick_left.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/attribute/tick_left.ams new file mode 100644 index 000000000..bb2cf7d52 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/attribute/tick_left.ams @@ -0,0 +1,80 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: tick_left.ams,v 1.2 2003-08-05 15:14:24 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +-- A simple RC circuit but both R & C are in between array terminals. +-- trying to use 'left, 'right, 'low, 'high attributes. + +PACKAGE electricalSystem IS + subtype voltage is real ; + subtype current is real ; + + NATURE electrical IS real ACROSS real THROUGH ground REFERENCE; + NATURE electrical_vector is array(natural range<>) of electrical ; + subnature el_vect4 is electrical_vector(1 to 2); + + FUNCTION SIN(X : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalsystem.all; + +--entity declaration + +ENTITY RLC IS + +END RLC; + +--architecture declaration + +ARCHITECTURE behavior OF RLC IS + + + terminal n1: electrical; + terminal n2: el_vect4; + + quantity vr1 across ir1 through n1 to n2; + quantity vr2 across ir2 through n2 to Ground; + quantity vs across n1 ; + constant r1 : REAL := 1000.0; + constant cap : REAL := 100.0e-9; + +BEGIN + +res11 : vr1(n2'left) == ir1(n2'left) * r1; +res12 : vr1(el_vect4'right) == ir1(el_vect4'right) * r1; +cap11 : ir2(el_vect4'low) == vr2(1)'dot * cap; +cap12 : ir2(el_vect4'high) == cap * vr2(2)'dot; + +vsrc : vs == 5.0 * sin(2.0 * 3.1415 * 15.0 --sine source + * real(time'pos(now)) * 1.0e-13); + +END architecture behavior; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/attribute/tick_reference.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/attribute/tick_reference.ams new file mode 100644 index 000000000..563ddddbd --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/attribute/tick_reference.ams @@ -0,0 +1,67 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: tick_reference.ams,v 1.1 2002-03-27 22:11:17 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH Ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalsystem.all; + +--entity declaration + +ENTITY RLC IS + +END RLC; + +--architecture declaration + +ARCHITECTURE behavior OF RLC IS + + terminal n1,n2: electrical; + constant r1 : real := 10.0; + constant r2 : real := 20.0; + quantity ir1 through n1 to n2; + quantity vr2 across ir2 through n2; + quantity vs across n1; +BEGIN + +i1 : ir1 == (n1'reference - n2'reference)/ r1 ; +v1 : vr2 == ir2*r2; +vsrc : vs == 5.0 * sin(2.0 * 3.1415 * 10.0 --sine source + * real(time'pos(now)) * 1.0e-9); + +END architecture behavior; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/bouncing_ball.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/bouncing_ball.ams new file mode 100644 index 000000000..b646742fc --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/bouncing_ball.ams @@ -0,0 +1,55 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: bouncing_ball.ams,v 1.1 2002-03-27 22:11:17 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +ENTITY bouncing_ball IS +END ENTITY bouncing_ball; + +ARCHITECTURE simple OF bouncing_ball IS + + QUANTITY v: real; + QUANTITY s: real; + CONSTANT G: real := 9.81; + + CONSTANT Air_Res: real := 0.1; + +BEGIN + + b1:BREAK v => 0.0, s => 30.0; -- announce discontinuity and reset + + b2:BREAK v => -0.7*v WHEN NOT(s'above(0.0)); + + velocity: v == s'dot ; + + acceleration: v'dot == -G; + +END ARCHITECTURE simple; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/lorenz_chaos.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/lorenz_chaos.ams new file mode 100644 index 000000000..97b3bcc57 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/lorenz_chaos.ams @@ -0,0 +1,56 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: lorenz_chaos.ams,v 1.1 2002-03-27 22:11:17 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +entity LorenzChaos is +end entity LorenzChaos; + +architecture Chaotic of LorenzChaos is + + constant s: real := 10.0; -- define equation parameters s,b,r + constant b: real := 8.0/3.0; + constant r: real := 28.0; + quantity x: real; + quantity y: real; + quantity z: real; + +begin + -- set an initial condition to guarantee chaotic behaviour: + br:break x=> y , y => 5.0, z => 25.0; + br1:break when y'above(25.0); + + -- equation set: + eq1:x == y-(x'dot/s); + eq2:y == r*x-x*z-y'dot; + eq3:z == (x*y -z'dot)/b; + +end architecture Chaotic; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/precharged_capacitor.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/precharged_capacitor.ams new file mode 100644 index 000000000..d62c63a3e --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/precharged_capacitor.ams @@ -0,0 +1,67 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: precharged_capacitor.ams,v 1.1 2002-03-27 22:11:17 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +-- This is a model of discharging of a precharged capacitor +-- Break statement has been used here to set the initial +-- value of the voltage to which the capacotor was charged +-- authors: Shishir Agrawal +-- Vikram +-- Sanjiv Pandey + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH Ground REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalsystem.all; + +ENTITY RC IS +END; + +ARCHITECTURE behav OF RC IS + TERMINAL n1,n2: ELECTRICAL; + QUANTITY v_in ACROSS i_in THROUGH n1; + QUANTITY u_r ACROSS i_r THROUGH n1 TO n2; + QUANTITY u_c ACROSS i_c THROUGH n2; +BEGIN + + + b1: BREAK u_c => 0.5; --initvalue + + e1: v_in == 0.0; --constant voltage source + e2: i_r == u_r / 1000.0; --resistor equation + e3: i_c == 1.0e-6 * u_c'dot; --capacitor equation +END; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test123.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test123.ams new file mode 100644 index 000000000..9d3e53e7b --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test123.ams @@ -0,0 +1,82 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test123.ams,v 1.1 2002-03-27 22:11:17 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test113.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- to check the correct implementation of the simultaneous if statement +-- break and 'above is also used. it checks for the eqns v'=g*v**2 for +-- +g and -g. +---------------------------------------------------------------------- +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH; + FUNCTION SIN(X : real) RETURN real; +-- alias ground is electrical'reference; +END PACKAGE electricalSystem; + +use work.electricalsystem.all; + +entity test is +end entity test; + +architecture atest of test is +quantity v : real; +quantity s: real; +constant g : real :=9.81; +constant r : real:=1.02; + +begin + +break v=>0.0, s=>100.0; + +break v=>-v when not s'above(0.0); + +s'dot==v; + +if v>0.0 use + v'dot == -g+v*v*r; +else + v'dot == -g-v*v*r; +end use; + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test133.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test133.ams new file mode 100644 index 000000000..e97d77b03 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test133.ams @@ -0,0 +1,78 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test133.ams,v 1.1 2002-03-27 22:11:17 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test133.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- + +--this test checks the correctness of the break statement for a +-- quantity port declaration. +-- LRM ref: 8.14 +---------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + subtype voltage is real; + +END PACKAGE electricalSystem; + +use work.electricalSystem.all; + +entity test is + generic (m: real := 1.0); + port (quantity x: out voltage); +end entity test; + +architecture atest of test is +--quantity x: real; +quantity q: real; +begin + break x => 0.0, x'dot => 0.1; + e1: q== x'dot; + x'dot'dot == -1.0*( m*(x*x - 1.0)* x'dot); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test134.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test134.ams new file mode 100644 index 000000000..0f80d28c0 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test134.ams @@ -0,0 +1,98 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test134.ams,v 1.1 2002-03-27 22:11:17 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test151.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- this is a test to check the corretness of the implemntation of the break +-- statement and also the use of quantity port of type voltage. +-- this is a vco model which first sets the initial condition +-- using a break statement. Then again, a break statement is applied to keep +-- the phase within 0-2pi. Thr output voltage eqn is obtained as vout and the +-- phase eqn as phase'dot. +-- LRM ref: 8.14, 4.3.2. +--------------------------------------------------------------------------------- +PACKAGE electricalSystem IS + SUBTYPE voltage is real; + NATURE electrical IS real ACROSS real THROUGH; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; + +entity vco is + generic( + fc: real := 1.0e6; -- VCO frequency at Vc + df: real := 0.5e6; -- [Hz/V], frequency characteristic slope + Vc: voltage := 0.0 -- centre frequency input voltage + ); + port( quantity Vin: in voltage; + terminal OutTerminal: electrical); +end entity VCO; + +architecture avco of vco is + constant TwoPi: real := 6.283118530718; -- 2pi + + quantity Phase : real; + + -- define a branch for the output voltage source + + quantity Vout across Iout through OutTerminal to electrical'reference; + +begin + -- use break to set the phase initial condition + break Phase => 0.0; + + -- another break statement keeps the phase within 0.. 2pi + break Phase => Phase mod TwoPi on Phase'above(TwoPi); + + -- phase equation + Phase'dot == TwoPi*realmax(0.5E6, fc+(Vin-Vc)*df); + + -- output voltage source equation + Vout == 2.5*(1.0+sin(Phase)); + +end architecture avco; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test158.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test158.ams new file mode 100644 index 000000000..f96b6f476 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test158.ams @@ -0,0 +1,98 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test158.ams,v 1.1 2002-03-27 22:11:17 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test134.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : June 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- this is a test to check the corretness of the implemntation of the break +-- statement and also the use of quantity port of type voltage. +-- this is a vco model which first sets the initial condition +-- using a break statement. Then again, a break statement is applied to keep +-- the phase within 0-2pi. Thr output voltage eqn is obtained as vout and the +-- phase eqn as phase'dot. +-- LRM ref: 8.14, 4.3.2. +---------------------------------------------------------------------- +PACKAGE electricalSystem IS + -- SUBTYPE voltage is real; + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; + +entity vco is + generic( + fc: real := 1.0e6; -- VCO frequency at Vc + df: real := 0.5e6; -- [Hz/V], frequency characteristic slope + Vc: voltage := 0.0 -- centre frequency input voltage + ); + port( quantity Vin: in real; + terminal OutTerminal: electrical); +end entity VCO; + +architecture avco of vco is + constant TwoPi: real := 6.283118530718; -- 2pi + + quantity Phase : real; + + -- define a branch for the output voltage source + + quantity Vout across Iout through OutTerminal to electrical'reference; + +begin + -- use break to set the phase initial condition + break Phase => 0.0; + + -- another break statement keeps the phase within 0.. 2pi + break Phase => Phase mod TwoPi on Phase'above(TwoPi); + + -- phase equation + Phase'dot == TwoPi*realmax(0.5E6, fc+(Vin-Vc)*df); + + -- output voltage source equation + Vout == 2.5*(1.0+sin(Phase)); + +end architecture avco; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test180.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test180.ams new file mode 100644 index 000000000..3e33069e4 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test180.ams @@ -0,0 +1,74 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test180.ams,v 1.1 2002-03-27 22:11:17 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test180.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test is done for checking the correct implementation +-- of the break statement.it checks simple break and break on +-- codition. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH; -- GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +entity VCO is + port(terminal InTerminal,OutTerminal: electrical); +end VCO; + +architecture PhaseIntegrator of VCO is + + quantity Vin across Iin through InTerminal to OutTerminal; + constant TwoPi: real := 6.283118530718; -- 2pi + quantity Phase : real; -- phase is a free quantity: + quantity Vout across Iout through OutTerminal; + +begin + + break Phase => TwoPi; + Vout == 2.5*(sin(Phase)); -- output statement + +end PhaseIntegrator; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test181.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test181.ams new file mode 100644 index 000000000..4c7caf467 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test181.ams @@ -0,0 +1,73 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test181.ams,v 1.1 2002-03-27 22:11:17 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test181.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test is done for checking the correct implementation +-- of the break statement.it checks simple break and break on +-- codition. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH; -- GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity VCO is + port(terminal InTerminal,OutTerminal: electrical); +end VCO; + +architecture PhaseIntegrator of VCO is + quantity Vin across Iin through InTerminal to OutTerminal; + constant TwoPi: real := 6.283118530718; -- 2pi + quantity Phase : real; -- phase is a free quantity: + quantity Vout across Iout through OutTerminal; +begin + break Phase => TwoPi; + -- break allows to define the initial conditions + break Phase => 0.0 on Phase'above(TwoPi); + Vout == 2.5*(sin(Phase)); -- output statement +end PhaseIntegrator; + diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/torsional_oscillator.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/torsional_oscillator.ams new file mode 100644 index 000000000..084f90c99 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/torsional_oscillator.ams @@ -0,0 +1,52 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: torsional_oscillator.ams,v 1.1 2002-03-27 22:11:17 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +--Torsional oscillator +ENTITY bouncer IS +END ENTITY bouncer; + +ARCHITECTURE simple OF bouncer IS + CONSTANT m1 : REAL := 0.0; + CONSTANT md : REAL := 0.0; + CONSTANT mc : REAL := 1.0; + QUANTITY om : REAL; + QUANTITY ph : REAL; + +BEGIN + --Initvalues + BREAK om => 0.0, ph => 0.0; + + (om'dot) == 10000.0*(1.0 - 1000.0 * ph); + (ph'dot) == om; + +END ARCHITECTURE simple; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/free_equations/2nd_order_ode.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/free_equations/2nd_order_ode.ams new file mode 100644 index 000000000..88b5c9aae --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/free_equations/2nd_order_ode.ams @@ -0,0 +1,47 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: 2nd_order_ode.ams,v 1.1 2002-03-27 22:11:17 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +entity VanDerPol is + generic (m: real := 1.0); +end entity VanDerPol; + +architecture SecondOrderODE of VanDerPol is +quantity x:real; +begin + -- the break statement sets the initial conditions + break x => 0.0, x'dot => 0.1; + + -- second-order Van Der Pol ODE + x'dot'dot == -x -m*(x*x - 1.0)*x'dot; +end architecture SecondOrderODE; + diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/free_equations/test1.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/free_equations/test1.ams new file mode 100644 index 000000000..ec8962376 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/free_equations/test1.ams @@ -0,0 +1,81 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test1.ams,v 1.1 2002-03-27 22:11:17 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH Ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalsystem.all; + +--entity declaration + +ENTITY RLC IS + +END RLC; + +--architecture declaration + +ARCHITECTURE behavior OF RLC IS + +-- terminal n1,n2,n3: electrical; + +-- quantity vl1 across il1 through n1 ; +-- quantity vl2 across il2 through n2 ; +-- quantity vl3 across il3 through n2 ; + +-- quantity vs across n1 ; + + quantity x:real; + quantity y:real; + quantity z:real; + +-- constant l : REAL := 0.01; + +BEGIN + +--r1 : vl1 == il1'dot * l; +--r2 : vl2 == il2'dot * l; +--r3 : vl3 == il3'dot * l; + +e1 : x == (16.00 - (6.00 * y)) / 4.00; +e2 : y == (5.00 - x)/2.00; +e3 : z == x+y; + +--eqn4:vs == 5.0 * sin(2.0 * 3.1415 * 10.0 --sine source +-- * real(time'pos(now)) * 1.0e-15); + +END architecture behavior; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/free_equations/test2.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/free_equations/test2.ams new file mode 100644 index 000000000..40e1a6e16 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/free_equations/test2.ams @@ -0,0 +1,72 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test2.ams,v 1.1 2002-03-27 22:11:17 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH Ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION TAN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalsystem.all; + +--entity declaration + +ENTITY RLC IS + +END RLC; + +--architecture declaration + +ARCHITECTURE behavior OF RLC IS + + quantity qfree:real:=0.0; + quantity qdot : real ; + quantity comp : real ; +BEGIN + +e1 : qdot == qfree'dot; + + +e2:qfree == 5.0 * sin(2.0 * 3.1415 * 10.0 --sine source + * real(time'pos(now)) * 1.0e-15); + +e3 : if (qfree <= 0.0) use + comp == -1.00; + else + comp == 1.00; + end use; + +END architecture behavior; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/above_attr.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/above_attr.ams new file mode 100644 index 000000000..c3bf7abd0 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/above_attr.ams @@ -0,0 +1,98 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: above_attr.ams,v 1.1 2002-03-27 22:11:17 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + -- NATURE electrical IS real ACROSS real THROUGH; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + + --ALIAS GND is electrical'reference; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +use std.textio.all; +entity test is +end entity; + +architecture atest of test is + constant R1: real :=10.0; + constant R2: real :=5.0; + terminal T1,T2:electrical; + quantity V1 across I1 through T1 to T2; + quantity V2 across I2 through T2; + quantity VS across T1; + quantity rt:real; + signal ABSIG,o:boolean; + --signal y:bit; + +begin + + +ABSIG<=V1'above(V2+1.0); + + testbench:PROCESS + VARIABLE outline : LINE; + VARIABLE Headline : string(1 TO 33) := + "time ABSIG"; + VARIABLE seperator : string(1 TO 1) := " "; + VARIABLE flag : bit := '0'; + VARIABLE tmp:bit; + FILE outfile: text OPEN WRITE_MODE IS "above_attr.out"; + BEGIN + IF (flag = '0') THEN + flag := '1'; + WRITE(outline,Headline); + WRITELINE(outfile,outline); + ELSE + WRITE(outline, now); + WRITE(outline,seperator); + IF (ABSIG = true) THEN + tmp:='1'; + ELSE + tmp:='0'; + WRITE(outline,tmp); + END IF; + WRITE(outline,seperator); + writeline(outfile,outline); + END IF; + WAIT ON ABSIG; + END PROCESS; + +e1: V1 == I1*R1; +e2: V2 == I2*R2; +esource: VS == 5.0 * sin(2.0 * 3.141592 *100.0 * real(time'pos(now))*1.0e-15); + +END ARCHITECTURE atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/am_modulation.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/am_modulation.ams new file mode 100644 index 000000000..cd49b93c7 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/am_modulation.ams @@ -0,0 +1,135 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: am_modulation.ams,v 1.1 2002-03-27 22:11:17 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +--Package defining eleectrical nature and some functions... +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; + +USE work.electricalSystem.ALL; +---------------------------------------------------------------------- +-- The sinusoidal voltage source definition begins..... +---------------------------------------------------------------------- +-- Schematic of the sinusoidal voltage source: +-- ------------------------------------------- +-- +-- p o----(~)----o m a sinusoidal voltage of amplitude ampl +-- Vs and frequency 'freq'. +---------------------------------------------------------------------- + +--entity declaration. +ENTITY sineSource IS + generic (ampl,freq : REAL); + PORT(TERMINAL p,m: ELECTRICAL); --Interface ports. +END; + +--architecture declaration. +ARCHITECTURE behav OF sineSource IS + --quantity declarations. + quantity v_in across i_out through p to m; +BEGIN + -- The sinusoidal voltage source equation. + v_in==ampl * sin (2.0*3.14* freq * real(time'pos(now)) * 1.0e-15); --input sinusoidal source +END; + +USE work.electricalSystem.ALL; +---------------------------------------------------------------------- +-- The resistor definition begins..... +---------------------------------------------------------------------- +-- Schematic of the resistor component: +-- +-- p o----/\/\/\----o m +-- +---------------------------------------------------------------------- + +ENTITY resistor IS + GENERIC (resistance : REAL); --resistance value given as a generic parameter. + + PORT (TERMINAL p,m : ELECTRICAL); --Interface ports. +END resistor; + +ARCHITECTURE behav OF resistor IS + quantity r_e across r_i through p to m; +BEGIN + r_i == r_e/resistance; -- The ohmic resistance equation. +END behav; +---------------------------------------------------------------- + + +USE work.electricalSystem.ALL; +----------------------------------------------------------------- +--testbench +-- ============================================================== +-- n1 R2 1k n2 +-- o __________________/\/\/\__________________o +-- | | | | +-- | T1 | | | +-- | < < | +-- (~)modulation < R1 < R3 (~) basiswave +-- | 100(sinwt) < 1k < 1k | 320(sinwt) +-- | | | | +-- | | | | +-- o___________________________________________o +-- | gnd +-- ----- + +ENTITY network IS +END; + +ARCHITECTURE behav OF network IS +component sineSource IS + generic (ampl,freq : REAL); + PORT(TERMINAL p,m: ELECTRICAL); --Interface ports. +END component; + +component resistor IS + GENERIC (resistance : REAL); --resistance value given as a generic parameter. + + PORT (TERMINAL p,m : ELECTRICAL); --Interface ports. +END component; + + terminal n1,n2: ELECTRICAL; +BEGIN + Modulation : sineSource generic MAP(100.0,5000.0) PORT MAP(n1,ground); + + R1 : Resistor generic MAP(1000.0) PORT MAP(n1,ground); + + Groundwave : sineSource generic MAP(320.0,500.0) PORT MAP(n2,ground); + + R3 : Resistor generic MAP(1000.0) PORT MAP (n2,ground); + + R2 : Resistor generic MAP(1000.0) PORT MAP (n1, n2); + +END; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/generic_model.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/generic_model.ams new file mode 100644 index 000000000..eb636b540 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/generic_model.ams @@ -0,0 +1,145 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: generic_model.ams,v 1.1 2002-03-27 22:11:17 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +-- trying to check both ports and generics. +-- resistor component below has both port and generic. +-- same example as in mixed_mode_1 with ports +-- simulate for 2e10 +-- end comments by shishir. + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use std.textio.all ; + +entity NOT_GATE is + generic ( delay : TIME := 100 ns ) ; + port ( + C : in bit; + Cbar : out bit); + +end NOT_GATE; + +architecture dataflow of NOT_GATE is + --signal my : bit := '0'; +begin -- dataflow + + Cbar <= not C after delay ; + +end dataflow ; + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND reference; + FUNCTION SIN (X : real ) RETURN real; + FUNCTION EXP (X : real ) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +use std.textio.all; + +entity resistor is + generic ( resvalue : real := 100.0 ) ; + port (terminal P, N : electrical ); +end resistor; + +architecture behav of resistor is + quantity VPTON across IPTON through P to N; +begin + res1 : VPTON == IPTON * resvalue ; +end behav; + +use work.electricalSystem.all; +use std.textio.all; + +ENTITY circuit1 IS +END circuit1; + +ARCHITECTURE behavior OF circuit1 IS + component NOT_GATE is + generic ( delay : TIME := 100 ns) ; + port ( + C : in bit; + Cbar : out bit); + end component ; + for all : NOT_GATE use entity work.NOT_GATE(dataflow) ; + + component resistor is + generic ( resvalue : real := 100.0 ) ; + port (terminal P, N : electrical ); + end component; + for all : resistor use entity work.resistor(behav); + + terminal n1,n2 : electrical; + QUANTITY vIn ACROSS iIn THROUGH n1 ; + --QUANTITY vr1 ACROSS ir1 THROUGH n1 to n2; + --QUANTITY vr2 ACROSS ir2 THROUGH n2 ; + + signal y:bit:='0'; + +BEGIN + +-- digital component instantiation. + D2 : NOT_GATE generic map ( delay => 1000 ns) port map(C=>y, Cbar=>y); + + testbench:PROCESS + VARIABLE outline : LINE; + VARIABLE Headline : string(1 TO 8) := + "time y "; + VARIABLE seperator : string(1 TO 1) := " "; + VARIABLE flag : bit := '0'; + FILE outfile: text OPEN WRITE_MODE IS "generic_model.out"; + BEGIN + IF (flag = '0') THEN + flag := '1'; + WRITE(outline,Headline); + WRITELINE(outfile,outline); + ELSE + WRITE(outline, now); + WRITE(outline,seperator); + WRITE(outline,y); + WRITE(outline,seperator); + writeline(outfile,outline); + END IF; + WAIT ON y; + END PROCESS; + +-- analog component instantiation. +-- for some strange reason if i put it above the process, it does not work. + + R1 : resistor generic map ( resvalue => 500.0) port map (P => n1, N => n2); + --R1 : resistor port map (P => n1, N => n2); + R2 : resistor port map (P => n2, N => ground); +-- R1 : vr1 == ir1 * 100.0 ; + -- R2 : vr2 == ir2 * 100.0 ; + vsource: vIn == 5.0 * sin(2.0 * 3.14 * 100000.0 * real(time'pos(now)) * 1.0e-15); + +END ARCHITECTURE behavior; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/iofiles/above_attr.out b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/iofiles/above_attr.out new file mode 100644 index 000000000..34d04f6aa --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/iofiles/above_attr.out @@ -0,0 +1,21 @@ +time ABSIGtestbenchwork_Dte +1098543.277411 NS +4034001.034625 NS 0 +11029402.988035 NS +14000633.820645 NS 0 +21180065.574642 NS +24074961.958137 NS 0 +31051068.654154 NS +34010938.898262 NS 0 +41184808.429215 NS +44077392.700384 NS 0 +51052348.254524 NS +54011554.141123 NS 0 +61185092.495303 NS +64077540.337822 NS 0 +71052427.799030 NS +74011594.434932 NS 0 +81185113.202536 NS +84077552.980693 NS 0 +91052436.416308 NS +94011600.731912 NS 0 diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/iofiles/generic_model.out b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/iofiles/generic_model.out new file mode 100644 index 000000000..5e1e1424b --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/iofiles/generic_model.out @@ -0,0 +1,21 @@ +time y +1000 NS 1 +2000 NS 0 +3000 NS 1 +4000 NS 0 +5000 NS 1 +6000 NS 0 +7000 NS 1 +8000 NS 0 +9000 NS 1 +10000 NS 0 +11000 NS 1 +12000 NS 0 +13000 NS 1 +14000 NS 0 +15000 NS 1 +16000 NS 0 +17000 NS 1 +18000 NS 0 +19000 NS 1 +20000 NS 0 diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/iofiles/mixed_model_1.out b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/iofiles/mixed_model_1.out new file mode 100644 index 000000000..5530249a8 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/iofiles/mixed_model_1.out @@ -0,0 +1,21 @@ +time y +1000 NS 1 +2000 NS 0 +3000 NS 1 +4000 NS 0 +5000 NS 1 +6000 NS 0 +7000 NS 1 +8000 NS 0 +9000 NS 1 +10000 NS 0 +11000 NS 1 +12000 NS 0 +13000 NS 1 +14000 NS 0 +15000 NS 1 +16000 NS 0 +17000 NS 1 +18000 NS 0 +19000 NS 1 +20000 NS 0 diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/iofiles/mixed_model_2.out b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/iofiles/mixed_model_2.out new file mode 100644 index 000000000..5530249a8 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/iofiles/mixed_model_2.out @@ -0,0 +1,21 @@ +time y +1000 NS 1 +2000 NS 0 +3000 NS 1 +4000 NS 0 +5000 NS 1 +6000 NS 0 +7000 NS 1 +8000 NS 0 +9000 NS 1 +10000 NS 0 +11000 NS 1 +12000 NS 0 +13000 NS 1 +14000 NS 0 +15000 NS 1 +16000 NS 0 +17000 NS 1 +18000 NS 0 +19000 NS 1 +20000 NS 0 diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/mesh.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/mesh.ams new file mode 100644 index 000000000..f0e4f12be --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/mesh.ams @@ -0,0 +1,143 @@ + +-- Copyright (C) 1998-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: mesh.ams,v 1.1 2002-03-27 22:11:17 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +-- /**************************************************************************/ +-- /* File: mesh.ams */ +-- /**************************************************************************/ +-- /* Author: Venkateswaran Krishna */ +-- /* Date of creation: Dec 1 1998 */ +-- /* Last changed by: Venkateswaran Krishna */ +-- /**************************************************************************/ +-- Roadmap +---------- +--While it might look like a trivial circuit this model actually +--managed to find a breach in seams!! Specifically with the code +--generation of generics... so it is important to have it as part +--of the test suite. The model is a small mesh ckt with 3 resistors +--and 2 voltage sources.. simple nodal soln of the mesh is all that +--seams has to do +-- +-- +-- t1 1 t2 3 t3 +-- o---/\/\/\---o---/\/\/\---o +-- | | | +-- | < | +-- ( )5v <2 ( )10v +-- | < | +-- | | | +-- o------------o------------o +-- | +-- _| +-- \/ + +--package definition +PACKAGE electricalSystem IS + + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN (X : real ) RETURN real; + FUNCTION EXP (X : real ) RETURN real; + +END PACKAGE electricalSystem; + +use work.electricalSystem.all; + +entity resistor is + generic(r: real := 10000.0 ); --- resistance + port( terminal tr1,tr2 : electrical); --- interface ports +end resistor; + +architecture rbehavior of resistor is + quantity Vr across Ir through tr1 to tr2; +begin + Vr == Ir*r; +end architecture rbehavior; --- of resisitor + + +use work.electricalSystem.all; +ENTITY constVSource IS + GENERIC (voltage : real := 10.0); + PORT (TERMINAL ta4, tb4 : electrical ); +END constVSource; + +ARCHITECTURE behavioral OF constVSource IS + quantity vsource across isource through ta4 TO tb4; +BEGIN -- behavior + constSource_equation: vsource == voltage; +END behavioral; + + +use work.electricalSystem.all; + +entity mesh is +end mesh; + +architecture struc of mesh is + + terminal t1, t2, t3 : electrical; + + component resComp + generic(r: real := 10000.0 ); --- resistance + port( terminal tr1,tr2 : electrical); --- interface ports + end component; + + for all : rescomp use entity work.resistor(rbehavior); + + component source + GENERIC (voltage : real := 10.0); + PORT (TERMINAL ta4, tb4 : electrical ); + END component; + + for all : source use entity work.constVSource(behavioral); + +begin + + voltage_source1: source + generic map(5.0) + port map(t1, ground); + + voltage_source2: source + port map(t3, ground); + + r1: resComp + generic map(1.0) + port map(t1, t2); + + r2: resComp + generic map(2.0) + port map(t2, ground); + + r3: resComp + generic map(3.0) + port map(t2, t3); + +end; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/mixed_model_1.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/mixed_model_1.ams new file mode 100644 index 000000000..10fd3bbeb --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/mixed_model_1.ams @@ -0,0 +1,86 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: mixed_model_1.ams,v 1.1 2002-03-27 22:11:17 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +-- an example of a model having both a signal assignment statement +-- as well as a simple simultaneous statement. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND reference; + FUNCTION SIN (X : real ) RETURN real; + FUNCTION EXP (X : real ) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +use std.textio.all; +ENTITY circuit1 IS +END circuit1; + +ARCHITECTURE behavior OF circuit1 IS + CONSTANT resistance1 : real := 100.0; -- value of R1 + terminal n1 : electrical; + QUANTITY vIn ACROSS n1; + QUANTITY vR ACROSS iR THROUGH n1 ; + signal y:bit:='0'; +BEGIN + +process(y) +begin + y <= not(y) after 1000 ns; + +end process; + + testbench:PROCESS + VARIABLE outline : LINE; + VARIABLE Headline : string(1 TO 8) := + "time y"; + VARIABLE seperator : string(1 TO 1) := " "; + VARIABLE flag : bit := '0'; + FILE outfile: text OPEN WRITE_MODE IS "mixed_model_1.out"; + BEGIN + IF (flag = '0') THEN + flag := '1'; + WRITE(outline,Headline); + WRITELINE(outfile,outline); + ELSE + WRITE(outline, now); + WRITE(outline,seperator); + WRITE(outline,y); + WRITE(outline,seperator); + writeline(outfile,outline); + END IF; + WAIT ON y; + END PROCESS; + res_stmt1: vR == iR * resistance1 ; + vsource: vIn == 5.0 * sin(2.0 * 3.14 * 100000.0 * real(time'pos(now)) * 1.0e-15); + +END ARCHITECTURE behavior; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/mixed_model_2.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/mixed_model_2.ams new file mode 100644 index 000000000..dd80c233e --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/mixed_model_2.ams @@ -0,0 +1,143 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: mixed_model_2.ams,v 1.1 2002-03-27 22:11:17 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +-- This is a model that has both a signal assignment statement as well as a +-- simple simultaneous statement. So supposedly uses both digital and +-- analog kernel but does not have any interaction between digital and +-- analog portion. Also there is a port declaration to check whether +-- addition of code for terminals in ports has not affected the digital +-- part. same example as in mixed_mode_1 with ports simulate for 2e10 end +-- comments by shishir. + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use std.textio.all ; + +entity NOT_GATE is + + port ( + C : in bit; + Cbar : out bit); + +end NOT_GATE; + +architecture dataflow of NOT_GATE is + +begin -- dataflow + + Cbar <= not C after 1000 ns; + +end dataflow ; + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND reference; + FUNCTION SIN (X : real ) RETURN real; + FUNCTION EXP (X : real ) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +use std.textio.all; + +entity resistor is + port (terminal P, N : electrical ); +end resistor; + +architecture behav of resistor is + quantity VPTON across IPTON through P to N; +begin + res1 : VPTON == IPTON * 100.0 ; +end behav; + +use work.electricalSystem.all; +use std.textio.all; + +ENTITY circuit1 IS +END circuit1; + +ARCHITECTURE behavior OF circuit1 IS + component NOT_GATE is + port ( + C : in bit; + Cbar : out bit); + end component ; + for all : NOT_GATE use entity work.NOT_GATE(dataflow) ; + + component resistor is + port (terminal P, N : electrical ); + end component; + for all : resistor use entity work.resistor(behav); + + terminal n1,n2 : electrical; + QUANTITY vIn ACROSS iIn THROUGH n1 ; + QUANTITY vr1 ACROSS ir1 THROUGH n1 to n2; + QUANTITY vr2 ACROSS ir2 THROUGH n2 ; + + signal y:bit:='0'; + +BEGIN + +-- digital component instantiation. + D2 : NOT_GATE port map(C=>y, Cbar=>y); + + testbench:PROCESS + VARIABLE outline : LINE; + VARIABLE Headline : string(1 TO 8) := + "time y"; + VARIABLE seperator : string(1 TO 1) := " "; + VARIABLE flag : bit := '0'; + FILE outfile: text OPEN WRITE_MODE IS "mixed_model_2.out"; + BEGIN + IF (flag = '0') THEN + flag := '1'; + WRITE(outline,Headline); + WRITELINE(outfile,outline); + ELSE + WRITE(outline, now); + WRITE(outline,seperator); + WRITE(outline,y); + WRITE(outline,seperator); + writeline(outfile,outline); + END IF; + WAIT ON y; + END PROCESS; + +-- analog component instantiation. +-- for some strange reason if i put it above the process, it does not work. + + R1 : resistor port map (P => n1, N => n2); + R2 : resistor port map (P => n2, N => ground); +-- R1 : vr1 == ir1 * 100.0 ; + -- R2 : vr2 == ir2 * 100.0 ; + vsource: vIn == 5.0 * sin(2.0 * 3.14 * 100000.0 * real(time'pos(now)) * 1.0e-15); + +END ARCHITECTURE behavior; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/multiple_res_comp.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/multiple_res_comp.ams new file mode 100644 index 000000000..c09cd0fbb --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/multiple_res_comp.ams @@ -0,0 +1,96 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: multiple_res_comp.ams,v 1.1 2002-03-27 22:11:17 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +package electricalSystem is + NATURE electrical IS real ACROSS real THROUGH Ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalsystem.all; + +entity bad_resistor is + port (terminal P, N : electrical ); +end bad_resistor; + +architecture behav of bad_resistor is + quantity VPTON across IPTON through P to N; +begin + res1 : VPTON == IPTON * 100.0 ; +end behav; + +use work.electricalsystem.all; +entity good_resistor is + port (terminal P, N : electrical ); +end good_resistor; + +architecture behav of good_resistor is + quantity VP across IP through P to N; +begin + res1 : VP == IP * 1000.0 ; +end behav; + + +use work.electricalsystem.all; + +entity resistor_ckt is +end resistor_ckt; + +architecture structure of resistor_ckt is + + component bad_resistor is + port (terminal P, N : electrical ); + end component; + + component good_resistor is + port (terminal P, N : electrical ); + end component; + + for all : good_resistor use entity work.good_resistor(behav); + for all : bad_resistor use entity work.bad_resistor(behav); + + terminal X,Y,Z,t1,t2 : electrical; + quantity vout across iout through t2 to electrical'reference; + quantity vs across X to electrical'reference; + +begin + R1 : bad_resistor port map (P => X, N => Y); + R2 : bad_resistor port map (P => Y, N => Z); + R3 : vout == iout * 1200.0; + R4 : good_resistor port map (P => Z, N => t1); + R5 : good_resistor port map (P => t1, N => t2); + vsrc : vs == 5.0 * sin(2.0 * 3.1415 * 10.0 --sine source + * real(time'pos(now)) * 1.0e-9); +end structure; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/parallel-plate.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/parallel-plate.ams new file mode 100644 index 000000000..5ceeaf0db --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/parallel-plate.ams @@ -0,0 +1,117 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: parallel-plate.ams,v 1.1 2002-03-27 22:11:17 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +-- This model was tested and compared with SPICE. +-- The results match with SPICE +-- The model implements a simple parallel place cap with just +-- one top and one bottom plate. +-- simulation time 2e11. +-- Initially proposed by Dr. Carter. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN (X : real ) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +entity plate is + generic ( + cell_resistance : real := 1000.0 + ); + + port ( + terminal up, down, left, right, top : electrical + ); +end entity plate; + +architecture behav of plate is + +quantity Vup across Iup through up to top ; +quantity Vdown across Idown through down to top ; +quantity Vleft across Ileft through left to top ; +quantity Vright across Iright through right to top ; + +begin + + Rup : Vup == Iup * cell_resistance ; + Rdown : Vdown == Idown * cell_resistance ; + Rleft : Vleft == Ileft * cell_resistance ; + Rright : Vright == Iright * cell_resistance ; +end behav ; + + +use work.electricalSystem.all; + +entity parallel_plate_cap is +end entity; + +architecture struc of parallel_plate_cap is + component plate is + generic ( + cell_resistance : real := 1000.0 + ); + port ( + terminal up, down, left, right, top : electrical + ); + end component ; + for all : plate use entity work.plate(behav); + + terminal up1, up2, down1, down2, left1, left2, right1, right2, top1, top2 : electrical ; + + quantity vcap across icap through top1 to top2 ; + quantity vrgnd across irgnd through top2 ; + quantity vs1 across left1 to left2; + quantity vs2 across right1 to right2; + quantity vs3 across up1 to up2; + quantity vs4 across down1 to down2; + + constant cell_cap : real := 1.0e-6; + +begin + plate1 : plate port map ( up1, down1, left1, right1, top1) ; + plate2 : plate port map ( up2, down2, left2, right2, top2) ; + --plate2 : plate port map ( up2, down2, left2, right2, ground) ; + + capeqn : icap == cell_cap * vcap'dot; + -- there should be some ground + resgnd : vrgnd == irgnd * 1000.0 ; + vsrc1 : vs1 == 5.0 * sin(2.0 * 3.1415 * 10.0e3 --sine source + * real(time'pos(now)) * 1.0e-15); + vsrc2 : vs2 == 5.0 * sin(2.0 * 3.1415 * 10.0e3 --sine source + * real(time'pos(now)) * 1.0e-15); + vsrc3 : vs3 == 5.0 * sin(2.0 * 3.1415 * 10.0e3 --sine source + * real(time'pos(now)) * 1.0e-15); + vsrc4 : vs4 == 5.0 * sin(2.0 * 3.1415 * 10.0e3 --sine source + * real(time'pos(now)) * 1.0e-15); + +end struc ; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/parallel-plates4.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/parallel-plates4.ams new file mode 100644 index 000000000..a4ebbe219 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/parallel-plates4.ams @@ -0,0 +1,161 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: parallel-plates4.ams,v 1.1 2002-03-27 22:11:17 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +-- This model was tested and compared with SPICE. +-- The results match with SPICE +-- The model implements a simple parallel plate cap with just +-- one top and one bottom plate. +-- The top and bottom plates have been divided into 4 sub plates. +-- Actually its like 4 parallel-plate subsections have been connected +-- to form the capacitor. +-- simulation time 2e11. +-- Initially proposed by Dr. Carter. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN (X : real ) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +entity plate is + generic ( + cell_resistance : real := 1000.0 + ); + + port ( + terminal up, down, left, right, top : electrical + ); +end entity plate; + +architecture behav of plate is + +quantity Vup across Iup through up to top ; +quantity Vdown across Idown through down to top ; +quantity Vleft across Ileft through left to top ; +quantity Vright across Iright through right to top ; + +begin + + Rup : Vup == Iup * cell_resistance ; + Rdown : Vdown == Idown * cell_resistance ; + Rleft : Vleft == Ileft * cell_resistance ; + Rright : Vright == Iright * cell_resistance ; +end behav ; + + +use work.electricalSystem.all; + +entity parallel_plate_cap is + port ( + terminal up1, up2, down1, down2, left1, left2, right1, right2, top1, top2: electrical + ); +end entity; + +architecture struc of parallel_plate_cap is + component plate is + generic ( + cell_resistance : real := 1000.0 + ); + port ( + terminal up, down, left, right, top : electrical + ); + end component ; + for all : plate use entity work.plate(behav); + + -- this need not be in the port list but i am adding it + -- to observe vcap uniquely. + --terminal top1, top2 : electrical ; + quantity vcap across icap through top1 to top2 ; + quantity vrgnd across irgnd through top2 ; +-- quantity vs1 across left1 to left2; +-- quantity vs2 across right1 to right2; +-- quantity vs3 across up1 to up2; +-- quantity vs4 across down1 to down2; + + constant cell_cap : real := 1.0e-8; + +begin + plate1 : plate port map ( up1, down1, left1, right1, top1) ; + plate2 : plate port map ( up2, down2, left2, right2, top2) ; + --plate2 : plate port map ( up2, down2, left2, right2, ground) ; + + capeqn : icap == cell_cap * vcap'dot; + -- there should be some ground + resgnd : vrgnd == irgnd * 1000.0 ; +-- vsrc1 : vs1 == 5.0 * sin(2.0 * 3.1415 * 10.0e3 --sine source + -- * real(time'pos(now)) * 1.0e-15); + -- vsrc2 : vs2 == 5.0 * sin(2.0 * 3.1415 * 10.0e3 --sine source + -- * real(time'pos(now)) * 1.0e-15); + -- vsrc3 : vs3 == 5.0 * sin(2.0 * 3.1415 * 10.0e3 --sine source + -- * real(time'pos(now)) * 1.0e-15); + -- vsrc4 : vs4 == 5.0 * sin(2.0 * 3.1415 * 10.0e3 --sine source + -- * real(time'pos(now)) * 1.0e-15); + +end struc ; + +use work.electricalSystem.all; + +entity real_cap is +end entity ; + +architecture struct of real_cap is + component parallel_plate_cap is + port ( + terminal up1, up2, down1, down2, left1, left2, right1, right2, top1, top2: electrical + ); + end component ; + + for all : parallel_plate_cap use entity work.parallel_plate_cap(struc); + + terminal u1, u2, u3 , u4, d1, d2, d3, d4, l1, l2 , r1, r2, r3, r4 , t1, t2, t3, t4: electrical ; + terminal d11, d21, d31, d41, l11, l21 , r11, r21, r31, r41 , t11, t21, t31, t41: electrical ; + -- not needed. + --terminal l3 , l4 : electrical ; + + quantity vs across l1 to l2 ; + quantity vs1 across l11 to l21 ; + + +begin + + p1 : parallel_plate_cap port map (u1, u2, d1, d2, l1, l2, r1, r2, t1, t2); + p2 : parallel_plate_cap port map (u3, u4, d3, d4, r1, r2, r3, r4, t3, t4); + p3 : parallel_plate_cap port map (d1, d2, d11, d21, l11, l21, r11, r21, t11, t21); + p4 : parallel_plate_cap port map (d3, d4, d31, d41, r11, r21, r31, r41, t31, t41); + + vsrc : vs == 5.0 * sin(2.0 * 3.1415 * 10.0e3 --sine source + * real(time'pos(now)) * 1.0e-15); + vsrc1 : vs1 == 5.0 * sin(2.0 * 3.1415 * 10.0e3 --sine source + * real(time'pos(now)) * 1.0e-15); + +end ; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/res_component.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/res_component.ams new file mode 100644 index 000000000..32f876221 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/res_component.ams @@ -0,0 +1,79 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: res_component.ams,v 1.1 2002-03-27 22:11:17 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +package electricalSystem is + NATURE electrical IS real ACROSS real THROUGH Ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalsystem.all; + +entity resistor is + port (terminal P, N : electrical ); +end resistor; + +architecture behav of resistor is + quantity VPTON across IPTON through P to N; +begin + res1 : VPTON == IPTON * 100.0 ; +end behav; + + +use work.electricalsystem.all; + +entity resistor_ckt is +end resistor_ckt; + +architecture structure of resistor_ckt is + + component resistor is + port (terminal P, N : electrical ); + end component; + for all : resistor use entity work.resistor(behav); + terminal X,Y,Z,t1,t2 : electrical; + quantity vout across iout through t2 to electrical'reference; + quantity vs across X to electrical'reference; + +begin + R1 : resistor port map (P => X, N => Y); + R2 : resistor port map (P => Y, N => Z); + --R3 : vout == iout * 200.0; + R3 : resistor port map (P => t2, N => ground); + R4 : resistor port map (P => Z, N => t1); + R5 : resistor port map (P => t1, N => t2); + vsrc : vs == 5.0 * sin(2.0 * 3.1415 * 10.0 --sine source + * real(time'pos(now)) * 1.0e-9); +end structure; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/inverter_model/inverter.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/inverter_model/inverter.ams new file mode 100644 index 000000000..ae9e5be1d --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/inverter_model/inverter.ams @@ -0,0 +1,431 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: inverter.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +-- /**************************************************************************/ +-- /* File: inverter.ams */ +-- /**************************************************************************/ +-- /* Author(s): Vishwashanth Kasula Reddy & Venkateswaran Krishna */ +-- /* Date of creation: Mon Nov 30th 1998 */ +-- /**************************************************************************/ +--Roadmap: +---------- +--This is a mixed signal model of an inverter... The input is a bit signal +-- which is converted to a 5/0 value realSignal. This signal is then given +-- to the input of the cmos inverter and the output of the cmos inverter is +-- then given to a atod... the final output is then a bit signal which is +-- the inverse of the input bit signal... + +------------------------------------------------------------------------ +-- /\ Vdd +-- | +-- o S +-- | +-- -- +-- -----<-|p +-- | -- +-- | | +-- --0--/\/\--0 D 0--------o--------o---------- +-- + /\ | | | | /\ + +-- | | -- > | | +-- vin is | ----->-|n < --- Vout ==> atod ==> op +-- atod(inp) Vin -- > --- | +-- | | < | | +-- | o S | | | +-- - \/ | | | \/ - +-- ------------------------------------------------- +-- | +-- --- +-- - +------------------------------------------------------------------------ + +-------***************************************************************** +-- Package definition Begins +-------***************************************************************** + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +-- ALIAS GND is electrical'reference; +END PACKAGE electricalSystem; + +------- Square wave generator + +-------***************************************************************** +-- New Entity Begins : 1 BIT A/D CONVERTER +-------***************************************************************** + +use work.electricalsystem.all; + +entity a2d1bit is + generic (vlo : real := 0.0; + vhi : real := 10.0; + ped : time := 1 ns); + port (signal input : in bit; + terminal pos, neg : electrical); +end entity a2d1bit; + +architecture behav of a2d1bit is + quantity vsqr across isqr through pos to neg; + signal vsig : real := 0.0; +begin + + vsqr == vsig; + break on vsig; + + bit2real : process + begin + if(input = '0') then + vsig <= vlo; + else + vsig <= vhi; + end if; + wait on input; + end process; --- generator; + +end architecture behav; + +-------***************************************************************** +-- New Entity Begins : RESISTOR +-------***************************************************************** +use work.electricalSystem.all; + +entity resistor is + generic(r: real := 1.0 ); --- resistance + port( terminal tr1,tr2 : electrical); --- interface ports +end resistor; + +architecture rbehavior of resistor is + quantity Vr across Ir through tr1 to tr2; +begin + Vr == Ir*r; +end architecture rbehavior; --- of resistor + +-------***************************************************************** +-- New Entity Begins : PMOS TRANSISTOR +-------***************************************************************** + +----- PMOS +--use std.textio.all; +use work.electricalsystem.all; + +entity pmos is + port (terminal g,s,d : electrical); +end entity pmos; + +architecture behav of pmos is + terminal g2, d1 : electrical; + quantity vdsg across idsgi through d1 to s; + quantity idsg through d1 to s; + quantity vdsr across idsr through d1 to d; + quantity vds across d to s; + quantity vgs_in across g to s; + quantity vgsr across igsr through g to g2; + quantity vgs across igs through g2 to s; + constant vth : real := 0.5; + constant hfe : real := 3.54e-03; +-- quantity flag : real := 1.0; +-- quantity vgs : real; +-- signal vgs_sig,vds_sig : real := 0.0; + +begin + ------ Setting initial conditions +-- init : break vds => 1.0; + + opn : vdsg == 1.0e+06 * idsgi ; -- almost + d12_res : vdsr == idsr * 1.0; + g12res : vgsr == igsr * 1.0; + g_oup : vgs == igs * 1.0; + +-- flag == 1.0; + +---- Current is in Micro Amps. + + ------ Cut OffRegion + if((vgs <= 0.0) and (vgs >= vth)) use + gnc : idsg == 0.0; + + ------ Linear Region + elsif((vds >= (vgs-vth)) and (vds < 0.0)) use + gnl : idsg == -1.0*hfe*(((vgs-vth)*vds) - (pow(vds,2.0)/2.0)); + + ------ Saturation Region + elsif((vds < (vgs-vth)) and (vgs < vth)) use + gns2 : idsg == -1.0*(hfe/2.0)*(pow((vgs-vth),2.0)); + + ------ Other conditions + -- elsif(vgs < 0.0 or vds <= 0.0) use + elsif(1.0 = 1.0) use + temp : idsg == 0.0; + end use; + +end architecture behav; --- of pmos; + + +-------***************************************************************** +-- New Entity Begins : NMOS TRANSISTOR +-------***************************************************************** + +----- NMOS +--use std.textio.all; +use work.electricalsystem.all; + +entity nmos is + port (terminal g,s,d : electrical); +end entity nmos; + +architecture behav of nmos is + terminal g2, d1 : electrical; + quantity vdsg across idsgi through d1 to s; + quantity idsg through d1 to s; + quantity vdsr across idsr through d1 to d; + quantity vds across d to s; + quantity vgs_in across g to s; + quantity vgsr across igsr through g to g2; + quantity vgs across igs through g2 to s; + constant vth : real := 0.5; + constant hfe : real := 8.85e-03; +-- quantity flag : real := 1.0; +-- quantity vgs : real; +-- signal vgs_sig,vds_sig : real := 0.0; + +begin + ------ Setting initial conditions +-- init : break vds => 1.0; + + opn : vdsg == 1.0* idsgi ; -- almost + d12_res : vdsr == idsr * 1.0e-3; + g12res : vgsr == igsr * 1.0; + g_oup : vgs == igs * 1.0; + +-- flag == 1.0; + +---- Current is in Micro Amps. + + ------ Cut OffRegion + if((vgs >= 0.0) and (vgs <= vth)) use + gnc : idsg == 0.0; + + ------ Linear Region + elsif((vds <= (vgs-vth)) and (vds > 0.0)) use + gnl : idsg == hfe*(((vgs-vth)*vds) - (pow(vds,2.0)/2.0)); + + ------ Saturation Region + elsif((vds > (vgs-vth)) and (vgs > vth)) use + gns2 : idsg == (hfe/2.0)*(pow((vgs-vth),2.0)); + + ------ Other conditions + -- elsif(vgs < 0.0 or vds <= 0.0) use + elsif(1.0 = 1.0) use + temp : idsg == 0.0; + end use; + +end architecture behav; --- of nmos; + +--------- Inverter Test Bench + +-------***************************************************************** +-- New Entity Begins : CMOS INVERTER +-------***************************************************************** + +use work.electricalsystem.all; + +entity inverter is + port(inv_inp : in bit; + inv_op : out bit); +end entity inverter; + +architecture behav of inverter is + + terminal iin, iout, idd : electrical; + quantity vdd across idd to electrical'reference; + quantity vin across iin to electrical'reference; + quantity vout across irout through iout to electrical'reference; + + constant power : real := 5.0; + + component nmos is + port (terminal g,s,d : electrical); + end component; + for all : nmos use entity work.nmos(behav); + + component pmos is + port (terminal g,s,d : electrical); + end component; + for all : pmos use entity work.pmos(behav); + + component a2d_comp is + generic(vlo : real := 0.0; + vhi : real := 10.0; + ped : time := 1 ns); + port (signal input : in bit; + terminal pos, neg : electrical); + end component; + for all : a2d_comp use entity work.a2d1bit(behav); + + component resistor_comp + generic ( r : real := 1.0); + port ( terminal tr1, tr2 : electrical ); + end component; + for all : resistor_comp use entity work.resistor(rbehavior); + +begin + + vdd == power; + + sqr : a2d_comp + generic map(0.0, 10.0, 500 ps) + port map(inv_inp, iin, electrical'reference); + + nm : nmos port map(iin, electrical'reference, iout); + pm : pmos port map(iin, idd, iout); + + res_out : resistor_comp + generic map(5000000.0) + port map(iout,electrical'reference); + + a2d: process + begin + if(vout'above(0.003) = true) then + inv_op <= '1'; + else + inv_op <= '0'; + end if; + end process; + +end architecture behav; ---- of inverter + +-------***************************************************************** +-- New Entity Begins : TESTBENCH +-------***************************************************************** + +use std.textio.all; + +entity test_bench is +end test_bench; + +architecture tb_arch of test_bench is + +component inverter_comp + port(inv_inp : in bit; + inv_op : out bit); +end component; + +for all : inverter_comp use entity work.inverter(behav); + +signal ip, op : bit; + +begin + + i1 : inverter_comp + port map(ip, op); + + inputtestbench:PROCESS + begin + ip <= '0'; + wait for 100 NS; + ip <= '1'; + wait for 100 NS; + ip <= '0'; + wait for 100 NS; + ip <= '1'; + wait for 100 NS; + ip <= '0'; + wait for 100 NS; + ip <= '1'; + wait for 100 NS; + ip <= '0'; + wait for 100 NS; + ip <= '1'; + wait for 100 NS; + ip <= '0'; + wait for 100 NS; + ip <= '1'; + wait for 100 NS; + ip <= '0'; + wait for 100 NS; + ip <= '1'; + wait for 100 NS; + ip <= '0'; + wait for 100 NS; + ip <= '1'; + wait for 100 NS; + ip <= '0'; + wait for 100 NS; + ip <= '1'; + wait for 100 NS; + ip <= '0'; + wait for 100 NS; + ip <= '1'; + wait for 100 NS; + ip <= '0'; + wait for 100 NS; + ip <= '1'; + wait for 100 NS; + ip <= '0'; + wait for 100 NS; + ip <= '1'; + wait for 100 NS; + ip <= '0'; + wait for 100 NS; + ip <= '1'; + wait for 100 NS; + + END process; + + testbench:PROCESS + VARIABLE outline : LINE; + VARIABLE Headline : string(1 TO 54) := + "time inv_input inv_output"; + VARIABLE seperator : string(1 TO 1) := " "; + VARIABLE flag : bit := '0'; + FILE outfile: text OPEN WRITE_MODE IS "Output.out"; + BEGIN + IF (flag = '0') THEN + flag := '1'; + WRITE(outline,Headline); + WRITELINE(outfile,outline); + ELSE + WRITE(outline, now); + WRITE(outline,seperator); + WRITE(outline,ip); + WRITE(outline,seperator); + WRITE(outline,op); + WRITELINE(outfile,outline); + END IF; + WAIT ON ip, op; + END PROCESS; + +end; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/mixed_tests/iofiles/mixed_1.out b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/mixed_tests/iofiles/mixed_1.out new file mode 100644 index 000000000..58c2c98a2 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/mixed_tests/iofiles/mixed_1.out @@ -0,0 +1,6 @@ +time ytestbenchwork_Drlc_Dbehavior_state::locateSi +300 NS 1 +600 NS 0 +900 NS 1 +1200 NS 0 +1500 NS 1 diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/mixed_tests/iofiles/mixed_2.out b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/mixed_tests/iofiles/mixed_2.out new file mode 100644 index 000000000..2968583af --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/mixed_tests/iofiles/mixed_2.out @@ -0,0 +1,8 @@ +time y xtestbenchwork_Drlc_Dbehavior_state:: +30 NS 1 0 +50 NS 1 1 +60 NS 0 1 +90 NS 1 1 +100 NS 1 0 +120 NS 0 0 +150 NS 1 1 diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/mixed_tests/mixed_1.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/mixed_tests/mixed_1.ams new file mode 100644 index 000000000..37cd1280c --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/mixed_tests/mixed_1.ams @@ -0,0 +1,105 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: mixed_1.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +--This model basically consists of an analog and a single digital process +--and this tests the simulators capability of synchronization between the +--analog and the digital model +--Partha + + PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH Ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalsystem.all; +USE std.textio.ALL; +--entity declaration + +ENTITY RLC IS + +END RLC; + +--architecture declaration + +ARCHITECTURE behavior OF RLC IS + + + terminal n1, n2, n3 : electrical; + + quantity vr1 across ir1 through n1 to n2; + quantity vr2 across ir2 through n2 to n3; + quantity vr3 across ir3 through n3; + quantity vs across n1; + constant r1 : REAL := 10.0; + constant r2 : REAL := 20.0; + constant r3 : REAL := 50.0; + signal y:bit := '0'; + +BEGIN + + process(y) + begin + y <= not(y) after 300 ns; + end process; + +testbench:PROCESS(y) + VARIABLE outline : LINE; + VARIABLE Headline : string(1 TO 52) := + "time y"; + VARIABLE seperator : string(1 TO 1) := " "; + VARIABLE flag : bit := '0'; + FILE outfile: text OPEN WRITE_MODE IS "mixed_1.out"; + BEGIN + IF (flag = '0') THEN + flag := '1'; + WRITE(outline,Headline); + WRITELINE(outfile,outline); + ELSE + WRITE(outline, now); + WRITE(outline,seperator); + WRITE(outline, y); + WRITE(outline, seperator); + WRITELINE(outfile,outline); + END IF; + END PROCESS; + +res1 : vr1 == ir1 * r1; +res2 : vr2 == ir2 * r2; +res3 : vr3 == ir3 * r3; +vsrc : vs == 5.0 * sin(2.0 * 3.1415 * 10.0 --sine source + * real(time'pos(now)) * 1.0e-9); + +END architecture behavior; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/mixed_tests/mixed_2.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/mixed_tests/mixed_2.ams new file mode 100644 index 000000000..c78005790 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/mixed_tests/mixed_2.ams @@ -0,0 +1,106 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: mixed_2.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH Ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalsystem.all; +USE std.textio.ALL; +--entity declaration + +ENTITY RLC IS + +END RLC; + +--architecture declaration + +ARCHITECTURE behavior OF RLC IS + + terminal n1, n2, n3 : electrical; + + quantity vr1 across ir1 through n1 to n2; + quantity vr2 across ir2 through n2 to n3; + quantity vr3 across ir3 through n3; + quantity vs across n1; + constant r1 : REAL := 10.0; + constant r2 : REAL := 20.0; + constant r3 : REAL := 50.0; + signal y,x:bit := '0'; + +BEGIN + + process(y) + begin + y <= not(y) after 30 ns; + end process; + + process(x) + begin + x <= not(x) after 50 ns; + end process; + +testbench:PROCESS(y,x) + VARIABLE outline : LINE; + VARIABLE Headline : string(1 TO 52) := + "time y x"; + VARIABLE seperator : string(1 TO 1) := " "; + VARIABLE flag : bit := '0'; + FILE outfile: text OPEN WRITE_MODE IS "mixed_2.out"; + BEGIN + IF (flag = '0') THEN + flag := '1'; + WRITE(outline,Headline); + WRITELINE(outfile,outline); + ELSE + WRITE(outline, now); + WRITE(outline,seperator); + WRITE(outline, y); + WRITE(outline, seperator); + WRITE(outline, x); + WRITE(outline, seperator); + WRITELINE(outfile,outline); + END IF; + END PROCESS; + +res1 : vr1 == ir1 * r1; +res2 : vr2 == ir2 * r2; +res3 : vr3 == ir3 * r3; +vsrc : vs == 5.0 * sin(2.0 * 3.1415 * 10.0 --sine source + * real(time'pos(now)) * 1.0e-9); + +END architecture behavior; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test100.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test100.ams new file mode 100644 index 000000000..a3d35b4e0 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test100.ams @@ -0,0 +1,77 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test100.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test100.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple resistor model... +-- the test is done for checking the correct implementation +--of the simple simultaneous equation statement.it checks +--nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity V1 across I1 through T1 to T2; +quantity V2 across I2 through T2; +quantity V3 across I3 through T2; +quantity VS across T1; + +begin + +e1: V1 == I1*100.0; +e2: V2 == I2*10.0; +e3: V3 == I3*10.0; + +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test101.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test101.ams new file mode 100644 index 000000000..64a81a499 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test101.ams @@ -0,0 +1,76 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test101.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test101.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- this test checks teh correctness of the 'integ implementation. +-- it finds the integral of teh source voltage. +-- the input is a sine wave. +--------------------------------------------------------------------- +PACKAGE electricalSystem IS + + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +entity test is +end entity test; + +architecture atest of test is + + quantity vs : real; + quantity vout: real; + +begin + + vs== 5.0 * sin(2.0 * 3.1415 * 10.0 * real(time'pos(now)) * + 1.0e-15); + vout == vs'integ; + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test102.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test102.ams new file mode 100644 index 000000000..430b9b47b --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test102.ams @@ -0,0 +1,82 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test102.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test102.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks the correctness of the Q'integ usage on the RHS of +-- the simple simultaneous eqn. +-------------------------------------------------------------------- +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + + --ALIAS GND is electrical'reference; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +entity tank is +end tank; + +architecture atank of tank is + + terminal t1,t2 : electrical; + + constant r: real :=10.00; + constant c: real:=0.00000003; + + quantity vin across t1 to electrical'reference; + quantity vr across ir through t1 to t2; + quantity vc across ic through t2 to electrical'reference; + quantity q : real; + +begin + vr == ir*r; + q==c*vc; + ic==q'integ; + vin == 5.0 * sin(2.0 * 3.1415 * 10.0 * real(time'pos(now)) * + 1.0e-15); +end atank; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test103.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test103.ams new file mode 100644 index 000000000..880ea33d8 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test103.ams @@ -0,0 +1,85 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test103.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test103.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks the correctness of the simple simultaneous eqn. +-- implementation. This is also a test for the lexical analysis. +-------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUD REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +entity test is +end entity; + +architecture atest of test is + + terminal T1,T2,T3,T4,T5:electrical; + quantity v1 across i1 through T1 to T2; + quantity v2 across i2 through T2 to T4; + quantity v3 across i3 through T4 to T3; + quantity v4 across i4 through T2 to T5; + quantity v5 across i5 through T5 to T3; + quantity v6 across i6 through T2 to T3; + quantity vS across T1 to electrical'reference; + +begin + +e1: v1==i1*1.0; +e2: v2==i2*1.0; +e3: v3==i3*1.0; +e4: v4==i4*1.0; +e5: v5==i5*1.0; +e6: v6==i6*1.0; +es: vS==5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test104.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test104.ams new file mode 100644 index 000000000..d23ea0335 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test104.ams @@ -0,0 +1,91 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test104.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test104.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- this is a test that checks for the correct implementation of if use +--end use. The condition is checked by comparing the quantity against a +--known constant value. +----------------------------------------------------------------------- +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +entity test is + generic (vmax :real:=10.0); + port(terminal T1:electrical); +end entity; + +architecture atest of test is + +quantity vin across T1; +constant a:real:=1.0; +constant b:real:=2.0; +quantity vin1:real; +quantity vin2:real; + +begin + +vin == vmax/a; + +if (vin==10.0) use +e1: vin1==vmax*b; +else +e2: vin2==vmax; +end use; + + +--if(vin<vmax) use +--e3: vin==vmax/b; +--else +--e4: vin==vmax; +--end use; + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test105.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test105.ams new file mode 100644 index 000000000..d146c52ec --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test105.ams @@ -0,0 +1,79 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test105.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test105.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks for the correctness of quantity as a port declaration. +-- the circuit is a simple RC network with vout acting as thge output port. +-- a sine input is applied to the network. +------------------------------------------------------------------------- +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + FUNCTION COS(X : real) RETURN real; + --ALIAS GND is electrical'reference; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +entity test is + port(quantity vout:out real); +end entity; + +architecture atest of test is + terminal T1,T2:electrical; + quantity VR across IR through T1 to T2; + constant R:real:=100.0; + constant C:real:=1.0e-9; + quantity vout across T2; + quantity vin across T1; +begin + vsource: vin==5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + + vres: IR== VR/R; + cap: vout==C*IR'integ; + +end atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test106.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test106.ams new file mode 100644 index 000000000..c887f76c5 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test106.ams @@ -0,0 +1,86 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test106.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test106.ams +-- Author(s) : Geeta Balarkishnan (gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple resistor model... +-- the test is done for checking the correct implementation +--of the simple simultaneous equation statement.it checks +--nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +entity test is +end entity; + +architecture atest of test is + terminal T1,T2, T3, T4,T5,T6:electrical; + quantity VRgen across IRgen through T1 to T2; + quantity VLgen across ILgen through T2 to T3; + quantity VRin across IRin through T3; + quantity VR1 across IR1 through T4 to T5; + quantity VR1A across IR1A through T4 to T6; + quantity VC1A across IC1A through T6 to T5; + quantity VC1 across IC1 through T5; + quantity VS across T1; + constant C1: real:=3.5e-3; + constant C1A: real:=0.3e-3; +begin + + e1: VRgen == IRgen*10.0; + e2: VLgen == 0.5*ILgen'dot; + e3: VRin == IRin*500.0; + e4: VR1 == IR1*1.0; + e5: VR1A == IR1A*0.2; + e6: IC1 == C1 * VC1'dot; + e7: IC1A == C1A*VC1A'dot; + + esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test107.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test107.ams new file mode 100644 index 000000000..03d2eaa54 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test107.ams @@ -0,0 +1,152 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test107.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test107.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks for the correct impelmentation of the port terminal +-- decl. signal decl. of type real, type array decl. +-- the test performs a 4 bit digital to analog conversion. +---------------------------------------------------------------------- + +PACKAGE electricalsystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; +END electricalsystem; + +USE work.electricalsystem.all; +ENTITY dac is + port(inputvector : in bit_vector(3 downto 0); --inputvector is an array of 16 bits + terminal T1, T2: electrical); --terminal declarations +END dac; + +ARCHITECTURE behavior OF dac IS + + type temp_array is array(0 to 3) of integer; -- temp to store the array values + quantity vout across T1 to T2; --output of the dac + + signal vout_sig, vcopy : real; +BEGIN + + dac_process: PROCESS(inputvector) + variable a : temp_array := (0,0,0,0); + variable tmp : real; + + BEGIN + for index in 3 downto 0 loop + if inputvector(index) = '0' then + a(index) := 0; --bit to integer conversion done here + else a(index) := 1; + end if; + end loop; + + tmp := real(a(3)*8) + real(a(2)*4) + real(a(1)*2 + a(0)); --find the corresponding value of the binary + vout_sig <= tmp; + + END PROCESS dac_process; + + -- digital to analog conversion is done here + vout == vcopy; + + convert: process(vout_sig) + begin + vcopy <= TRANSPORT vout_sig; + end process; + +END behavior; +use work.electricalsystem.all; +ENTITY tb_dac is +end tb_dac; + +architecture stimuli of tb_dac is + signal myinputvector : bit_vector(3 downto 0); + terminal tout : electrical; + component dac port( inputvector : in bit_vector(3 downto 0); + terminal T1, T2: electrical); + end component; + for all: dac use entity work.dac(behavior); + +BEGIN + + unit:dac port map (myinputvector, tout, electrical'reference); + + stimuli_process: process + BEGIN + + myinputvector <= "0000"; + wait for 10 ns; + + myinputvector <= "0001"; + wait for 10 ns; + + myinputvector <= "0010"; + wait for 10 ns; + + myinputvector <= "0100"; + wait for 10 ns; + + myinputvector <= "1000"; + wait for 10 ns; + + myinputvector <= "1100"; + wait for 10 ns; + + myinputvector <= "1110"; + wait for 10 ns; + + myinputvector <= "1101"; + wait for 10 ns; + + myinputvector <= "1111"; + wait for 10 ns; + myinputvector <= "0000"; + wait for 10 ns; + + myinputvector <= "1100"; + wait for 10 ns; + + myinputvector <= "1010"; + wait for 10 ns; + + wait; + end process; +end stimuli; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test108.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test108.ams new file mode 100644 index 000000000..d8eb05903 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test108.ams @@ -0,0 +1,75 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test108.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test100.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple resistor model... +-- the test is done for checking the correct implementation +-- of the simple simultaneous equation statement.it checks +-- nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +entity test is +end entity; + +architecture atest of test is + terminal t1, t2: electrical; + quantity vd across id through T1; -- to T2; + quantity charge :real; + constant vt:real:=0.02; +begin + + p1: procedural is + begin + vd:=1.0*id; + end procedural; + +end architecture; + diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test109.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test109.ams new file mode 100644 index 000000000..3424a2d73 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test109.ams @@ -0,0 +1,80 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test109.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test109.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks for the correctness of the procedural statements. +-- multiple terms on the RHS +---------------------------------------------------------------------- +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUD REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + + --ALIAS GND is electrical'reference; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +entity test is +end entity; + +architecture atest of test is + terminal t1,t2: electrical; + quantity vd across id through t1 to t2; + quantity charge:real; + constant vt:real:=0.0258; + constant x:real:=1.0; + quantity ic:real; + +begin + p1: procedural + begin + id:=0.1*(exp((vd-1.0*id)/vt)-1.0); + charge := x*id; + ic:= charge'dot; + end procedural; + +end architecture; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test110.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test110.ams new file mode 100644 index 000000000..359bf84d0 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test110.ams @@ -0,0 +1,69 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test110.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +-- an example of a model having both a signal assignment statement +-- as well as a simple simultaneous statement. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND reference; + FUNCTION SIN (X : real ) RETURN real; + FUNCTION EXP (X : real ) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +use std.textio.all; +ENTITY test IS +END test; + +ARCHITECTURE behavior OF test IS + CONSTANT r1 : real := 100.0; -- value of R1 + terminal t1 : electrical; + QUANTITY vIn ACROSS t1; + QUANTITY vR ACROSS iR THROUGH t1 ; + signal y:bit:='0'; +BEGIN + +process(y) +begin + y <= not(y) after 1000 ns; + +end process; + + testbench:PROCESS + BEGIN + WAIT ON y; + END PROCESS; + res_stmt1: vR == iR * r1 ; + vsource: vIn == 5.0 * sin(2.0 * 3.14 * 100000.0 * real(time'pos(now)) * 1.0e-15); + +END ARCHITECTURE behavior; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test111.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test111.ams new file mode 100644 index 000000000..118ec318f --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test111.ams @@ -0,0 +1,75 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test111.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : model.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks the correctness of the Q'Tolerance. +-- the test checks for the simpel diode implementation +-- wherein the charge is evaluated wrt a relative tolerance value +---------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +entity test is + generic(a:real:=1.0e-10; b:real:=0.0); + port (terminal t1: electrical); +end entity; + +architecture atest of test is + quantity vd tolerance "reltol=1.0e-2" across id through t1; + quantity charge: real; + quantity ic : real; + constant rd: real:=1.0; +begin + e1: id== a*(sin((vd-id*rd)/0.5)-1.0); + e2: charge== b*id; + e3: ic==charge'dot; +end architecture; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test112.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test112.ams new file mode 100644 index 000000000..b50437f4d --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test112.ams @@ -0,0 +1,86 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test112.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : model.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks the correctness of the subtype declarations for the +-- through and across quantities. +---------------------------------------------------------------------- +PACKAGE electricalSystem IS + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; + +entity test is + +subtype voltage is real; +subtype current is real; +nature electrical is voltage across current through ground reference; + +end entity; + +architecture atest of test is + +constant R1: real :=10.0; +constant R2: real :=5.0; +constant R3: real :=1.0; +terminal T1,T2:electrical; +quantity V1 across I1 through T1 to T2; +quantity V2 across I2 through T2 to electrical'reference; +quantity V3 across I3 through T2 to electrical'reference; +quantity VS across T1 to electrical'reference; + +begin + +e1: V1 == I1*R1; +e2: V2 == I2*R2; +e3: V3 == I3*R3; + +esource:VS == 5.0 * sin(2.0 * 3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test113.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test113.ams new file mode 100644 index 000000000..81e546ea7 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test113.ams @@ -0,0 +1,79 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test113.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test113.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks the correctness of the Q'Tolerance for across qnty +-- and for the real quantity.The test checks for the simpel diode +-- implementation wherein the charge is evaluated wrt a relative +-- tolerance value +-- the test doesn't seem to take a tolerance associated with a +-- free quantity. we need to check on this!! (LRM : 4.3.1 spec +-- followed. +---------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +entity test is + generic(a:real:=1.0e-10; b:real:=0.0); + port (terminal t1: electrical); +end entity; + +architecture atest of test is + quantity vd across id through t1; -- to electrical'reference; + quantity charge:real tolerance "reltol=1.0e-2"; + --quantity ic : real; + constant rd: real:=1.0; +begin + e1: id== a*(sin((vd-id*rd)/0.5)-1.0); + e2: charge== b*id; + --e3: ic==charge'dot; +end architecture; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test114.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test114.ams new file mode 100644 index 000000000..1471d82c3 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test114.ams @@ -0,0 +1,77 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test114.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : model.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks the correctness of the two currents associated +-- as through between same terminals.for eg: consider 2 resistors in +-- parallel.. here vd is same and id and ic are the currents. +-- the test checks for the simpel diode implementation +-- wherein the charge is evaluated wrt a relative tolerance value +---------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +entity test is + generic(a:real:=1.0e-10; b:real:=0.0); + port (terminal t1: electrical); +end entity; + +architecture atest of test is + quantity vd across id, ic through t1; + quantity charge: real; + --quantity ic : real; + constant rd: real:=1.0; +begin + e1: id== ((vd-id*rd)/0.5); + e2: charge== b*id; + e3: ic==charge'dot; +end architecture; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test115.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test115.ams new file mode 100644 index 000000000..e71523f00 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test115.ams @@ -0,0 +1,79 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test115.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test115.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks for the correctness of the interface declaration: +-- quantity : in| out. +-- ref LRM 4.3.2 +--------------------------------------------------------------------- +PACKAGE electricalSystem IS + subtype voltage is real; + subtype current is real; + NATURE electrical is voltage across current THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +entity test is + port(quantity vout:out electrical); +end entity test; + +architecture atest of test is + terminal t1,t2: electrical; + + quantity vin across iin through t1; + quantity vr across ir through t1 to t2; + quantity vout across t1 to t2; + +begin + + e1: vin== 5.0 * sin(2.0 * 3.1415 * 10000000.0 * real(time'pos(now)) *1.0e-15); + e2: vr==ir*1.0; + e3: vout== vr; + +end architecture; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test116.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test116.ams new file mode 100644 index 000000000..87032a99a --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test116.ams @@ -0,0 +1,79 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test116.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test116.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks for the correctness of the interface declaration: +-- quantity : in| out. A simple R circuit with an ac voltage source +-- is used. +-- ref LRM 4.3.2 +--------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical is real across real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +entity test is + port(quantity vout:out voltage); +end entity test; + +architecture atest of test is + terminal t1,t2: electrical; + + quantity vin across iin through t1; + quantity vr across ir through t1 to t2; + quantity vout across t1 to t2; + +begin + + e1: vin== 5.0 * sin(2.0 * 3.1415 * 10000000.0 * real(time'pos(now)) *1.0e-15); + e2: vr==ir*1.0; + e3: vout== vr; + +end architecture; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test117.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test117.ams new file mode 100644 index 000000000..f9d993352 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test117.ams @@ -0,0 +1,83 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test117.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test117.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks the correctness of the subtype usage and also +-- checks for the tolerance aspect associated with the subtype. +---------------------------------------------------------------------- + +Package electricalsystem is + FUNCTION SIN(X : real) RETURN real; + +subtype voltage is real tolerance "default_voltage=1.0e-3"; +subtype current is real; -- tolerance "default_current= 1.0e-4"; +subtype resistance is real; + +nature electrical is voltage across current through ground reference; +end package electricalsystem; + +use work.electricalsystem.all; + +entity test is +end entity; + +architecture atest of test is +--subtype voltage is real tolerance "default_voltage=1.0e-3"; +--subtype current is real; -- tolerance "default_current= 1.0e-4"; +subtype resistance is real; + +nature electrical is voltage across current through; + +terminal t1, t2: electrical; +quantity vr tolerance across ir through t1 to t2; +quantity vs across t1; +--quantity vout across t2; + +begin +e1: vs==5.0 *sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +e2: vr==ir*1.0; + +end architecture; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test118.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test118.ams new file mode 100644 index 000000000..a9831e1ac --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test118.ams @@ -0,0 +1,93 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test118.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test118.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- + +-- the test checks for the correctness of the implemenatation of the case +-- statement. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + + --ALIAS GND is electrical'reference; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +entity test is +end entity test; + +architecture atest of test is + terminal t1:electrical; + signal ison: boolean; + quantity vr across ir through t1; + constant vt:real:=0.0258; +begin + +process + variable off : boolean:=true; +begin + ison <= not off; + case off is + when true=> + ison<= not off; + when false=> + ison<=off; + end case; +end process; + +source: vr==10.0 * sin(2.0 *(22.0/7.0)*100000.0*real(time'pos(now)) * 1.0e-15); +if ison use + ir== 5.0; --*(exp(vr/vt)-1.0); +else + ir==0.0; +end use; + +break on ison; + +end architecture; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test119.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test119.ams new file mode 100644 index 000000000..973d0f2db --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test119.ams @@ -0,0 +1,91 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test119.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test1.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- This is the simple resistor model that sets the foundation on which +-- we build SIERRA, the VHDL AMS simulator. The circuit consists of 3 +-- resistors connected to a voltage source. +-- T1 R1 T2 +-- o-----/\/\----o-------- +-- | | | +-- ( ) > > +-- |Vs = 5sinwt >R2 >R3 +-- | > > +-- |_____________|____|___ +-- |gnd +-- ---- +-------------------------------------------------------------------------- +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +entity test is +end entity; + +architecture atest of test is + + constant R1: real :=10.0; + constant R2: real :=5.0; + constant R3: real :=1.0; + terminal T1,T2:electrical; + quantity V1 across I1 through T1 to T2; + quantity V2 across I2 through T2 to electrical'reference; + quantity V3 across I3 through T2 to electrical'reference; + quantity VS across T1 to electrical'reference; + +begin + + e1: V1 == I1*R1; + e2: V2 == I2*R2; + e3: V3 == I3*R3; + + esource:VS == 5.0 * sin(2.0 * 3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test121.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test121.ams new file mode 100644 index 000000000..8166369d6 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test121.ams @@ -0,0 +1,80 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test121.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test3.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- this is to check the quantity: q'dot in the lhs and rhs of the +-- simultaneous statements +--------------------------------------------------------------------- +PACKAGE electricalSystem is + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +entity test is +end entity; + +architecture atest of test is + quantity x11: real; + constant x1:real:=2.0; + constant x2:real:=1.0; + constant m1 : real:=1.0; + quantity f : real; + quantity dx1 : real; + +begin +e1: f == 10.0* sin(2.0 * 3.141592 *10000.0 * real(time'pos(now))*1.0e-12); +e2: x11 == f*(x1-x2)/m1; +e3: dx1 == f'dot; + +-- x1'dot == f*(x1-x2)/m1; +-- x2'dot == f*(x1-x2)/m2; +-- xs == (m1*x1+m2*x2)/(m1+m2); +-- m3 == m1*x1'dot+ m2*x2'dot; +end atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test122.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test122.ams new file mode 100644 index 000000000..c3f9c096f --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test122.ams @@ -0,0 +1,80 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test122.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test122.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- to check for the correct implementation of the simple simultaneous +-- statements +------------------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + + --ALIAS GND is electrical'reference; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +entity chk is + + generic(i:real:=1.0e-9); + port(terminal t1, t2: electrical); + +end chk; + +architecture achk of chk is + quantity vd across id through t1 to t2; + quantity q: real; + quantity ic:real; + constant vth : real:= 0.025; +begin + +e1: id == i*(exp(vd/vth)-1.0); +e2: q == id*0.25; +e3: ic == q'dot; + +end achk; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test123.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test123.ams new file mode 100644 index 000000000..6e2699793 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test123.ams @@ -0,0 +1,82 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test123.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test113.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- to check the correct implementation of the simultaneous if statement +-- break and 'above is also used. it checks for the eqns v'=g*v**2 for +-- +g and -g. +---------------------------------------------------------------------- +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH; + FUNCTION SIN(X : real) RETURN real; +-- alias ground is electrical'reference; +END PACKAGE electricalSystem; + +use work.electricalsystem.all; +entity test is +end entity test; + +architecture atest of test is + + quantity v : real; + quantity s: real; + constant g : real :=9.81; + constant r : real:=1.02; + +begin + +break v=>0.0, s=>100.0; + +break v=>-v when not s'above(0.0); + +s'dot==v; + +if v>0.0 use + v'dot == -g+v*v*r; +else + v'dot == -g-v*v*r; +end use; + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test124.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test124.ams new file mode 100644 index 000000000..ee84d2125 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test124.ams @@ -0,0 +1,81 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test124.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test124.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- + +--this test is to chk the support of ALIAS, NATURE in the PACKAGE declaration +--the test also chks the corrct use of quantity and terminal declarations. +-------------------------------------------------------------------------- +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; +END PACKAGE electricalSystem; + +--entity declaration + +use work.electricalsystem.all; +ENTITY Rckt IS + +END Rckt; + +--architecture declaration + +ARCHITECTURE aRckt OF Rckt IS + + + terminal T1, T2 : electrical; + + quantity VR across IR through T1 to T2; + quantity VR1 across IR1 through T2; + quantity VS across T1; + constant R : REAL := 10.00; + +BEGIN + +eqn1 : VR == IR * R; +e2: VR1 == IR1 * R; +eqn2 : VS == 5.0; + +end arckt; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test125.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test125.ams new file mode 100644 index 000000000..6b82f12a1 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test125.ams @@ -0,0 +1,60 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test125.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +-- this model tests for the correst implementation of the 'above +-- statement. +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH; + FUNCTION SIN(X : real) RETURN real; + alias ground is electrical'reference; +END PACKAGE electricalSystem; + +use work.electricalsystem.all; + +entity product is +generic(bound:real:=1.0); +port( + quantity out1:real); +end product; + +architecture pro of product is +constant in1:real:=10.0; +constant in2:real:=1.0; +signal outofbound:out boolean; + +begin + outofbound<=true; + out1== in1*in2; + outofbound<=out1'above(1.0); + +end pro; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test126.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test126.ams new file mode 100644 index 000000000..2c8c320e3 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test126.ams @@ -0,0 +1,78 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test126.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test8.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks the corretness of the 'left 'right 'high 'low +-- 'ascending 'length declarations. +---------------------------------------------------------------------- +entity test is +port (y: out bit); +end test; + +architecture atest of test is +type value is range 10 downto 0; +signal a: bit; +begin + + y<=a; +e1:process +begin +if (value'left=10)then + a <='1'; + else + a <='0'; + end if; + assert (value'right=0) + report "pass 'right check" + assert(value'high=10) + report "pass 'high check" + assert (value'low=0) + report "pass 'low check" + assert (value'ascending=false) + report "pass 'ascending check" + assert (value'length=11) + report "pass 'length check" +end process; +end atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test127.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test127.ams new file mode 100644 index 000000000..09f2cceb9 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test127.ams @@ -0,0 +1,75 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test127.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test9.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- + +--this checks the step limit specification incorporated. +--this gives atleast 20 analog solution points if the +--" STEP LIMIT' is implemented correctly. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + + --ALIAS GND is electrical'reference; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity source is +generic (Amplitude :real:=1.0; + frequency:real:=1.0); +port (quantity sine:out real); +end entity source; + +architecture asource of source is + limit sine:real with 0.05/frequency; + +begin +e1: sine== Amplitude*sin(2*3.14159*frequency*real(time'pos(now))*1.0e-12); + +end architecture asource; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test128.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test128.ams new file mode 100644 index 000000000..760a2c40e --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test128.ams @@ -0,0 +1,86 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test128.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test104.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- this is a test that checks for the correct implementation of if use +-- end use. The condition is checked by comparing the quantity against a +-- known constant value. +----------------------------------------------------------------------- +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + + --ALIAS GND is electrical'reference; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +entity test is +end entity; + +architecture atest of test is + terminal T1, T2:electrical; + + quantity vin across T1 to electrical'reference; + constant a:real:=1.0; + constant b:real:=2.0; + + quantity vin1 across iin1 through T1 to T2; + quantity vin2 across iin2 through T2 to electrical'reference; +begin + +eq1: vin==5.0* sin(2.0 * 3.141592 *1000.0 * real(time'pos(now))*1.0e-12); +eq2: vin1== iin1*a; +eq3: vin2== iin2*b; +if (vin1>5.0) and (vin1<10.0) use +e1: vin1==vin/a; +elsif (vin2<5.0) use +e2: vin2==vin/b; +else +e3: vin1==vin; +end use; +end atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test129.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test129.ams new file mode 100644 index 000000000..052c634b1 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test129.ams @@ -0,0 +1,100 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test129.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +package electricalSystem is + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION POW(X,Y: real) RETURN real; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + type electrical_vector is array(0 to 3) of electrical; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; + +entity test is +generic( a: real); +port( terminal ip: electrical_vector; + terminal op:electrical); +end entity; + +architecture atest of test is +type electrical_vector is array(0 to 3) of electrical; +--variable i: real:=0.0; +variable a:real:=5.0; +variable output:real:=0.0; +quantity vin across ip to electrical'reference; +quantity vout across iout through ip to op; +begin + + for i in 0 to 3 loop + output:=output + vin(i)*a; + end loop; +vout:=output; + +end architecture atest; +-- test bench needs to be corrected + +use work.electricalSystem.all; +entity tb is +end entity; + +architecture atb of tb is +signal myvector : electrical_vector(0 to 3); +terminal tip : electrical_vector; +terminal top:electrical; +component test + port(terminal ip, op: electrical); +end component; +for all: test use entity work.test(atest); +begin + +unit: test port map(tip, top, electrical'reference); + +a_process: process +begin + +myvector == 1.0; +wait for 10 ns; +myvector == 2.0; +wait for 10 ns; +myvector == 2.0; +wait for 10 ns; +myvector ==1.0; +wait for 10 ns; + +wait; + +end process; + +end atb; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test130.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test130.ams new file mode 100644 index 000000000..7ac92b5bd --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test130.ams @@ -0,0 +1,98 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test130.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +package electricalSystem is + NATURE electrical IS real ACROSS real THROUGH; + FUNCTION POW(X,Y: real) RETURN real; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + type electrical_vector is array(0 to 3) of electrical; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; + +entity test is +port( terminal ip: electrical_vector; + terminal op:electrical); +end entity; + +architecture atest of test is +type electrical_vector is array(0 to 3) of electrical; +type t_a is array(0 to 3) of real; +variable i: real:=0.0; +variable output:real:=0.0; +quantity vin across ip to electrical'reference; +quantity vout across iout through ip to op; +begin +t1: process + variable a: t_a :=(1.0, 1.2, 1.5, 2.0); + for i in 0 to 3 loop + output:=output + vin(i)*a(i); + end loop; +vout:=output; +end architecture atest; + +use work.electricalSystem.all; +entity tb is +end entity; + +architecture atb of tb is +signal myvector : electrical_vector(0 to 3); +terminal tip : electrical_vector; +terminal top:electrical; +signal myconst : real_vector(0 to 3); +component test + port(terminal ip, op: electrical); +end component; +for all: test use entity work.test(atest); +begin + +unit: test port map(tip, top, electrical'reference); + +a_process: process +begin + +myvector == 1.0; +wait for 10 ns; +myvector == 2.0; +wait for 10 ns; +myvector == 2.0; +wait for 10 ns; +myvector==1.0; +wait for 10 ns; +wait; + +end process; + +end atb; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test133.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test133.ams new file mode 100644 index 000000000..7a0e28bac --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test133.ams @@ -0,0 +1,77 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test133.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test133.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- this test checks the correctness of the break statement for a +-- quantity port declaration. +-- LRM ref: 8.14 +---------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + subtype voltage is real; + +END PACKAGE electricalSystem; + +use work.electricalSystem.all; + +entity test is + generic (m: real := 1.0); + port (quantity x: out voltage); +end entity test; + +architecture atest of test is +--quantity x: real; +quantity q: real; +begin + break x => 0.0, x'dot => 0.1; + e1: q== x'dot; + x'dot'dot == -1.0*( m*(x*x - 1.0)* x'dot); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test134.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test134.ams new file mode 100644 index 000000000..de8f2e1ef --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test134.ams @@ -0,0 +1,98 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test134.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test151.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- this is a test to check the corretness of the implemntation of the break +-- statement and also the use of quantity port of type voltage. +-- this is a vco model which first sets the initial condition +-- using a break statement. Then again, a break statement is applied to keep +-- the phase within 0-2pi. Thr output voltage eqn is obtained as vout and the +-- phase eqn as phase'dot. +-- LRM ref: 8.14, 4.3.2. +---------------------------------------------------------------------- +PACKAGE electricalSystem IS + SUBTYPE voltage is real; + NATURE electrical IS real ACROSS real THROUGH; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; + +entity vco is + generic( + fc: real := 1.0e6; -- VCO frequency at Vc + df: real := 0.5e6; -- [Hz/V], frequency characteristic slope + Vc: voltage := 0.0 -- centre frequency input voltage + ); + port( quantity Vin: in voltage; + terminal OutTerminal: electrical); +end entity VCO; + +architecture avco of vco is + constant TwoPi: real := 6.283118530718; -- 2pi + + quantity Phase : real; + + -- define a branch for the output voltage source + + quantity Vout across Iout through OutTerminal to electrical'reference; + +begin + -- use break to set the phase initial condition + break Phase => 0.0; + + -- another break statement keeps the phase within 0.. 2pi + break Phase => Phase mod TwoPi on Phase'above(TwoPi); + + -- phase equation + Phase'dot == TwoPi*realmax(0.5E6, fc+(Vin-Vc)*df); + + -- output voltage source equation + Vout == 2.5*(1.0+sin(Phase)); + +end architecture avco; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test135.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test135.ams new file mode 100644 index 000000000..d247089fc --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test135.ams @@ -0,0 +1,71 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test135.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground refernce; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; + +USE use.electricalSystem.all; +ENTITY vpwl IS + GENERIC (v0 : real := 0.0); + PORT (SIGNAL slope : in real; + TERMINAL p, m : electrical); +END ENTITY vpwl; + +ARCHITECTURE one OF vpwl IS + QUANTITY v ACROSS i THROUGH p TO m; +BEGIN + v==v0; + BREAK WHEN slope'event; + v'dot == slope; +END ARCHITECTURE one; + +entity tb is +end entity; +architecture atb of tb is +signal myinput: real; + +begin + myinput<='1'; +ARCHITECTURE two OF vpwl IS + QUANTITY v ACROSS i THROUGH p TO m; + SIGNAL startv : voltage := v0; +BEGIN + BREAK WHEN slope'event; + startv <= v WHEN slope'event; + v == startv + slope'delayed * startv'last_event; +END ARCHITECTURE two; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test136.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test136.ams new file mode 100644 index 000000000..09357f084 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test136.ams @@ -0,0 +1,82 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test136.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test136.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A resistor bridge network... +-- the test is done for checking the correct implementation +-- of the simple simultaneous equation statement.it checks +-- nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +entity test is +end entity; + +architecture mesh of test is + +terminal t1, t2, t4 : electrical; +quantity v1 across i1 through t1 to t2; +quantity v2 across i2 through t2; +quantity v3 across i3 through t4; +quantity v4 across i4 through t1 to t4; +quantity v5 across i5 through t1; +quantity vs across t1; + +begin + +e1: v1== i1*10.0; +e2: v2== i2*10.0; +e3: v3== i3*10.0; +e4: v4== i4*10.0; +e5: v5== i5*20.0; + +esource: vs== 10.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-15); + +end architecture mesh; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test137.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test137.ams new file mode 100644 index 000000000..43c4d6dc9 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test137.ams @@ -0,0 +1,136 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test137.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------------- +-- File : test137.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +----------------------------------------------------------------------------- +-- Description : +----------------------------------------------------------------------------- +-- the test cheks the correctness of the electrical_vector.array of terminals +-- also the use of real vectors.. array of real values. +-- the circuit is a weighted summer the output is available at the +-- ooutput terminal o. +-- LRM 4.3.2 +------------------------------------------------------------------------------- +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + TYPE real_vector is array(0 to 3) of real; + TYPE electrical_vector is array(0 to 3) of electrical; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +generic (beta,gamma : real_vector); +port(terminal inp, inm: electrical_vector; + terminal o: electrical); +end entity; +architecture atest of test is +--TYPE real_vector is array(0 to 3) of real; +--TYPE electrical_vector is array(0 to 3) of electrical; +quantity vp across ip through inp to electrical'reference; +quantity vm across inm to electrical'reference; +quantity vo across io through o to electrical'reference; +variable bvs, gvs : real:=0.0; +function "*" (a:real_vector; + b: electrical_vector'across) +return real is + +variable result : real:=0.0; +begin + +for i in (0 to 3) loop + result:= result+ a(i)*b(i); +end loop; +return result; +end function "*"; +begin +vo== beta*vp - gamma*vm; +end architecture atest; + +use work.electricalSystem.all; + +entity tb is +end entity; + +architecture atb of tb is +signal myvec1,myvec2:real_vector(0 to 3); +signal myinput1, myinput2: electrical_vector(0 to 3); +terminal tinp, tinm: electrical_vector; +terminal to: electrical; + +component test + port(terminal inp, inm: electrical_vector; + terminal o: electrical); +end component test; +for all: test use entity work.test(atest); +begin +unit: test port map(tinp,tinm, to, electrical'reference); +a_process: process +begin + +myvec1 == 1.0; +myinput1 == 1.0; +myvec2 == 2.0; +myinput2 == 2.0; +wait for 10 ns; +myvec1 == 1.0; +myinput1 == 1.0; +myvec2 == 2.0; +myinput2 == 2.0; +wait for 10 ns; +myvec1 == 1.0; +myinput1 == 2.0; +myvec2 == 2.0; +myinput2 == 1.0; +wait for 10 ns; +myvec1 == 1.0; +myinput1 == 2.0; +myvec2 == 2.0; +myinput2 == 1.0; +wait for 10 ns; + +end process; + +end atb; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test138.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test138.ams new file mode 100644 index 000000000..4c11b3aeb --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test138.ams @@ -0,0 +1,72 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test138.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +package mosdata is +-- + type mosmodel is + record + vt0 : real; + kp : real; + end record mosmodel; + + nature electrical is real across real through ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + +end package mosdata; + +use work.mosdata.all; + +entity test is +generic ( + model: mosmodel:=( + vt0 => 0.7, + kp => 1.0); + + constant a: real:=1.0 + ); +end entity; + +architecture atest of test is +terminal t1, t2: electrical; +quantity vr across ir through t1 to t2; +quantity vs across t1; + +begin +e1: vs== 5.0 * sin(2.0 * 3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +e2: vr== ir* model.kp*a + model.vt0; + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test139.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test139.ams new file mode 100644 index 000000000..16e5a9ebf --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test139.ams @@ -0,0 +1,122 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test139.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +----------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +----------------------------------------------------------------------- +-- File : test139.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +----------------------------------------------------------------------- +-- Description : +----------------------------------------------------------------------- +-- this test checks the correctness of the record declaration as a type +-- it also checks for the usage of the record element declarations. +-- the assert statement is also checked. +-- the record is declared within a package +-- the test also checks the correctness of the function impelmentation. +-- the function accepts the record parameters and returns the result of +-- type real. +----------------------------------------------------------------------- +PACKAGE electricalsystem IS + + SUBTYPE voltage IS real; + SUBTYPE current IS real; + + NATURE electrical IS + voltage ACROSS + current THROUGH ground reference; + +END PACKAGE electricalsystem; + +PACKAGE types IS + + TYPE cmodel IS RECORD + cj : real; + cjsw : real; + defw : real; + narrow : real; + END RECORD; + +END PACKAGE types; + +USE work.electricalsystem.all; +USE work.types.all; + +ENTITY test IS + GENERIC (cnom : real := 0.0; + model : cmodel := (0.0, 0.0, 1.0e-6, 0.0); + l : real := 0.0; + w : real := 0.0; + ic : real := 0.0 ); + PORT (TERMINAL t1,t2 : electrical); +END ENTITY test; + +ARCHITECTURE atest OF test IS + FUNCTION c_init ( cnom : real; + model : cmodel; + l, w : real) + RETURN real IS + VARIABLE ceff : real; -- effective capacitance value + VARIABLE weff : real; -- effective channel width + BEGIN + + IF cnom /= 0.0 THEN + ASSERT (model.cj = 0.0 AND model.cjsw = 0.0) + REPORT "Both cnom and model specified"; + ceff := cnom; + ELSE + ASSERT (l > 0.0) + REPORT "Channel length not specified"; + IF w = 0.0 THEN + weff := model.defw; + ELSE + weff := w; + END IF; + ASSERT (weff > 0.0) + REPORT "Channel width not specified"; + ceff := model.cj*(l-model.narrow)*(weff-model.narrow) + + model.cjsw*(l+weff-2.0*model.narrow); + END IF; + RETURN (ceff); + END FUNCTION c_init; + + CONSTANT ceff : real := c_init(cnom, model, l, w); + QUANTITY v ACROSS i THROUGH t1 TO t2; +BEGIN + i == ceff * v'dot; +END ARCHITECTURE atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test140.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test140.ams new file mode 100644 index 000000000..f43142bac --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test140.ams @@ -0,0 +1,77 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test140.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test140.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks for the correctness of the quantity, terminal, nature +-- and package declarations. the terminals are assigned as terminals. +-- a simple V-R circuit is considered. +----------------------------------------------------------------------- + +PACKAGE electricalsystem IS + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +-- SUBTYPE voltage IS real; +-- SUBTYPE current IS real; + +NATURE electrical IS real ACROSS real THROUGH ground reference; + +END PACKAGE electricalsystem; +use work.electricalsystem.all; + +ENTITY test IS + PORT (TERMINAL p: electrical); +END ENTITY test; + +ARCHITECTURE sine OF test IS + constant ampl: REAL:=5.0; + constant freq: real:=10000.0; + QUANTITY v ACROSS i THROUGH p; + quantity vr across ir through p; +BEGIN +e1: v == ampl * sin(2.0 * 3.14159 * freq * real(time'pos(now))*1.0e-12); +e2: vr== ir*10.0; +END ARCHITECTURE sine; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test141.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test141.ams new file mode 100644 index 000000000..5303951b9 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test141.ams @@ -0,0 +1,75 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test141.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test141.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +-- this is the behavioral model of a simple error amplifier. +-- the entity consists of a quatity port and the architecture consists +-- of a simple simultaneos statement +---------------------------------------------------------------------- +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +-- subtype voltage is real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity ErrorAmplifier is + generic( Gain : REAL := 10.0 -- amplifier gain + ); + port( terminal P_T,N_T: electrical; -- analog input pins + quantity Vout : out real -- analog output + ); +end entity ErrorAmplifier; + +architecture Behavior of ErrorAmplifier is + +quantity DeltaV across P_T through N_T; -- differential input voltage +begin +e1: DeltaV== 1.0* sin(2.0 * 3.141592 *10000.0 * real(time'pos(now))*1.0e-12); +e2: Vout == Gain*DeltaV; + +end architecture Behavior; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test143.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test143.ams new file mode 100644 index 000000000..f83c97aa3 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test143.ams @@ -0,0 +1,83 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test143.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +------------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +------------------------------------------------------------------------- +-- File : test143.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +------------------------------------------------------------------------ +-- Description : +------------------------------------------------------------------------ +-- the test checks for the correctness of the concurrent signal +-- assignment. it accepts sine wave as input and the architecture has a +-- concurrent signal assignment statement that assigns either a 1 or 0 +-- depending on the condition. +------------------------------------------------------------------------ + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + subtype voltage is real; + subtype current is real; + +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity AnaComparator is + generic( Vth: voltage := 0.0 -- [V] comparator threshold level + ); + port( terminal P_T: electrical; + signal Out_T: out BIT + ); +end entity AnaComparator; + +architecture Behavior of AnaComparator is + quantity DeltaV across P_T to electrical'reference; -- differential input voltage + +begin + +e1: DeltaV== 5.0*sin(2.0*3.14159*10000.0*real(time'pos(now))*1.0e-15); + + out_T <= '1' when DeltaV'above(0.0) -- trigger event when V+>V- + else '0' when not DeltaV'above(0.0); -- trigger event when V+<=Vt- + +end architecture Behavior; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test144.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test144.ams new file mode 100644 index 000000000..7fe6c01b8 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test144.ams @@ -0,0 +1,130 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test144.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +------------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +------------------------------------------------------------------------- +-- File : test144.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------------- +-- Description : +----------------------------------------------------------------------------- +-- the test checks for the correctness of the ATTRIBUTE declaration +-- also checks function, real_vector and quantity vector declarations +-- the integer range<> is used instead of specifying the actaul range +-- or size of the matrix. +-- 1 D and 2 D matrix operations are verified. +-- the test performs the matrix dot product caluculation and also +-- product of a 2 D matrix with a column vector. +---------------------------------------------------------------------- + +PACKAGE electrical_system IS + + -- declare attribute to hold units + ATTRIBUTE unit : string; + NATURE electrical IS + real ACROSS + real THROUGH; + NATURE electrical_vector IS ARRAY(integer range<>) OF electrical; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + NATURE real_vector IS ARRAY(integer range<>) of real; +END PACKAGE electrical_system; + +PACKAGE real_aux IS + TYPE real_vector IS ARRAY(integer range<>) OF real; + TYPE real_matrix IS ARRAY(integer range<>, integer range<>) OF real; + + -- scalar := (row_)vector * (column_)vector + + FUNCTION "*"(v1, v2 : real_vector) RETURN real IS + VARIABLE result : real := 0.0; + BEGIN + ASSERT v1'range = v2'range; -- to ensure correct dot product evaluation + FOR i IN v1'range LOOP + result := result + v1(i) * v2(i); + END LOOP; + RETURN result; + END FUNCTION "*"; + + -- (column_)vector := matrix * (column_)vector + + FUNCTION "*"(m : real_matrix; v : real_vector) RETURN real_vector IS + VARIABLE result : real_vector(m'range(1)); + BEGIN + ASSERT m'range(2) = v'range; + FOR i IN result'range LOOP + result(i) = 0.0; + FOR j IN v'range LOOP + result(i) := result(i) + m(i,j) * v(j); + END LOOP; + END LOOP; + RETURN result; + END FUNCTION "*"; +END PACKAGE real_aux; + +use work.electrical_system.all; +-- ideal multiplier + +ENTITY mult IS + PORT (TERMINAL in1, in2, output, ref : electrical); +END ENTITY mult; + +ARCHITECTURE ideal OF mult IS + QUANTITY vout ACROSS iout THROUGH output TO ref; + QUANTITY vin1 ACROSS in1 TO ref; + QUANTITY vin2 ACROSS in2 TO ref; +BEGIN + vout == vin1 * vin2; +END ARCHITECTURE ideal; + +USE work.electrical_system.all; +USE work.real_aux.all; + +ENTITY xfrm IS + GENERIC (ml : real_matrix); -- self/mutual inductances + PORT (TERMINAL p, m : electrical_vector); +END ENTITY xfrm; + +ARCHITECTURE one OF xfrm IS + QUANTITY v ACROSS i THROUGH p TO m; -- arrays! +BEGIN + v == ml*real_vector(i'dot); +END ARCHITECTURE one; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test145.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test145.ams new file mode 100644 index 000000000..c27c40f5b --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test145.ams @@ -0,0 +1,359 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test145.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test145.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : June 2001 +---------------------------------------------------------------------- +-- Description : +-- this is a mos model. It tests for the correctness of the procedural +-- statement. +-- +-- the model accepts the mos data as generic constants. The terminals +-- are defined as of nature electrical. +-- it also tests the alias declaration for real'low. +-- Charges associated with the 4 terminals are declared as quantities. +-- The voltage associated with each of them is also defined. +-- a signal is used to drive i.e to carry out a generic initialization. +-- The various mos equations are evaluated depending on the conditions. +-- The equations for charges and currents are evaluated. +---------------------------------------------------------------------- + +package mosdata is + NATURE electrical is real across real through; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + alias undefined is real'low; + constant Temperature: real:=27.0; + constant eps0 : real :=8.85418e-12; + constant Ni : real :=1.45e16; + constant Boltzmann : real :=1.380662e-23; + constant echarge: real :=1.6021892e-19; + constant epsSiO2 : real :=3.9*eps0; + constant epsSi : real :=11.7*eps0; + constant kTQ : real :=Boltzmann*temperature/echarge; + constant pi: real := 3.14159; +end package mosdata; + +use work.mosdata.all; +entity mos is + + generic( + width : real:=1.0E-4; + length : real:=1.0E-4; + channel: real :=1.0; + kp :real:= 2.0E-5; + gamma :undefined; + phi :undefined; + tox :real:= 1.0E-7; + nsub :real:= 0.0; + nss :real:=0.0; + nfs :real:= 0.0; + tpg :real:= 1.0; + xj :real:=0.0; + ld :real:= 0.0; + u0 :real:= 600.0; + vmax :real:=0.0; + xqc :real:= 1.0; + kf :real:=0.0; + af :real:=1.0; + fc :real:=0.5; + delta :real:=0.0; + theta :real:=0.0; + eta :real:=0.0; + Sigma :real:=0.0; + kappa :real:=0.2 ); + + port ( terminal drain, gate, source, bulk : electrical); + +end entity mos; + +architecture amos of mos is + quantity Qc, Qb, Qg: real; + quantity Qcq, Qbq, Qgq : real; -- channel, bulk and gate charges + quantity Vdsq across drain to source; + quantity Vgsq across gate to source; + quantity Vbsq across bulk to source; + quantity Idq through drain; + quantity Igq through gate; + quantity Isq through source; + quantity Ibq through bulk; + + signal Initialized: boolean; -- use a signal as generic initialisation + +begin + MOSeqns: procedural is + variable + cox,vt,beta,sigma,nsub,Phi,Gamma,nss,ngate,A,B,C,D,Vfb,fshort, + wp,wc,sqwpxj,vbulk,delv,vth,Vgstos, Vgst, + Ueff,Tau,Vsat,Vpp,fdrain, + stfct,leff,xd,qnfscox,fn,dcrit,deltal,It,Ids,R,Vds,Vgs,Vbs, + forward ,egfet,fermig, mobdeg: real; + begin -- procedural statements + + if not Initialized then + if tox<=0.0 then + cox:=epsSiO2/1.0e-7; + else + cox:=epsSiO2/tox; + end if; + + if kp = 0.0 then + beta:=cox*u0; + else + beta:=kp; + end if; + + nsub := nsub * 1.0e6; -- scale nsub to SI units + + if (phi = undefined) then + if (nsub > 0.0) then + if (0.1<2.0*KTQ*(nsub/Ni)) then + Phi:=(2.0*kTQ*(nsub/Ni)); + else + Phi:=0.1; + end if; + else + Phi:=0.6; + end if; + else + Phi:=phi; + end if; + + if (gamma = undefined) then + if (nsub > 0.0) then + Gamma:=sqrt(2.0*epsSi*echarge*nsub)/cox; + else + Gamma:=0.0; + end if; + else + Gamma:=gamma; + end if; + + nss:=nss*1.0e4; -- Scale to SI + ngate:=gamma*1.0e4; -- Scale to SI + + leff:=length-2.0*ld; + if leff>0.0 then + Sigma:= eta * 8.15e-22/(cox*leff*leff*leff); + else + Sigma:=0.0; + end if; + + if nsub>0.0 then -- N.B. nsub was scaled, above. + xd:=sqrt(2.0*epsSi/(echarge*nsub)); + else + xd:=0.0; + end if; + + if (nfs>0.0) and(cox>0.0) then + qnfscox:=echarge*nfs/cox; + else + qnfscox:=0.0; + end if; + + if cox>0.0 then + fn:=delta*pi*epsSi*0.5/(cox*width); + else + fn:=delta*pi*epsSi*0.5*tox/epsSiO2; + end if; + + --Scale beta and convert cox from Fm^-2 to F + beta:=beta*width/leff; + cox:=cox*width*leff; + + Initialized <= true; + end if; -- not initialized + + Vds:=channel*Vdsq; + if Vds>=0.0 then + Vgs:=channel* Vgsq; + Vbs:=channel* Vbsq; + forward:=1.0; + else + Vds:=-Vds; + Vgs:=channel* Vgsq; + Vbs:=channel* Vbsq; + forward:=-1.0; + end if; + + if Vbs<=0.0 then + A:=Phi-Vbs; + D:=sqrt(A); + else + D:=2.0*sqrt(Phi)*Phi/(2.0*Phi+Vbs); + A:=D*D; + end if; + + Vfb:=Vt-Gamma*sqrt(Phi)-Sigma*Vds; + if (xd=0.0) OR (xj=0.0) then + fshort:=1.0; + else + wp:=xd*D; + wc:=0.0631353*xj+0.8013292*wp-0.01110777*wp*wp/xj; + sqwpxj:=sqrt(1.0-(wp*wp/((wp+xj)*(wp+xj)))); + fshort:=1.0-((ld+wc)*sqwpxj-ld)/leff; + end if; + + vbulk:=Gamma*fshort*D+fn*A; + if nfs=0.0 then + delv:=0.0; + else + delv:=kTQ*(1.0+qnfscox+vbulk*0.5/A); + end if; + + vth:=Vfb+vbulk; + Vgstos:=Vgs-Vfb; + + if (vgs-vth > delv) then + Vgst:=Vgs-vth; + else + Vgst:= delv; + end if; + + if (vgs>=vth) or (delv/=0.0) then + + if (Vbs<=0.0) or (Phi /= 0.0) then + B:=0.5*Gamma/D+fn; + else + B:=fn; + end if; + + mobdeg:=1.0/(1.0+theta*Vgst); + + if (vmax /=0.0) then + Ueff:=u0*mobdeg; + Tau:=Ueff/Leff*vmax; + else + Tau:=0.0; + end if; + + Vsat:=Vgst/(1.0+B); + Vsat:=Vsat*(1.0-0.5*Tau*Vsat); -- not quite the same as SPICE + if (vds<Vsat) then + Vpp:=vds; + else + Vpp:= Vsat; + end if; + + fdrain:=1.0/(1.0+Tau*Vpp); + if (Vgs<vth+delv) and (nfs>0.0) then + stfct:=exp((Vgs-vth-delv)/delv); + else + stfct:=1.0; + end if; + + if Vds>=Vsat then + if (kappa>0.0) and (xd>0.0) then + + if vmax=0.0 then + deltal:=sqrt(kappa*xd*xd*(Vds-Vsat)); + else + dcrit:=(xd*xd*vmax*0.5)/(Ueff*(1.0-fdrain)); + + deltal:=sqrt(kappa*xd*xd*(Vds-Vsat)+dcrit*dcrit)-dcrit; + end if; + + if deltal<=0.5*Leff then + C:=Leff/(Leff-deltal); + else + C:=4.0*deltal/Leff; + end if; + + else + C:=1.0; + end if; + + else + C:=1.0; + end if; + + It:=Vgst-Vpp*(1.0+B)*0.5; + Beta:=Beta*mobdeg; + Ids:=Beta*Vpp*It*C*fdrain*stfct; + else + -- Cutoff + Ids:=0.0; + end if; -- vgs >= vth + + if Cox /= 0.0 then + --Charges + if Vgs<=vth then + if Gamma /= 0.0 then + if Vgstos < -A then + Qg:=Cox*(Vgstos+A); -- Accumulation + else + Qg:=0.5*Gamma*Cox*(sqrt(4.0*(Vgstos+A)+Gamma*Gamma-Gamma)); + end if ; -- vgstos <-A + else-- Gamma = 0.0 + Qg:=0.0; + end if; -- gamma /= 0 + Qb:=-Qg; + Qc:=0.0; + else + -- depletion mode: + R:=(1.0+B)*Vpp*Vpp/(12.0*It); + Qg:=Cox*(Vgstos-Vpp*0.5+R); + Qc:=-Cox*(Vgst+(1.0+B)*(R-Vpp*0.5)); + Qb:=-(Qc+Qg); + end if; + + else + Qg:=0.0; + Qc:=0.0; + Qb:=0.0; + end if; -- cox /= 0 + + -- equations for charges (in a procedural we have assignments to + --quantitites): + Qcq := Qc; + Qgq := Qg; + Qbq := Qb; + + -- equations for currents: + Idq := channel*forward*Ids+channel*xqc*Qc'dot; + Igq := channel*Qg'dot; + Ibq := channel*Qb'dot; + Isq := -Idq - Igq - Ibq; + + end procedural; +end architecture amos; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test146.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test146.ams new file mode 100644 index 000000000..03319068f --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test146.ams @@ -0,0 +1,109 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test146.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test100.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- half wave Rectifier model ... +-- the test is done for checking the correct implementation +--of the simultaneous if statement.it checks +--nature declaration, terminal and quantity declarations. + + +---------------------------------------------------------------------- +-- T1 diode D T2 +-- o-----|>|-----o-------o The circuit comprises: +-- | | i) A diode . +-- ( ) >R=100ohms ii) A sinusoidal voltage source. +-- |Vs = 5sinwt > iii)A resistor R. +-- | > +-- |_____________|_______o +-- |gnd +-- ----- +---------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH; + FUNCTION SIN (X : real ) RETURN real; + FUNCTION EXP (X : real ) RETURN real; +END PACKAGE electricalSystem; + +---------------------------------------------------------------------- + +USE work.electricalSystem.all; + +ENTITY hwr IS +END hwr; + +ARCHITECTURE ahwr OF hwr IS + + terminal T1, T2 : electrical; + quantity VDiode across IDiode through T1 to T2; + quantity V2 across I2 through T2 to electrical'reference; + quantity VS across T1 to electrical'reference; + + CONSTANT saturation_current : real := 0.0000000000001; + CONSTANT Vt : real := 0.025; + + CONSTANT BV : real := 100.0; + CONSTANT neg_sat : real := -saturation_current; + +BEGIN + + --diode equations + if( vDiode >= (-1.0 * Vt)) USE + eq1: iDiode == saturation_current; + + ELSIF ((vDiode < (-3.0 * Vt)) AND (vDiode > -BV)) use + eq2: iDiode == neg_sat; + + ELSE + eq3: iDiode == neg_sat; + END USE ; + + eqn2: v2 == 100.0 * i2; + + eqn4: vs == 5.0 * sin(2.0 * 3.14 * 100000.0 * + real(time'pos(now)) * 1.0e-15 ); + +END ahwr ; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test147.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test147.ams new file mode 100644 index 000000000..59574f436 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test147.ams @@ -0,0 +1,75 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test147.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test147.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- this checks for the corect implementation of the 'dot'dot and negation +-- operator implementation for simple simulataeous statements +---------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity V1 across I1 through T1 to T2; +quantity V2: real; +quantity V3: real; +quantity VS across Isource through T1; + +begin + +e1: I1 == V1'dot*1e-15; +e2: V2 == VS'dot'dot; +e3: V3 == -VS'dot; +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test148.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test148.ams new file mode 100644 index 000000000..4445de2be --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test148.ams @@ -0,0 +1,77 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test148.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test148.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks for the correctness of the quantity, terminal, nature +-- and package declarations. the terminals are assigned as terminals. +-- a simple V-R circuit is considered. +----------------------------------------------------------------------- + +PACKAGE electricalsystem IS + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +-- SUBTYPE voltage IS real; +-- SUBTYPE current IS real; + +NATURE electrical IS real ACROSS real THROUGH ground reference; + +END PACKAGE electricalsystem; +use work.electricalsystem.all; + +ENTITY test IS + generic(ampl:real:=5.0); + PORT (TERMINAL p: electrical); +END ENTITY test; + +ARCHITECTURE sine OF test IS + constant freq: real:=10000.0; + QUANTITY v ACROSS i THROUGH p; + quantity vr across ir through p; +BEGIN +e1: v == ampl * sin(2.0 * 3.14159 * freq * real(time'pos(now))*1.0e-12); +e2: vr== ir*10.0; +END ARCHITECTURE sine; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test149.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test149.ams new file mode 100644 index 000000000..befafb72e --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test149.ams @@ -0,0 +1,113 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test149.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test149.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple resistor model... +-- the test is done for checking the correct implementation of the +-- componet declaration. The model consists of 2 resistor models which are +-- instantiated. + +package electricalSystem is + NATURE electrical IS real ACROSS real THROUGH Ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalsystem.all; + +entity test1 is + port (terminal P, N : electrical ); +end entity test1; + +architecture behav of test1 is + quantity Vt1 across It1 through P to N; +begin + res1 : Vt1 == It1 * 10.0 ; +end architecture behav; + +use work.electricalsystem.all; +entity test2 is + port (terminal P, N : electrical ); +end test2; + +architecture behav of test2 is + quantity Vt2 across It2 through P to N; +begin + res1 : Vt2 == It2 * 100.0 ; +end behav; + + +use work.electricalsystem.all; + +entity resistor_ckt is +end resistor_ckt; + +architecture ares_ckt of resistor_ckt is + + component test1 is + port (terminal P, N : electrical ); + end component; + + component test2 is + port (terminal P, N : electrical ); + end component; + + for all : test1 use entity work.test1(behav); + for all : test2 use entity work.test2(behav); + + terminal a,b,c,t1,t2 : electrical; + quantity vout across iout through t2 to electrical'reference; + quantity vs across a to electrical'reference; + +begin + e1 : test1 port map (P => a, N => b); + e2 : test2 port map (P => b, N => c); + e3 : vout == iout * 1200.0; + e4 : test1 port map (P => c, N => t1); + e5 : test1 port map (P => t1, N => t2); + source : vs == 5.0 * sin(2.0 * 3.1415 * 10000.0* real(time'pos(now)) * 1.0e-12); +end architecture ares_ckt; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test150.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test150.ams new file mode 100644 index 000000000..d159873e0 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test150.ams @@ -0,0 +1,75 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test150.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test150.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple RC model... +-- the test is done for checking the correct implementation +-- of the simple simultaneous equation statement with 'dot expression on +-- RHS. it checks nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity V1 across I1 through T1 to T2; +quantity V2 across I2 through T2; +quantity VS across T1; + +begin + +e1: V1 == I1*10.0; +e2: I2 == 1.0e-12*V2'dot; + +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test151.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test151.ams new file mode 100644 index 000000000..647d8eb53 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test151.ams @@ -0,0 +1,76 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test151.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test151.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple resistor model...2 resistors in parallel +-- the test is done for checking the correct implementation +-- of the simple simultaneous equation statement with multiple expressions +-- RHS. It checks nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1:electrical; +quantity V1 across I1 through T1 to electrical'reference; +quantity V2 across I2 through T1 to electrical'reference; +quantity VS across T1; +quantity I12 : real; +begin + +e1: V1 == I1*10.0; +e2: V2 == I2*10.0; +e3: I12 == I1+I2; + +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test152.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test152.ams new file mode 100644 index 000000000..a3a5fd9f1 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test152.ams @@ -0,0 +1,75 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test152.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test150.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple RC model... +-- the test is done for checking the correct implementation of the simple +-- simultaneous equation statement with 'dot expression on RHS. it checks +-- nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity V1 across I1 through T1 to T2; +quantity V2 across I2 through T2; +quantity VS across T1; + +begin + +e1: V1 == I1*10.0; +e2: I2 == V2'dot*1.0e-12; + +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test153.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test153.ams new file mode 100644 index 000000000..091e91fde --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test153.ams @@ -0,0 +1,79 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test153.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test100.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple model which has a voltage source. +-- The output voltage Vout is dependent on the value of vS at that point +-- of time. If the voltage is below Vref, the output is a 1 else output is +-- a 0. the test is done for checking the correct implementation of the +-- simple simultaneous if statement.it checks nature declaration, terminal +-- and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity VS across T1; +quantity Vout: real; +constant Vref:real:=5.0; +begin + +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +if (VS <= Vref) use +e1: Vout == 1.0; +else +e2: Vout == 0.0; +end use; + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test154.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test154.ams new file mode 100644 index 000000000..eb87aee45 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test154.ams @@ -0,0 +1,79 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test154.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test154.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple model which has a voltage source. +-- The output voltage Vout is dependent on the value of VS wrt Vref +-- If the voltage is below Vref, the output is a 0 else output is a 1. +-- the test is done for checking the correct implementation +--of the simple simultaneous if statement.it checks +--nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity VS across T1; +quantity Vout: real; +constant Vref:real:=5.0; +begin + +esource: VS == 5.0; + +if (VS<=Vref) use +e1: Vout == 1.0; +else +e2: Vout == 0.0; +end use; + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test155.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test155.ams new file mode 100644 index 000000000..56e0adfd7 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test155.ams @@ -0,0 +1,81 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test155.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test155.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple model which has a voltage source. +-- The output voltage Vout is dependent on the value of VS wrt Vref +-- If the voltage is above/below Vref, the output is a 0 else output is a 1. +-- the test is done for checking the correct implementation +-- of the simple simultaneous if statement with multiple if conditions.it +-- checks nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity VS across T1; +quantity Vout: real; +constant Vref:real:=5.0; +begin + +esource: VS == 5.0; + +if (VS<Vref) use +e1: Vout == 0.0; +elsif (VS=Vref) use +e2: Vout == 1.0; +else +e3: Vout == 0.0; +end use; + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test156.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test156.ams new file mode 100644 index 000000000..8837429f1 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test156.ams @@ -0,0 +1,108 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test156.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +-- check the implemetatio of ports and generics. + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity inv is + port ( + x : in bit; + xout : out bit); +end inv; + +architecture inverter of inv is +begin + + xout <= not x after 100ns ; + +end inverter ; + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND reference; + FUNCTION SIN (X : real ) RETURN real; + FUNCTION EXP (X : real ) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; + +entity resistor is + generic ( res : real := 10.0 ) ; + port (terminal P, N : electrical ); +end resistor; + +architecture behav of resistor is + quantity VPTON across IPTON through P to N; +begin + res1 : VPTON == IPTON * res ; +end behav; + +use work.electricalSystem.all; + +ENTITY circuit1 IS +END circuit1; + +ARCHITECTURE behavior OF circuit1 IS + component inv is + port ( + x : in bit; + xout : out bit); + end component ; + for all : inv use entity work.inv(inverter) ; + + component resistor is + generic ( res : real := 10.0 ) ; + port (terminal P, N : electrical ); + end component; + for all : resistor use entity work.resistor(behav); + + terminal n1,n2 : electrical; + QUANTITY vIn ACROSS iIn THROUGH n1 ; + + signal y:bit:='0'; + +BEGIN + + D2 : inv port map(x=>y, xout=>y); + + testbench:PROCESS + BEGIN + WAIT ON y; + END PROCESS; + + R1 : resistor generic map ( res => 500.0) port map (P => n1, N => n2); + R2 : resistor port map (P => n2, N => ground); + vsource: vIn == 5.0 * sin(2.0 * 3.14 * 100000.0 * real(time'pos(now)) * 1.0e-15); + +END ARCHITECTURE behavior; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test157.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test157.ams new file mode 100644 index 000000000..d73dadb62 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test157.ams @@ -0,0 +1,108 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test157.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +-- check the implemetatio of ports and generics. + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +--entity inv is +-- port ( +-- x : in bit; +-- xout : out bit); +--end inv; + +--architecture inverter of inv is +--begin + +-- xout <= not x after 100ns ; + +--end inverter ; + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND reference; + FUNCTION SIN (X : real ) RETURN real; + FUNCTION EXP (X : real ) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; + +entity resistor is + generic ( res : real := 10.0 ) ; + port (terminal P, N : electrical ); +end resistor; + +architecture behav of resistor is + quantity VPTON across IPTON through P to N; +begin + res1 : VPTON == IPTON * res ; +end behav; + +use work.electricalSystem.all; + +ENTITY circuit1 IS +END circuit1; + +ARCHITECTURE behavior OF circuit1 IS +-- component inv is +-- port ( +-- x : in bit; +-- xout : out bit); +-- end component ; +-- for all : inv use entity work.inv(inverter) ; + + component resistor is + generic ( res : real := 10.0 ) ; + port (terminal P, N : electrical ); + end component; + for all : resistor use entity work.resistor(behav); + + terminal n1,n2 : electrical; + QUANTITY vIn ACROSS iIn THROUGH n1 ; + +-- signal y:bit:='0'; + +BEGIN + +-- D2 : inv port map(x=>y, xout=>y); + +-- testbench:PROCESS +-- BEGIN +-- WAIT ON y; +-- END PROCESS; + + R1 : resistor generic map ( res => 500.0) port map (P => n1, N => n2); + R2 : resistor port map (P => n2, N => ground); + vsource: vIn == 5.0 * sin(2.0 * 3.14 * 100000.0 * real(time'pos(now)) * 1.0e-15); + +END ARCHITECTURE behavior; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test158.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test158.ams new file mode 100644 index 000000000..0f80dc695 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test158.ams @@ -0,0 +1,98 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test158.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test134.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : June 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- this is a test to check the corretness of the implemntation of the break +-- statement and also the use of quantity port of type voltage. +-- this is a vco model which first sets the initial condition +-- using a break statement. Then again, a break statement is applied to keep +-- the phase within 0-2pi. Thr output voltage eqn is obtained as vout and the +-- phase eqn as phase'dot. +-- LRM ref: 8.14, 4.3.2. +---------------------------------------------------------------------- +PACKAGE electricalSystem IS + -- SUBTYPE voltage is real; + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; + +entity vco is + generic( + fc: real := 1.0e6; -- VCO frequency at Vc + df: real := 0.5e6; -- [Hz/V], frequency characteristic slope + Vc: voltage := 0.0 -- centre frequency input voltage + ); + port( quantity Vin: in real; + terminal OutTerminal: electrical); +end entity VCO; + +architecture avco of vco is + constant TwoPi: real := 6.283118530718; -- 2pi + + quantity Phase : real; + + -- define a branch for the output voltage source + + quantity Vout across Iout through OutTerminal to electrical'reference; + +begin + -- use break to set the phase initial condition + break Phase => 0.0; + + -- another break statement keeps the phase within 0.. 2pi + break Phase => Phase mod TwoPi on Phase'above(TwoPi); + + -- phase equation + Phase'dot == TwoPi*realmax(0.5E6, fc+(Vin-Vc)*df); + + -- output voltage source equation + Vout == 2.5*(1.0+sin(Phase)); + +end architecture avco; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test161.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test161.ams new file mode 100644 index 000000000..f63c3803a --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test161.ams @@ -0,0 +1,75 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test161.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test150.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple RC model... +-- the test is done for checking the correct implementation +-- of the simple simultaneous equation statement with 'dot expression on +-- RHS. it checks nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity V1 across I1 through T1 to T2; +quantity V2 across I2 through T2; +quantity VS across T1; + +begin + +e1: V1 == I1*10.0; +e2: V2 == I1'integ/1.0e-12; + +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test162.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test162.ams new file mode 100644 index 000000000..dbc7b3bac --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test162.ams @@ -0,0 +1,74 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test162.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test147.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- this checks for the corect implementation of the 'dot'dot and negation +-- operator implementation for simple simulataeous statements +---------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity V1 across I1 through T1 to T2; +quantity V2: real; +quantity i2 :real; +quantity VS across Isource through T1; + +begin + +e1: I1 == V1'dot*1.0e-15; +e2: V2 == V1'dot; +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test163.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test163.ams new file mode 100644 index 000000000..3b26a8aac --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test163.ams @@ -0,0 +1,81 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test163.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test162.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple rc model...with 2 res in parallel connected thru a capacitor +-- -------------||----- +-- | | +-- | R | R +-- -------------------- +-- the test is done for checking the correct implementation +--of the simple simultaneous equation statement.it checks +--nature declaration, terminal, 'dot and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity VR1 across IR1 through T1; +quantity VC across IC through T1 to T2; +quantity VR2 across IR2 through T2; +quantity VS across T1; + +begin + +e1: VR1 == IR1*100.0; +e2: IC == VC'dot *1.0e-12; +e3: VR2 == IR2*10.0; + +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test164.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test164.ams new file mode 100644 index 000000000..17a077817 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test164.ams @@ -0,0 +1,81 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test164.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test164.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple rc model...with 2 res in parallel connected thru a capacitor +-- -------------||----- +-- | | +-- | R | R +-- -------------------- +-- the test is done for checking the correct implementation +-- of the simple simultaneous equation statement.it checks +-- nature declaration, terminal, 'dot, 'integ and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity VR1 across IR1 through T1; +quantity VC across IC through T1 to T2; +quantity VR2 across IR2 through T2; +quantity VS across T1; + +begin + +e1: VR1 == IR1*100.0; +e2: IC == VC'dot *1.0e-12; +e3: VR2 == IR2*10.0; +e4: VC == IC'integ/1.0e15 +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test165.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test165.ams new file mode 100644 index 000000000..cf085096d --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test165.ams @@ -0,0 +1,80 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test165.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test164.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple rl model... +-- -----^^^------------- +-- R | > +-- | L > R +-- -------------------- +-- the test is done for checking the correct implementation +-- of the simple simultaneous equation statement.it checks +-- nature declaration, terminal, 'dot, and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity VR1 across IR1 through T1 to T2; +quantity VL across IL through T2; +quantity VR2 across IR2 through T2; +quantity VS across T1; + +begin + +e1: VR1 == IR1*10.0; +e2: VL == IL'dot *1.0; +e3: VR2 == IR2*10.0; +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test166.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test166.ams new file mode 100644 index 000000000..92dc6af26 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test166.ams @@ -0,0 +1,80 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test166.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test166.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple rl model... +-- -----^^^------------- +-- R | > +-- | L > R +-- -------------------- +-- the test is done for checking the correct implementation +-- of the simple simultaneous equation statement.it checks +-- nature declaration, terminal, 'dot,'integ and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity VR1 across IR1 through T1 to T2; +quantity VL across IL through T2; +quantity VR2 across IR2 through T2; +quantity VS across T1; + +begin + +e1: VR1 == IR1*10.0; +e2: VL == IL'dot *1.0; +e3: VR2 == IR2*10.0; +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); +e4: IL== 1.0* VL'integ; +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test167.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test167.ams new file mode 100644 index 000000000..35849f231 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test167.ams @@ -0,0 +1,81 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test167.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test167.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- An RC model... +-- the test is done for checking the correct implementation +-- of the simple simultaneous equation statement.it checks +-- nature declaration, terminal, 'dot, 'integ and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2, T3, T4:electrical; +quantity V1 across I1 through T1 to T2; +quantity V2 across I2 through T2 to T3; +quantity VC across IC through T3; +quantity VC1 across IC1 through T2 to T4; +quantity V3 across I3 through T4; +quantity VS across T1; + +begin + +e1: V1 == I1*1.0; +e2: V2 == I2*1.0; +e3: V3 == I3*10.0; +e4: IC == VC'dot*1.0e-12; +e5: IC1 == VC1'dot*1.0e-12; + +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test168.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test168.ams new file mode 100644 index 000000000..c78d544b6 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test168.ams @@ -0,0 +1,81 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test168.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test168.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- An RC model... +-- the test is done for checking the correct implementation +-- of the simple simultaneous equation statement.it checks +-- nature declaration, terminal, 'dot, 'integ and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2, T3, T4:electrical; +quantity V1 across I1 through T1 to T2; +quantity V2 across I2 through T2 to T3; +quantity VC across IC through T3; +quantity VC1 across IC1 through T2 to T4; +quantity V3 across I3 through T4; +quantity VS across T1; + +begin + +e1: V1 == I1*1.0; +e2: V2 == I2*1.0; +e3: V3 == I3*10.0; +e4: VC == IC'integ*1.0e12; +e5: VC1 == IC1'integ*1.0e12; + +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test169.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test169.ams new file mode 100644 index 000000000..c0b15e18f --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test169.ams @@ -0,0 +1,143 @@ + +-- Copyright (C) 1999-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test169.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +-------------------------------------------------------------------- +-- Ebers-moll Model for a transistor -- +-- VHDL-AMS Implementation -- +-- Developed at the Distributed Processing Lab at the University -- +-- of Cincinnati -- +-- by VishwaShanth Kasula on May 10, 1999 -- +-------------------------------------------------------------------- +-- Circuit Topology -- +-- BJT Ebers-Moll static model +-- Testbench Ckt to evaluate the DC operatioing point of an npn BJT, +-- Sedra smith page no. 152, fig 4.9 +-------------------------------------------------------------------- + +-- Three regions are simulated +-- Active region, vbb = 4.0 V +-- Saturation region, vbb = 6.0 V +-- Cutoff region, vbb = 0.0; + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalsystem.all; + +entity bjt_npn is + generic(isat : real := 1.0e-16; -- Saturation Current + bf : real := 100.0; -- Ideal maximus forward current + br : real := 1.0; -- ideal maximum reverse current + rb : real := 1.0e-5; -- Base resistance + rc : real := 1.0e-5; -- collector resistance + re : real := 1.0e-5; -- emmiter resistance + vaf : real := 100.0); -- Forward Early Voltage + port(terminal e,b,c : electrical); +end bjt_npn; + +architecture structure of bjt_npn is + terminal b1, c1, e1 : electrical; + quantity vbo across ib through b to b1; + quantity vco across ic through c to c1; + quantity veo across ie through e to e1; + quantity vct across Ict through c1 to e1;--current source + quantity vbe across ibe through b1 to e1; + quantity vbc across ibc through b1 to c1; + quantity vce : real := 1.0; -- used to calculate VCE + constant gmin : real := 1.0e-12; -- condutsnce in parallel with every pn junction + constant vt : real := 0.02589; -- thermal voltage + +begin + brk : break vbe => 1.0, vbc => -1.0; + + diodecond1 : if(vbe > -5.0*vt) use + diodebef : ibe == ((isat*(exp(vbe/vt) - 1.0)) + (gmin*vbe))/bf; + elsif (vbe <= -5.0*vt ) use + diodeber: ibe == ((-1.0*isat) + (gmin*vbe))/bf; + end use; + diodecond2 : if(vbc > -5.0*vt) use + diodebcf : ibc == ((isat*(exp(vbc/vt) - 1.0)) + (gmin*vbc))/br; + elsif(vbc <= -5.0*vt) use + diodebcr : ibc == ((-1.0*isat) + (gmin*vbc))/br; + end use; + bres : vbo == ib * 1.0e-6; + cres : vco == ic * 1.0e-6; + eres : veo == ie * 1.0e-6; + kcl_eqn : ie == -1.0*(ib + ic); + vcevolt : vce == vbe - vbc; + ictdep : Ict == ((Ibe*bf) - (Ibc*br)) * (1.0 -(vbc/vaf)); + +end architecture structure; + + +--***************************************************** +--TEST BENCH +use std.textio.all; +use work.electricalsystem.all; + +entity bjt_testbench is +end bjt_testbench; + +architecture structure of bjt_testbench is + terminal t1, t2, t3, t4 : electrical ; + component bjt_npn_comp + generic(isat : real := 1.0e-16; -- Saturation Current + bf : real := 100.0; -- Ideal maximus forward current + br : real := 1.0; -- ideal maximum reverse current + rb : real := 1.0e-5; -- Base resistance + rc : real := 1.0e-5; -- collector resistance + re : real := 1.0e-5; -- emmiter resistance + vaf : real := 100.0); -- Forward Early Voltage + port(terminal e,b,c : electrical); + end component; + for all : bjt_npn_comp use entity work.bjt_npn(structure); + + quantity vcc across icc through t1 to electrical'reference; + quantity vrc across irc through t1 to t2; + quantity vbb across ibb through t3 to electrical'reference; + quantity vre across ire through t4 to electrical'reference; + +begin + + bjt : bjt_npn_comp + generic map (isat => 1.8104e-15, vaf => 100.0) + port map(t4,t3,t2); + emres : vre == ire * 3.3e3; + ccurr : vcc == 10.0; + ecurr : vbb == 6.0; + cores : vrc == irc * 4.7e3; + +end architecture structure; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test170.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test170.ams new file mode 100644 index 000000000..dff75159a --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test170.ams @@ -0,0 +1,86 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test170.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test106.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple resistor model... +-- the test is done for checking the correct implementation +-- of the simple simultaneous equation statement.it checks +-- nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2, T3, T4,T5,T6:electrical; +quantity VRgen across IRgen through T1 to T2; +quantity VLgen across ILgen through T2 to T3; +quantity VRin across IRin through T3; +quantity VR1 across IR1 through T4 to T5; +quantity VR1A across IR1A through T4 to T6; +quantity VC1A across IC1A through T6 to T5; +quantity VC1 across IC1 through T5; +quantity VS across T1; +constant C1: real:=3.5e-3; +constant C1A: real:=0.3e-3; +begin + +e1: VRgen == IRgen*10.0; +e2: VLgen == 0.5*ILgen'dot; +e3: VRin == IRin*500.0; +e4: VR1 == IR1*1.0; +e5: VR1A == IR1A*0.2; +e6: VC1 == C1 /IC1'integ; +e7: VC1A == C1A/IC1A'integ; + +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test171.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test171.ams new file mode 100644 index 000000000..3d0dd76c9 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test171.ams @@ -0,0 +1,96 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test171.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test171.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test is done for checking the correct implementation +-- of the simultaneous if equation statement.it checks +-- nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2, T3 :electrical; +quantity VC1 across IC1 through T1 to T2; +quantity VC2 across IC2 through T3; +quantity VD1 across ID1 through T2; +quantity VD2 across ID2 through T2 to T3; +quantity VS across T1; +constant BV: real:=100.0; +constant satcur: real:=1.0e-12; +constant negsatcur: real:= -1.0*satcur; +constant VT: real:=0.025; +constant C1: real:= 1.0e-12; +constant C2: real:= 1.0e-12; +begin + +e1: IC1 == C1 * VC1'dot; +e2: IC2 == C2*VC2'dot; +diode1: if (VD1>=(-3.0*VT)) use + ID1 == satcur*(exp(VD1/VT)-1.0); + elsif (VD1 < (-3.0*VT) and (VD1 >-BV)) use + ID1==negsatcur; + else + ID1 == negsatcur * (exp(-(BV+ VD1/VT)-1)+satcur); + end use; + +diode2: if (VD2>=(-3.0*VT)) use + ID2 == satcur*(exp(VD2/VT)-1.0); + elsif (VD2 < (-3.0*VT) and (VD2 >-BV)) use + ID2==negsatcur; + else + ID2 == negsatcur * (exp(-(BV+ VD2/VT)-1)+satcur); + end use; + +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test172.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test172.ams new file mode 100644 index 000000000..123b9dd29 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test172.ams @@ -0,0 +1,98 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test172.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test172.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test is done for checking the correct implementation +-- of the simultaneous if equation statement.it checks +-- nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +port (input: in bit; + output: out bit); +end entity; + +architecture atest of test is +terminal t1, t2: electrical; +quantity v1 across i1 through t1 to t2; +quantity v2 across t2; +begin + +e1: v1== 1.0; +e2: v2==0.0; + + if (v1==1.0) use + output <= '1'; + else + output <='0'; + end use; + + if (v2==2.0) use + output <='0'; + else + output <='1'; + end use; +end architecture atest; +use work.electricalSystem.all; +--entity tb is +--port (tinput: in bit; +-- toutput: out bit); +--end entity; +--architecture atb of tb is +--terminal tt1, tt2: electrical; +--quantity tv1 across ti1 through tt1 to tt2; +--quantity tv2 across tt2; +--begin + +--tv1==1.0; +--tv2==0.0; + +--end architecture atb; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test173.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test173.ams new file mode 100644 index 000000000..c43afe846 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test173.ams @@ -0,0 +1,77 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test173.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test173.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test is done for checking the correct implementation +-- of the simultaneous if equation statement.it checks +-- nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal t1, t2: electrical; +quantity v1 across i1 through t1 to t2; +quantity v2 across t2; + +begin +e1: v1== 1.0; +e2: v2==0.0; + + if (v1==1.0) use + output <= '1'; + end use; + + if (v2==2.0) use + output <='1'; + end use; +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test174.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test174.ams new file mode 100644 index 000000000..4bf8c01ba --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test174.ams @@ -0,0 +1,89 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test174.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test174.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple resistor model... +-- the test is done for checking the correct implementation +-- of the simultaneous case statement.it checks +-- nature declaration, terminal and quantity declarations + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH Ground reference ; + FUNCTION SIN (X : real ) RETURN real; + FUNCTION EXP (X : real ) RETURN real; +END PACKAGE electricalSystem; + + +USE work.electricalSystem.all; + +ENTITY simcase IS +END simcase; + +ARCHITECTURE asimcase OF simcase IS + + terminal T1, T2 : electrical; + + quantity v1 across i1 through T1 ; + quantity v2 across i2 through T1 to T2; + quantity v3 across i3 through T2 ; + +BEGIN + + eqn1 : v1 == 1.0; + +c1: case (v1*2.0) use + + when (2.0) use + v2 == i2 * 100.0; + v3 == i3 * 100.0; + when (6.0) use + v2 == i2 * 200.0; + v3 == i3 * 200.0; + when (10.0) use + v2 == i2 * 300.0; + v3 == i3 * 300.0; + end case c1; + +END asimcase ; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test175.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test175.ams new file mode 100644 index 000000000..544527dc2 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test175.ams @@ -0,0 +1,87 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test175.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test175.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test is done for checking the correct implementation +--of the simultaneous case statement.it checks +--nature declaration, terminal and quantity declarations + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH Ground reference ; + FUNCTION SIN (X : real ) RETURN real; + FUNCTION EXP (X : real ) RETURN real; +END PACKAGE electricalSystem; + +USE work.electricalSystem.all; + +ENTITY simcase IS +END simcase; + +ARCHITECTURE asimcase OF simcase IS + + terminal T1, T2 : electrical; + + quantity v1 across i1 through T1 ; + quantity v2 across i2 through T1 to T2; + quantity v3 across i3 through T2 ; + +BEGIN + + eqn1 : v1 == 1.0; + eqn2 : v2 == 2.0; +c1: case (v1*2.0) use + + when (2.0) use + if (v2==2.0) use + v2 == i2 * 100.0; + else + v2 ==i2*10.0; + end use; + when (6.0) use + v2 == i2 * 200.0; + when (10.0) use + v2 == i2 * 300.0; + end case c1; +END asimcase ; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test176.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test176.ams new file mode 100644 index 000000000..dd7f81126 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test176.ams @@ -0,0 +1,80 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test176.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test176.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test is done for checking the correct implementation +-- of the simultaneous null statement.it checks +-- nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity V1 across I1 through T1 to T2; +quantity V2 across I2 through T2; +quantity V3 across I3 through T2; +quantity VS across T1; + +begin + + V1==1.0; + if (V1<=1.0) use + NULL; + else + V2 == V1*1.0; + end use; + + +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test177.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test177.ams new file mode 100644 index 000000000..75b230ab9 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test177.ams @@ -0,0 +1,82 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test177.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test177.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test is done for checking the correct implementation +-- of the 'path_name attribute. + +--PACKAGE electricalSystem IS +-- NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; +-- FUNCTION SIN (X : real ) RETURN real; +-- FUNCTION EXP (X : real ) RETURN real; +--END PACKAGE electricalSystem; + +--USE work.electricalSystem.all; + +ENTITY Bottom IS +generic(GBottom:integer); +--port (PBottom:integer); +constant SBottom:integer:=4; +END Bottom; + +ARCHITECTURE BottomArch OF Bottom IS +begin + ProcessBottom: process + variable V:integer; + begin + if GBottom=4 then + assert + V'Path_Name= ":top:b1:b2:g1(4):b3:11:processbottom:v"; + -- and GBottom'Path_Name=":top:b1:b2:g1(4):b3:11:gbottom"; + elsif GBottom=1 then + assert + V'Path_Name= ":top:12:processbottom:v"; + else + assert + GBottom'Path_Name="top:12:gbottom"; + end if; + wait; + end process ProcessBottom; +end architecture BottomArch; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test178.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test178.ams new file mode 100644 index 000000000..a3f8ea63a --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test178.ams @@ -0,0 +1,80 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test178.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test178.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test is done for checking the correct implementation +-- of the simultaneous procedural equation statement.it checks +-- nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN (X : real ) RETURN real; + FUNCTION EXP (X : real ) RETURN real; +END PACKAGE electricalSystem; + + +USE work.electricalSystem.all; + +ENTITY simproc IS +END simproc; + +ARCHITECTURE asimproc OF simproc IS + + terminal T1: electrical; + quantity vd across id through T1; + quantity charge: real; + constant vt: real:= 1.0; +BEGIN + eq1: vd==1.0; + proc1: procedural is + variable vres:real; + constant tau:real:=1.0; + variable ares: real; + begin + e1: ares:=vd*1.0; + e3: vres:=vt; + end procedural; + +END asimproc ; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test179.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test179.ams new file mode 100644 index 000000000..1249b0680 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test179.ams @@ -0,0 +1,86 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test179.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test179.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple resistor model... +-- the test is done for checking the correct implementation +-- 'instance_name attribute + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN (X : real ) RETURN real; + FUNCTION EXP (X : real ) RETURN real; +END PACKAGE electricalSystem; + + +USE work.electricalSystem.all; + +ENTITY Bottom IS +generic(GBottom:integer); +port (PBottom:integer); +constant SBottom:integer:=4; +END Bottom; + +ARCHITECTURE BottomArch OF Bottom IS +begin +-- SBottom :=4; + ProcessBottom: process + variable V:integer; + begin + if GBottom=4 then + assert + V'Instance_Name=":top(top):b1:b2:g1(4):b3:11@bottom(bottomarch):processbottom:v" + and + GBottom'Instance_Name=":top(top):b1:b2:g1(4):b3:11@bottom(bottomarch):gbottom"; + elsif GBottom=1 then + assert + V'Instance_Name=":top(top):12@bottom(bottomarch):processbottom:v"; + else + assert + GBottom'Instance_Name= ":top(top):12@bottom(bottomarch):gbottom"; + end if; + wait; + end process ProcessBottom; +end architecture BottomArch; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test180.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test180.ams new file mode 100644 index 000000000..feae7a692 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test180.ams @@ -0,0 +1,70 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test180.ams,v 1.2 2003-08-05 15:14:24 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test180.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test is done for checking the correct implementation +-- of the break statement.it checks simple break and break on +-- codition. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity VCO is +port(terminal InTerminal,OutTerminal: electrical); +end VCO; + +architecture PhaseIntegrator of VCO is + quantity Vin across Iin through InTerminal to OutTerminal; + constant TwoPi: real := 6.283118530718; -- 2pi + quantity Phase : real; -- phase is a free quantity: + quantity Vout across Iout through OutTerminal; +begin + break Phase => TwoPi; + Vout == 2.5*(sin(Phase)); -- output statement +end PhaseIntegrator; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test181.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test181.ams new file mode 100644 index 000000000..873a1f597 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test181.ams @@ -0,0 +1,72 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test181.ams,v 1.2 2003-08-05 15:14:24 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test181.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test is done for checking the correct implementation +-- of the break statement.it checks simple break and break on +-- codition. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +entity VCO is + port(terminal InTerminal,OutTerminal: electrical); +end VCO; + +architecture PhaseIntegrator of VCO is + quantity Vin across Iin through InTerminal to OutTerminal; + constant TwoPi: real := 6.283118530718; -- 2pi + quantity Phase : real; -- phase is a free quantity: + quantity Vout across Iout through OutTerminal; +begin + break Phase => TwoPi; + -- break allows to define the initial conditions + break Phase => 0.0 on Phase'above(TwoPi); + Vout == 2.5*(sin(Phase)); -- output statement +end PhaseIntegrator; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test182.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test182.ams new file mode 100644 index 000000000..d945f0172 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test182.ams @@ -0,0 +1,72 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test182.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test182.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test is done for checking the correct implementation +-- of the 'above attribute. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN (X : real ) RETURN real; + FUNCTION EXP (X : real ) RETURN real; +END PACKAGE electricalSystem; + + +USE work.electricalSystem.all; + +entity test is +port(signal vout:out boolean); +end entity; + +architecture atest of test is + +terminal T1: electrical; +quantity vin across iin through T1; +--constant vt: real:=3.0; +begin +e2 : vout <= vin'above(0.0); +e1: vin == 5.0 * sin(2.0 *3.141592 *100000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test183.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test183.ams new file mode 100644 index 000000000..9cd07f34b --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test183.ams @@ -0,0 +1,59 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test183.ams,v 1.2 2003-08-05 15:14:24 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +-- this model tests for the correst implementation of the 'above +-- statement. +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground REFERENCE; + FUNCTION SIN(X : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalsystem.all; + +entity product is +generic(bound:real:=1.0); +port( + quantity out1:real); +end product; + +architecture pro of product is +constant in1:real:=10.0; +constant in2:real:=1.0; +signal outofbound:out boolean; + +begin + outofbound<=true; + out1== in1*in2; + outofbound<=out1'above(bound); + +end pro; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test184.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test184.ams new file mode 100644 index 000000000..ad706e0e2 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test184.ams @@ -0,0 +1,110 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test184.ams,v 1.2 2003-08-05 15:14:24 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +--------------------------------------------------------------------- +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test100.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- half wave Rectifier model ... +-- the test is done for checking the correct implementation +-- of the simultaneous if statement.it checks +-- nature declaration, terminal and quantity declarations. + +---------------------------------------------------------------------- +-- T1 diode D T2 +-- o-----|>|-----o-------o The circuit comprises: +-- | | i) A diode . +-- ( ) >R=100ohms ii) A sinusoidal voltage source. +-- |Vs = 5sinwt > iii)A resistor R. +-- | > +-- |_____________|_______o +-- |gnd +-- ----- +---------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground REFERENCE; + FUNCTION SIN (X : real ) RETURN real; + FUNCTION EXP (X : real ) RETURN real; +END PACKAGE electricalSystem; + +---------------------------------------------------------------------- + +USE work.electricalSystem.all; + +ENTITY hwr IS +END hwr; + +ARCHITECTURE ahwr OF hwr IS + + terminal T1, T2 : electrical; + quantity VDiode across IDiode through T1 to T2; + quantity V2 across I2 through T2 ; + quantity VS across T1 ; + + CONSTANT saturation_current : real := 0.0000000000001; + CONSTANT Vt : real := 0.025; + + CONSTANT BV : real := 100.0; + CONSTANT neg_sat : real := -saturation_current; + +BEGIN + + --diode equations + if( vDiode >= (-1.0 * Vt)) USE + eq1: iDiode == saturation_current * (exp(vDiode/Vt) - 1.0); + + ELSIF ((vDiode < (-3.0 * Vt)) AND (vDiode > -BV)) use + eq2: iDiode == neg_sat; + + ELSE + eq3: iDiode == neg_sat * (exp(-(BV + vDiode)/Vt) - 1.0 + + saturation_current); + END USE ; + + eqn2: v2 == 100.0 * i2; + + eqn4: vs == 5.0 * sin(2.0 * 3.14 * 100000.0 * + real(time'pos(now)) * 1.0e-15 ); + +END ahwr ; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test185.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test185.ams new file mode 100644 index 000000000..785249934 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test185.ams @@ -0,0 +1,56 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test185.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN (X : real ) RETURN real; + FUNCTION EXP (X : real ) RETURN real; +END PACKAGE electricalSystem; + +USE work.electricalSystem.all; + +ENTITY simcase IS +END simcase; + +ARCHITECTURE asimcase OF simcase IS + + terminal T1: electrical; + + quantity v1 across i1 through T1 ; + +BEGIN + eq1: v1==1.0; + if (v1<=1.0) use + e1: null; + end use; +END asimcase ; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/resistor_models/ccvs.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/resistor_models/ccvs.ams new file mode 100644 index 000000000..65ba60b3e --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/resistor_models/ccvs.ams @@ -0,0 +1,71 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: ccvs.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH Ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalsystem.all; + +--entity declaration + +ENTITY RLC IS + +END RLC; + +--architecture declaration + +ARCHITECTURE behavior OF RLC IS + + terminal n1, n2 : electrical; + quantity is1 through n1; + quantity vr1 across ir1 through n1; + quantity vr2 across ir2 through n2; + quantity vs1 across n2; + constant r1 : REAL := 20.0; + constant r2 : REAL := 10.0; + constant r3 : REAL := 5.0; + +BEGIN + +res1 : vr1 == ir1 * r1; +res2 : vs1 == ir1 * r2; +res3 : vr2 == ir2 * r3; +vsrc : is1 == 5.0 * sin(2.0 * 3.1415 * 10.0 --sine source + * real(time'pos(now)) * 1.0e-15); + +END architecture behavior; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/resistor_models/parallel.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/resistor_models/parallel.ams new file mode 100644 index 000000000..0fbe03138 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/resistor_models/parallel.ams @@ -0,0 +1,72 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: parallel.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH Ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalsystem.all; + +--entity declaration + +ENTITY RLC IS + +END RLC; + +--architecture declaration + +ARCHITECTURE behavior OF RLC IS + + terminal n1 : electrical; + + quantity vr1 across ir1 through n1 ; + quantity vr2 across ir2 through n1; + quantity vr3 across ir3 through n1; + quantity vs across n1; + constant r1 : REAL := 10.0; + constant r2 : REAL := 20.0; + constant r3 : REAL := 50.0; + +BEGIN + +res1 : vr1 == ir1 * r1; +res2 : vr2 == ir2 * r2; +res3 : vr3 == ir3 * r3; +vsrc : vs == 5.0 * sin(2.0 * 3.1415 * 10.0 --sine source + * real(time'pos(now)) * 1.0e-9); + +END architecture behavior; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/resistor_models/series-parallel.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/resistor_models/series-parallel.ams new file mode 100644 index 000000000..a5f537f31 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/resistor_models/series-parallel.ams @@ -0,0 +1,75 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: series-parallel.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH Ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalsystem.all; + +--entity declaration + +ENTITY RLC IS + +END RLC; + +--architecture declaration + +ARCHITECTURE behavior OF RLC IS + + terminal n1, n2 : electrical; + + quantity vr1 across ir1 through n1 to n2; + + quantity vr2 across ir2 through n2 to electrical'reference; + --supposedly this works !!!! + --quantity vr2 across ir2 through n2 to ground; + quantity vr3 across ir3 through n2; + quantity vs across n1; + constant r1 : REAL := 20.0; + constant r2 : REAL := 10.0; + constant r3 : REAL := 5.0; + +BEGIN + +res1 : vr1 == ir1 * r1; +res2 : vr2 == ir2 * r2; +res3 : vr3 == ir3 * r3; +vsrc : vs == 5.0 * sin(2.0 * 3.1415 * 10.0 --sine source + * real(time'pos(now)) * 1.0e-9); + +END architecture behavior; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/resistor_models/series.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/resistor_models/series.ams new file mode 100644 index 000000000..9dbb7626e --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/resistor_models/series.ams @@ -0,0 +1,73 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: series.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH Ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalsystem.all; + +--entity declaration + +ENTITY RLC IS + +END RLC; + +--architecture declaration + +ARCHITECTURE behavior OF RLC IS + + terminal n1, n2, n3 : electrical; + + quantity vr1 across ir1 through n1 to n2; + quantity vr2 across ir2 through n2 to n3; + quantity vr3 across ir3 through n3; + quantity vs across n1; + constant r1 : REAL := 10.0; + constant r2 : REAL := 20.0; + constant r3 : REAL := 50.0; + +BEGIN + +res1 : vr1 == ir1 * r1; +res2 : vr2 == ir2 * r2; +res3 : vr3 == ir3 * r3; +cons : ir1 == ir2; +vsrc : vs == 5.0 * sin(2.0 * 3.1415 * 10.0 --sine source + * real(time'pos(now)) * 1.0e-9); + +END architecture behavior; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/resistor_models/vccs.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/resistor_models/vccs.ams new file mode 100644 index 000000000..3c2cc9a00 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/resistor_models/vccs.ams @@ -0,0 +1,72 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: vccs.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH Ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalsystem.all; + +--entity declaration + +ENTITY RLC IS + +END RLC; + +--architecture declaration + +ARCHITECTURE behavior OF RLC IS + +constant R1: real :=20.0; +constant R2: real :=10.0; +constant R3: real :=5.0; +terminal T1,T2,T3:electrical; +quantity Vs1 across T1; +quantity Is1 through T2; +quantity Vr1 across Ir1 through T2 to T3; +quantity Vr2 across Ir2 through T3; + +BEGIN + + +res1 : vr1 == ir1 * r1; +res2 : vr2 == ir2 * r2; +res3 : is1 == vs1 * r3; +vsrc : vs1 == 5.0 * sin(2.0 * 3.1415 * 10.0 --sine source + * real(time'pos(now)) * 1.0e-15); + +END architecture behavior; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/resistor_models/vcvs.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/resistor_models/vcvs.ams new file mode 100644 index 000000000..24ee97232 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/resistor_models/vcvs.ams @@ -0,0 +1,68 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: vcvs.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH Ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalsystem.all; + +--entity declaration + +ENTITY RLC IS + +END RLC; + +--architecture declaration + +ARCHITECTURE behavior OF RLC IS + +constant R1: real :=20.0; +constant R3: real :=10.0; +terminal T1,T2,T3:electrical; +quantity Vr2 across T2; +quantity Vr3 across Ir3 through T2; +quantity Vs across T1; + +BEGIN + +vol1 : Vr2 == Vs * r1; +res3 : vr3 == ir3 * r3; +vsrc : Vs == 5.0 * sin(2.0 * 3.1415 * 10.0 --sine source + * real(time'pos(now)) * 1.0e-15); + +END architecture behavior; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/clipper.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/clipper.ams new file mode 100644 index 000000000..dac895383 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/clipper.ams @@ -0,0 +1,100 @@ + +-- Copyright (C) 1998-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: clipper.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +------------------------------------------------------------------------ +-- Title : Single diode clipper circuit +-- Project : Mixed signal simulation +------------------------------------------------------------------------ +-- File : diode_clipper1.vhd +-- Author(s) : Vasudevan Shanmugasundaram(vasu@ececs.uc.edu) +-- Created : jan 16 1998 +------------------------------------------------------------------------ +-- Description : +-- Behavioral description of a single diode clipper circuit. +------------------------------------------------------------------------ +-- circuit diagram for the diode clipper: +-- the circuit comprises: +-- o______|l______o____|>|______o i) a diode D. +-- | |l | diode D ii) a constant voltage source vd. +-- | const | iii)a sinusoidal voltage source. +-- ( ) Vsource > iv) a resistor R. +-- |Vs >R +-- | > +-- o______________|_____________o +-- +------------------------------------------------------------------------ + +--package definition +PACKAGE electricalSystem IS +NATURE electrical IS real ACROSS real THROUGH ground reference; +FUNCTION SIN (X : real ) RETURN real; +FUNCTION EXP (X : real ) RETURN real; +END PACKAGE electricalSystem; +------------------------------------------------------------------------------- + +USE work.electricalSystem.all; + +ENTITY diode_clipper IS +END diode_clipper; + +ARCHITECTURE behav OF diode_clipper IS + --terminal declarations + terminal t1, t2, t3 : electrical; + --quantity declarations + quantity vDiode across iDiode through t1 TO t2; + quantity v2 across i2 through t2 TO t3; + quantity vd across electrical'reference TO t1; + quantity vs across electrical'reference TO t3; + --constants + CONSTANT saturation_current : real := 0.0000000000001; + CONSTANT Vt : real := 0.025; + CONSTANT BV : real := 100.0; + CONSTANT neg_sat : real := -saturation_current; + +BEGIN -- behav + if( vDiode >= (-1.0 * Vt)) USE --diode equations + eqn1_1: iDiode == saturation_current * ( exp(vDiode/Vt) - 1.0 ); + ELSIF ((vDiode < (-3.0 * Vt)) AND (vDiode > -BV)) use + eqn1_2: iDiode == neg_sat; + ELSE + eqn1_3: iDiode == neg_sat * (exp(-(BV + vDiode)/Vt) - 1.0 + + saturation_current); + END USE ; + + eqn2: v2 == i2 * 100.0; -- resistor eqn. + + eqn3: vs == 20.0 * sin(2.0 * 3.1415 * 10000.0 * real(time'pos(now)) * + 1.0e-15); -- source + + eqn4: vd == 5.0; -- dc source +END behav; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/double_tuned.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/double_tuned.ams new file mode 100644 index 000000000..d76b33795 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/double_tuned.ams @@ -0,0 +1,201 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: double_tuned.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +--************************************************************************ +-- Structural Model of a DOUBLED TUNED TRANSFORMER +-- VHDL-AMS implementation +-- Developed at Distributed Processing Laboratory +-- University of Cincinnati +--************************************************************************ + +--************************************************************************ +-- +-- ________________________________ +-- V_in | | +-- o-----|-------- ------------|---o V_out +-- | | | | | | +-- | | | | | | +-- | | | | | | +-- | | >rp rs< | | +-- | | > < --- | +-- FM | _|_ | . | --- | FM & AM Signal +-- Signal | ___ ( ) ( ) |Cs | +-- | | ( ) || ( ) | | +-- | |Cp ( ) || ( ) | | +-- | | | Lp Ls | | | +-- o-----|-------- ------------|---o V_out_gnd +-- Vin_gnd |________________________________| +-- +--************************************************************************ + +PACKAGE electricalSystem IS +NATURE electrical IS real ACROSS real THROUGH ground reference; +FUNCTION SIN (X : real ) RETURN real; +FUNCTION COS (X : real ) RETURN real; +FUNCTION EXP (X : real ) RETURN real; +FUNCTION SQRT (X : real) RETURN real; +END PACKAGE electricalSystem; + +------------------------------------------------------------------------------ +---------------------- TUNED TRANSFORMER ------------------------------------ +------------------------------------------------------------------------------ + +USE work.electricalSystem.all; + +ENTITY FM_2_AM_Converter IS +generic (freq_fm : real := 1.0); +port (terminal Signal_in, Signal_out : electrical); +END FM_2_AM_Converter; + +ARCHITECTURE behav OF FM_2_AM_Converter IS + + CONSTANT k :real:=0.4; + CONSTANT lp :real:=1.0e-3; + CONSTANT ls :real:=1.0e-3; + CONSTANT rp :real:=10.0; + CONSTANT rs :real:=10.0; + +--> Q = 2*PI*Freq*L/R : for 10.7 MHz -> q=6723 + + terminal temp1,temp2: electrical; + + quantity v_rp across i_rp through Signal_in to temp1; + quantity v_rs across i_rs through temp2 to Signal_out; + + quantity V_cp across i_cp through Signal_in to ground; + quantity V_cs across i_cs through Signal_out to ground; + + QUANTITY V_lp ACROSS i_lp Through temp1 to ground; + quantity v_ls across i_ls through temp2 to ground; + + quantity m : real ; -- mutual inductance; + + +BEGIN -- behavior + + brk : break i_lp => 0.0, i_ls => 0.0,v_cp=>0.0,v_cs=>0.0; + + mutual : m == k * sqrt(lp*ls); + voltp : v_lp == lp * i_lp'dot + m * i_ls'dot; + volts : v_ls == ls * i_ls'dot + m * i_lp'dot; + + i_cp == (25.331/(freq_fm*freq_fm))*v_cp'dot; -- cal. using the value of Inductance + i_cs == (25.331/(freq_fm*freq_fm))*v_cs'dot; -- as 1.0e-3. + -- modify this if u want to use another + v_rp == rp *i_rp; -- value of Lp and ls + v_rs == rs *i_rs; -- c =1/(2*PI*F)*(2*PI*F)*L + +END behav; + +------------------------------Test Waveforms----------------------- + +--> FM wave generator +---------------------- + +use work.electricalsystem.all; + +ENTITY fm_source IS +generic(c_freq:real:=100.0e6; -- carrier frequency + s_freq:real:=25.0e3; -- modulating(signal) frequency + V_fm :real:=1.0 -- Peak voltage of FM signal + ); +PORT(TERMINAL fm_out,fm_gnd : electrical); +END fm_source; + +ARCHITECTURE fm_behavior OF fm_source IS + +quantity V_fm_signal across i_fm_signal through fm_out to fm_gnd; + +BEGIN + +--- the max. freq. deviation is 75.0Khz for FM Signal. + + V_fm_signal == (V_fm*sin((2.0*22.0/7.0*c_freq*real(time'pos(now))*1.0e-15)+(75.0e3/s_freq*sin(2.0*22.0/7.0*s_freq*real(time'pos(now))*1.0e-15)))); + +END ARCHITECTURE fm_behavior; + +-------------------------------- TEST BENCH -------------------------- + +use work.electricalSystem.all; + +entity test is +end test; + +architecture structure of test is + + terminal t1,t2,t3 : electrical; + +--> Component Declarations + +component fm_source is +generic(c_freq:real:=100.0e6; -- carrier frequency + s_freq:real:=25.0e3; -- modulating(signal) frequency + V_fm:real:=1.0 -- Peak Voltage of FM Signal + ); +PORT( TERMINAL fm_out,fm_gnd : electrical); +end component; +for all: fm_source use entity work.fm_source(fm_behavior); + +component FM_2_AM_Converter IS +generic (freq_fm : real := 1.0); +port (terminal Signal_in, Signal_out : electrical); +end component; +for all : FM_2_AM_Converter use entity work.FM_2_AM_Converter(behav); + +quantity v_out across i_out through t2 to ground; + +begin + + FM_AM : FM_2_AM_Converter generic map(freq_fm=>10.7816e6) + port map(t1,t2); + + fm_ip : fm_source generic map(10.7e6,10.0e3,1.0) + port map(t1,ground); + + resout : v_out == i_out * 1.0e6; + +end structure; + +------------------------------ NOTES ------------------------------------- +-- It is a tuned transformer with the resonant freq. slighty higher +-- than the carrier freq. +-- +-- Q = 2*PI*Freq*L/Rl BandWidth = F_carrier/Q +-- F_carrier = 1/2*PI*sqrt(L*C) +-- +-- Tune the Transformer to a frequency of (All quantities in MHz) +-- ( F_carrier + 0.075 + 0.005 + Band_width ) +-- | +-- | +-- *-> Max Deviation +---------------------------------------------------------------------------- diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/hwr_filter.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/hwr_filter.ams new file mode 100644 index 000000000..ec678f192 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/hwr_filter.ams @@ -0,0 +1,109 @@ + +-- Copyright (C) 1998-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: hwr_filter.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- Title : Half Wave Rectifier with capacitor filter +-- Project : Mixed signal simulation +---------------------------------------------------------------------- +-- File : hwr.vhd (Behavioral) +-- Author(s) : Vasudevan Shanmugasundaram(vasu@ececs.uc.edu) +-- Created : jan 16 1998 +---------------------------------------------------------------------- +-- Description : +-- Behavioral description of a half wave rectifier circuit with a +-- capacitor filter. +---------------------------------------------------------------------- +-- T1 diode D T2 +-- o-----|>|-----o----o-------o The circuit comprises: +-- | | | i) A diode . +-- ( ) | >R=100ohms ii) A sinusoidal voltage source +-- |Vs = 5sinwt __ > iii)A resistor R. +-- | -- > iv) A capacitor C. +-- | |C | +-- |_____________|____|_______o +-- |gnd +-- ----- +---------------------------------------------------------------------- + +PACKAGE electricalSystem IS + + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN (X : real ) RETURN real; + FUNCTION EXP (X : real ) RETURN real; + +END PACKAGE electricalSystem; + +---------------------------------------------------------------------- + +USE work.electricalSystem.all; + +ENTITY hwr_filter IS +END hwr_filter; + +-- purpose: a capacitor filtered half wave rectifier +ARCHITECTURE behav OF hwr_filter IS + + terminal t1, t2 : electrical; + quantity vDiode across iDiode through t1 TO t2; + quantity v2 across i2 through t2 TO electrical'reference; + quantity vc across ic through t2 TO electrical'reference; + quantity vs across t1 TO electrical'reference; + + CONSTANT saturation_current : real := 0.0000000000001; + CONSTANT Vt : real := 0.025; + + CONSTANT BV : real := 100.0; + CONSTANT neg_sat : real := -saturation_current; + +BEGIN -- behav + + -- diode behavior equation + if( vDiode >= (-1.0 * Vt)) USE + eqn1_1: iDiode == saturation_current * (exp(vDiode/Vt) - 1.0); + + ELSIF ((vDiode < (-3.0 * Vt)) AND (vDiode > -BV)) use + eqn1_2: iDiode == neg_sat; + + ELSE + eqn1_3: iDiode == neg_sat * (exp(-(BV + vDiode)/Vt) - 1.0 + saturation_current); + + END USE ; + + eqn2: v2 == 100.0 * i2; -- resistor + + eqn4: vs == 5.0 * sin(2.0 * 3.1415 * 10000.0 --sine source + * real(time'pos(now)) * 1.0e-15); + + eqn6: ic == 0.000005 * vc'dot; -- capacitor + +END behav; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/limiter.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/limiter.ams new file mode 100644 index 000000000..3e605b442 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/limiter.ams @@ -0,0 +1,153 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: limiter.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +-- +-- R1(10.0) R2(10.0) +-- o----^^^^^^^^------o-^^^--o--------------o +-- V_in T1| | V_out +-- | | +-- | | +-- _|_ --- +-- \ / / \ +-- --- --- +-- | | +-- T2 o o T3 +-- | | +-- ----- --- +-- --- ----- +-- | | +-- | | +-- V_in_gnd | | V_out_gnd +-- o----------------------------------------o + + + PACKAGE electricalsystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X:real) RETURN real; + FUNCTION EXP(X:real) RETURN real; + END PACKAGE electricalsystem; + +-------------------------- LIMITER ------------------------------ +use work.electricalsystem.all; + +entity limiter is +generic (lim:real:=1.0); +port (terminal v_in,v_out :electrical); +end entity limiter; + +architecture behav of limiter is + +terminal t1,t2,t3 :electrical; + +constant k:real := 0.02586; -- thermal voltage +constant iss:real := 1.8104e-15; +constant gmin:real := 1.0e-12; + +quantity vd1 across id1 through t1 to t2; +quantity vd2 across id2 through t3 to v_out; +quantity V_volt1 across i_volt1 through t2 to ground ; +quantity V_volt2 across i_volt2 through ground to t3; +quantity v_r1 across i_r1 through V_in to T1; +quantity v_r2 across i_r2 through T1 to V_out; + +BEGIN + + if (vd1 >= (-5.0*k)) use + id1 == iss * (exp(vd1/k)-1.0) + vd1*gmin; + elsif (vd1<-5.0*k) use + id1 == -1.0*iss + vd1*gmin; + end use; + + if (vd2 >= (-5.0*k)) use + id2 == iss * (exp(vd2/k)-1.0) + vd2*gmin; + elsif (vd2<-5.0*k) use + id2 == -1.0*iss + vd2*gmin; + end use; + V_volt1 == (lim); + V_volt2 == (lim); + V_r1 == i_r1*10.0; + V_r2 == i_r2*10.0; + +end architecture behav; + + +--------------------------- Test Waveforms ----------------------------- + +use work.electricalsystem.all; +ENTITY sineSource IS +generic( amp:real:=1.0); + PORT( TERMINAL ta2,tb2 : electrical); +END sineSource; + +ARCHITECTURE sinebehavior OF sineSource IS +quantity Vsine across isine through ta2 to tb2; + +BEGIN + Vsine == (amp*sin((2.0*22.0/7.0*10.7e6)*real(time'pos(now))*1.0e-15)); + +END ARCHITECTURE sinebehavior; + + +------------------------------ Test Case ------------------------------- +use work.electricalsystem.all; +entity testbench is +end entity; + +architecture basic of testbench is + + +terminal t1,t2 :electrical; + +quantity v_out across i_out through t2 to ground; + +component limiter is +generic (lim:real:=1.0); +port(terminal v_in,v_out :electrical); +end component; + +component sinesource is +generic( amp:real:=1.0); + PORT( TERMINAL ta2,tb2 : electrical); +end component; + +BEGIN + +lim : limiter generic map(lim=>3.0) + port map(t1,t2); + +sine: sinesource generic map(amp=>6.0) + port map(t1,ground); + +v_out ==i_out*1.0e3; + +end basic; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/peak_detector.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/peak_detector.ams new file mode 100644 index 000000000..9e23e20b1 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/peak_detector.ams @@ -0,0 +1,274 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: peak_detector.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +-- Change the values of res. and cap for various freq.'s + + + +--************************************************************************* +-- Conceptual Level Model of a Peak Detector +-- VHDL-AMS implementation +-- Developed at Distributed Processing Laboratory +-- University of Cincinnati +-- by Murthy Revanuru on October 27, 2000. +--************************************************************************* + +--######################################################################### +-- R2= 10.0e3 +-- --------/\/\/\---------- +-- | |\ | +-- .-------|-\ Diode | +-- | \________|\___|_____o V_out +-- 10K | / |/ | +-- V_in o---^^^-|+/ |-------- +-- R1 |/ | | +-- _____ \ +-- Cap _____ / Res +-- | \ +-- | / +-- | | +-- --------- ----- +-- --- - +-- +--######################################################################### + + PACKAGE electricalsystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X:real) RETURN real; + FUNCTION COS(X:real) RETURN real; + FUNCTION EXP(X:real) RETURN real; + FUNCTION SQRT(X:real) RETURN real; + END PACKAGE electricalsystem; + +---------------------------- Diode ----------------------------- +use work.electricalsystem.all; + +entity diode is +port (terminal t21,t22:electrical); +end diode; + +architecture behavior of diode is + +quantity vd across id through t21 to t22; +constant k:real:=0.02586; -- thermal voltage +constant iss:real:=1.8104e-15; +constant gmin:real:=1.0e-12; + +begin + +if (vd >= (-5.0*k)) use + id == iss * (exp(vd/k)-1.0) + vd*gmin; +elsif (vd<-5.0*k) use + id == -1.0*iss + vd*gmin; +end use; +end architecture behavior; + +------------------------ RESISTOR--------------------------- +use work.electricalsystem.all; + +entity resistor is + generic(res :real:=1.0 ); + port(terminal r_in,r_out: electrical); +end entity resistor; + +architecture behav of resistor is + quantity vr across ir through r_in to r_out; + +begin + vr==ir*res; +end architecture behav; + +------------------------ CAPACITOR--------------------------- +use work.electricalsystem.all; + +entity capacitor is + generic(cap :real:=1.0;v_init:real:=0.0); + port(terminal c_in,c_out: electrical); +end entity capacitor; + +architecture behav of capacitor is + +quantity vc across ic through c_in to c_out; + +begin + break vc=>v_init; + ic==cap*vc'dot; +end architecture behav; + +------------------------- OP AMP ------------------------- +use work.electricalsystem.all; + +entity op_amp is +port(terminal inverting_ip,non_inverting_ip,output :electrical); +end entity op_amp; + +architecture struct of op_amp is + +Constant R_in:real:=1.0e6; +Constant R_out:real:=1.0; + +terminal t1:electrical; + +quantity v_in across i_in through non_inverting_ip to inverting_ip; +quantity v_gain across i_gain through t1 to ground; +quantity v_drop across i_drop through t1 to output; + +BEGIN + + V_in==i_in*R_in; + V_gain==V_in*(100.0); + V_drop==i_drop*R_out; + +end architecture struct; + +---------------------- PEAK DETECTOR --------------------- +use work.electricalsystem.all; + +entity peak_detector is +port (terminal v_in,v_out: electrical); +end entity peak_detector; + +architecture struct of peak_detector is + +component capacitor is + generic(cap :real:=1.0;v_init:real:=0.0); + port(terminal c_in,c_out: electrical); +end component; +for all: capacitor use entity work.capacitor(behav); + +component resistor is + generic(res :real:=1.0 ); + port(terminal r_in,r_out: electrical); +end component; +for all: resistor use entity work.resistor(behav); + +component diode is +port (terminal t21,t22:electrical); +end component; +for all: diode use entity work.diode(behavior); + +component op_amp is +port(terminal inverting_ip,non_inverting_ip,output :electrical); +end component; +for all:op_amp use entity work.op_amp(struct); + +terminal t11,t12,t13,t14: electrical; + + +begin + + D1: diode port map(t12,t13); + + R1: resistor generic map(10.0e3) + port map(v_in,T11); + R2: resistor generic map(10.0e3) + port map(T13,T14); + Rs: resistor generic map(1.0e-3) + port map(T13,V_out); + + C1: capacitor generic map(1.0e-9) + port map(T13,ground); + + op: op_amp port map(inverting_ip=>T14,non_inverting_ip=>T11,output=>T12); + +end struct; + +-- ################### TEST WAVE FORMS ####################### +-- Sine Source +-------------- +use work.electricalsystem.all; +ENTITY sineSource IS +generic (amp:real:=1.0; freq:real:=1.0); + PORT( TERMINAL ta2,tb2 : electrical); +END sineSource; + +ARCHITECTURE sinebehavior OF sineSource IS +quantity Vsine across isine through ta2 to tb2; + +BEGIN + Vsine ==(amp*sin((2.0*22.0/7.0*freq)*real(time'pos(now))*1.0e-15)); + +END ARCHITECTURE sinebehavior; + +-- AM Source +-------------- +use work.electricalsystem.all; +ENTITY amSource IS +generic (amp:real:=1.0; wc:real:=1.0;wm:real:=1.0); + PORT( TERMINAL ta2,tb2 : electrical); +END amSource; + +ARCHITECTURE ambehavior OF amSource IS +quantity V_am across i_am through ta2 to tb2; + +BEGIN + V_am == (amp*cos((2.0*22.0/7.0*wc)*real(time'pos(now))*1.0e-15)) +(amp/2.0*cos((2.0*22.0/7.0*(wc+wm))*real(time'pos(now))*1.0e-15)) + + (cos((2.0*22.0/7.0*(wc-wm))*real(time'pos(now))*1.0e-15)); + +END ARCHITECTURE ambehavior; + +------------------------- Test bench ------------------------- + +use work.electricalsystem.all; + +entity rf_test_bench is +end entity rf_test_bench; + +architecture basic of rf_test_bench is + +terminal t1,t2,t3,t4 : electrical; + +----> Components are declared here + +component peak_detector is +port(terminal v_in,v_out :electrical); +end component; +for all: peak_detector use entity work.peak_detector(struct); + +COMPONENT sineSource IS +generic (amp:real:=1.0; freq:real:=1.0); + PORT( TERMINAL ta2,tb2 : electrical);--Interface ports. +end COMPONENT; +for all : sinesource use entity work.sinesource(sinebehavior); + +quantity volt_op across i_op through t4 to ground; + +begin + + op_1 : volt_op==i_op*10000.0; + + peak_det : peak_detector port map(t1,t4); + sine_ip : sinesource generic map(1.0,455.0e3) + port map(t1,ground); + +end architecture basic; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/power_supply.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/power_supply.ams new file mode 100644 index 000000000..c83db0b57 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/power_supply.ams @@ -0,0 +1,138 @@ + +-- Copyright (C) 1997-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: power_supply.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- Title : Power supply circuit (Behavioral) +-- Project : Mixed signal simulation +---------------------------------------------------------------------- +-- File : power_supply.ams +-- Author : Kathiresan Nellayappan <knellaya@ececs.uc.edu> +-- Chandrashekar L Chetput <cchetput@ececs.uc.edu> +-- Created : 26.11.1997 +---------------------------------------------------------------------- +-- Description : +-- VHDL-AMS description of a power supply circuit. +-- BEHAVIORAL DESCRIPTION. +---------------------------------------------------------------------- +-- The ciruit schematic for the power supply circuit is as below: +-- ============================================================== +-- It comprises: +-- diode D1 inductor i) a sinusoidal +-- T2 _____|\|____ T3 L1 T4 voltage source +-- o______| |/| |____o______()()()____o______o ii) a diode D1 +-- | | | | 0.1H | | iii)3 capacitors +-- < | | | | | iv) inductor L1 +-- < R1 |_____||_____| | | | v) source and +-- < 5ohms || _____ _____ < load resistances +-- < C1 ----- ----- < RL +-- | 1microF | | < +-- o T1 | | < +-- | |C2 |C3 < 1K +-- ( )Vin |1mf |1mf < +-- | 10(sinwt) | | | +-- o________________________|________________|______| +-- |gnd +-- ----- +---------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN (X : real ) RETURN real; + FUNCTION EXP (X : real ) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; + +--Entity declaration: +ENTITY power_supply IS +END ENTITY power_supply; + + +--Architecture declaration: +ARCHITECTURE behavior OF power_supply IS + + CONSTANT Capacitance1 : real := 0.000001; -- value of C1 + CONSTANT Capacitance2 : real := 0.001; -- value of C2 + CONSTANT resistance1 : real := 5.0; -- value of R1 + CONSTANT load_resistance : real := 1000.0; -- value of RL + CONSTANT inductance : real := 0.1; -- value of L1 + CONSTANT BV : real := 100.0; -- Diode Breakdown voltage + CONSTANT saturation_current : real + := 0.0000000000001; -- Diode saturation current value. + CONSTANT Vt : real := 0.025; -- Vt = KT/q (thermal voltage) + CONSTANT neg_sat : real + := -saturation_current; -- Negative of the saturation current + CONSTANT MATH_PI : real := 3.14159_26535_89793_23846; + + terminal t1, t2, t3, t4 : electrical; + + +--quantity declarations: + QUANTITY Vin ACROSS Iin THROUGH T1; + QUANTITY vr1 ACROSS ir1 THROUGH T2 TO T1; + QUANTITY d1_v ACROSS d1_i THROUGH T2 TO T3; + QUANTITY vc1 ACROSS ic1 THROUGH T2 TO T3; + QUANTITY vc2 ACROSS ic2 THROUGH T3; + QUANTITY vl ACROSS il THROUGH T3 TO T4; + QUANTITY vc3 ACROSS ic3 THROUGH T4; + QUANTITY vr2 ACROSS ir2 THROUGH T4; + QUANTITY phi : real; --free quantity. + + +BEGIN + + C1: ic1 == vc1'dot * Capacitance1; -- capacitance equation: ic = c*dv/dt. + C2: ic2 == vc2'dot * Capacitance2; -- capacitance equation for C2. + C3: ic3 == vc3'dot * Capacitance2; -- capacitance equation for C3. + res_stmt1: vr1 == ir1 * resistance1; -- resistance equation: v = i*r. + res_stmt2: vr2 == ir2 * load_resistance; -- resistance equation. + induct_stmt: phi == inductance * il; -- inductance equation: flux = L*I + aux_stmt: vl == phi'dot; -- inductance equation: VL = dflux/dt. + + -- the diode equations: + diode1Cond1: IF( d1_V >= (-3.0 * Vt) ) USE + --active region: + diode1St1: d1_I == saturation_current * (exp(d1_V/Vt) - 1.0); + ELSIF( (d1_V < (-3.0 * Vt)) AND (d1_V > -BV)) USE + -- + diode1St2: d1_I == neg_sat; + ELSE + diode1St3: d1_I == neg_sat * (exp(-(BV + d1_V)/Vt) -1.0 + + saturation_current); + END USE; + + --Sinusoidal voltage source: + vsource: Vin == 10.0 * sin(2.0 * 3.14 * 60.0 * real(time'pos(now)) * + 1.0e-15); + +END ARCHITECTURE behavior; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test100.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test100.ams new file mode 100644 index 000000000..eba8a87cf --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test100.ams @@ -0,0 +1,77 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test100.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test100.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple resistor model... +-- the test is done for checking the correct implementation +-- of the simple simultaneous equation statement.it checks +-- nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity V1 across I1 through T1 to T2; +quantity V2 across I2 through T2; +quantity V3 across I3 through T2; +quantity VS across T1; + +begin + +e1: V1 == I1*100.0; +e2: V2 == I2*10.0; +e3: V3 == I3*10.0; + +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test101.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test101.ams new file mode 100644 index 000000000..daf5ffbb7 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test101.ams @@ -0,0 +1,70 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test101.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +---------------------------------------------------------------------- +-- File : test101.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- this test checks teh correctness of the 'integ implementation. +-- it finds the integral of teh source voltage. +-- the input is a sine wave. +--------------------------------------------------------------------- +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity test; + +architecture atest of test is +quantity vs : real; +quantity vout: real; +begin +vs== 5.0 * sin(2.0 * 3.1415 * 10.0 * real(time'pos(now)) * + 1.0e-15); +vout == vs'integ; +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test102.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test102.ams new file mode 100644 index 000000000..db2b9758f --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test102.ams @@ -0,0 +1,82 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test102.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test102.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks the correctness of the Q'integ usage on the RHS of +-- the simple simultaneous eqn. +-------------------------------------------------------------------- +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + + --ALIAS GND is electrical'reference; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity tank is +end tank; + +architecture atank of tank is + +terminal t1,t2 : electrical; + +constant r: real :=10.00; +constant c: real:=0.00000003; + +quantity vin across t1 to electrical'reference; +quantity vr across ir through t1 to t2; +quantity vc across ic through t2 to electrical'reference; +quantity q : real; +begin + + vr == ir*r; + q==c*vc; + ic==q'integ; + vin == 5.0 * sin(2.0 * 3.1415 * 10.0 * real(time'pos(now)) * + 1.0e-15); +end atank; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test103.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test103.ams new file mode 100644 index 000000000..805fac66e --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test103.ams @@ -0,0 +1,84 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test103.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test103.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks the correctness of the simple simultaneous eqn. +-- implementation. This is also a test for the lexical analysis. +-------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUD REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2,T3,T4,T5:electrical; +quantity v1 across i1 through T1 to T2; +quantity v2 across i2 through T2 to T4; +quantity v3 across i3 through T4 to T3; +quantity v4 across i4 through T2 to T5; +quantity v5 across i5 through T5 to T3; +quantity v6 across i6 through T2 to T3; +quantity vS across T1 to electrical'reference; + +begin + +e1: v1==i1*1.0; +e2: v2==i2*1.0; +e3: v3==i3*1.0; +e4: v4==i4*1.0; +e5: v5==i5*1.0; +e6: v6==i6*1.0; +es: vS==5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test104.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test104.ams new file mode 100644 index 000000000..72f1b4e9b --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test104.ams @@ -0,0 +1,90 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test104.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test104.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- this is a test that checks for the correct implementation of if use +-- end use. The condition is checked by comparing the quantity against a +-- known constant value. +----------------------------------------------------------------------- +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is + generic (vmax :real:=10.0); +end entity; + +architecture atest of test is +terminal T1:electrical; +quantity vin across T1; +constant a:real:=1.0; +constant b:real:=2.0; +quantity vin1:real; +quantity vin2:real; + +begin + +vin == vmax/a; + +if (vin==10.0) use +e1: vin1==vmax*b; +else +e2: vin2==vmax; +end use; + + +--if(vin<vmax) use +--e3: vin==vmax/b; +--else +--e4: vin==vmax; +--end use; + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test105.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test105.ams new file mode 100644 index 000000000..7b426ba97 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test105.ams @@ -0,0 +1,79 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test105.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test105.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks for the correctness of quantity as a port declaration. +-- the circuit is a simple RC network with vout acting as thge output port. +-- a sine input is applied to the network. +------------------------------------------------------------------------- +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + FUNCTION COS(X : real) RETURN real; + --ALIAS GND is electrical'reference; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +entity test is + port(quantity vout:out real); +end entity; + +architecture atest of test is + terminal T1,T2:electrical; + quantity VR across IR through T1 to T2; + constant R:real:=100.0; + constant C:real:=1.0e-9; + quantity vout across T2; + quantity vin across T1; +begin + vsource: vin==5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + + vres: IR== VR/R; + cap: vout==C*IR'integ; + +end atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test106.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test106.ams new file mode 100644 index 000000000..c548b2bf0 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test106.ams @@ -0,0 +1,85 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test106.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +---------------------------------------------------------------------- +-- File : test106.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple resistor model... +-- the test is done for checking the correct implementation +-- of the simple simultaneous equation statement.it checks +-- nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2, T3, T4,T5,T6:electrical; +quantity VRgen across IRgen through T1 to T2; +quantity VLgen across ILgen through T2 to T3; +quantity VRin across IRin through T3; +quantity VR1 across IR1 through T4 to T5; +quantity VR1A across IR1A through T4 to T6; +quantity VC1A across IC1A through T6 to T5; +quantity VC1 across IC1 through T5; +quantity VS across T1; +constant C1: real:=3.5e-3; +constant C1A: real:=0.3e-3; +begin + +e1: VRgen == IRgen*10.0; +e2: VLgen == 0.5*ILgen'dot; +e3: VRin == IRin*500.0; +e4: VR1 == IR1*1.0; +e5: VR1A == IR1A*0.2; +e6: IC1 == C1 * VC1'dot; +e7: IC1A == C1A*VC1A'dot; + +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test108.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test108.ams new file mode 100644 index 000000000..6bfad5b19 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test108.ams @@ -0,0 +1,74 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test108.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test100.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple resistor model... +-- the test is done for checking the correct implementation +-- of the simple simultaneous equation statement.it checks +-- nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; +architecture atest of test is +terminal t1, t2: electrical; +quantity vd across id through T1; -- to T2; +quantity charge :real; +constant vt:real:=0.02; + +begin + +p1: procedural is +begin + vd:=1.0*id; +end procedural; + +end architecture; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test109.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test109.ams new file mode 100644 index 000000000..0a2f21ae2 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test109.ams @@ -0,0 +1,80 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test109.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test109.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks for the correctness of the procedural statements. +-- multiple terms on the RHS +---------------------------------------------------------------------- +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUD REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + + --ALIAS GND is electrical'reference; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal t1,t2: electrical; +quantity vd across id through t1 to t2; +quantity charge:real; +constant vt:real:=0.0258; +constant x:real:=1.0; +quantity ic:real; + +begin +p1: procedural +begin +id:=0.1*(exp((vd-1.0*id)/vt)-1.0); +charge := x*id; +ic:= charge'dot; +end procedural; + +end architecture; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test110.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test110.ams new file mode 100644 index 000000000..96052a1e8 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test110.ams @@ -0,0 +1,69 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test110.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +-- an example of a model having both a signal assignment statement +-- as well as a simple simultaneous statement. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND reference; + FUNCTION SIN (X : real ) RETURN real; + FUNCTION EXP (X : real ) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +use std.textio.all; +ENTITY test IS +END test; + +ARCHITECTURE behavior OF test IS + CONSTANT r1 : real := 100.0; -- value of R1 + terminal t1 : electrical; + QUANTITY vIn ACROSS t1; + QUANTITY vR ACROSS iR THROUGH t1 ; + signal y:bit:='0'; +BEGIN + +process(y) +begin + y <= not(y) after 100 ns; + +end process; + + testbench:PROCESS + BEGIN + WAIT ON y; + END PROCESS; + res_stmt1: vR == iR * r1 ; + vsource: vIn == 5.0 * sin(2.0 * 3.14 * 100000.0 * real(time'pos(now)) * 1.0e-15); + +END ARCHITECTURE behavior; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test111.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test111.ams new file mode 100644 index 000000000..4f86612ba --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test111.ams @@ -0,0 +1,75 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test111.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : model.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks the correctness of the Q'Tolerance. +-- the test checks for the simpel diode implementation +-- wherein the charge is evaluated wrt a relative tolerance value +---------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +entity test is + generic(a:real:=1.0e-10; b:real:=0.0); + port (terminal t1: electrical); +end entity; + +architecture atest of test is + quantity vd tolerance "reltol=1.0e-2" across id through t1; + quantity charge: real; + quantity ic : real; + constant rd: real:=1.0; +begin + e1: id== a*(sin((vd-id*rd)/0.5)-1.0); + e2: charge== b*id; + e3: ic==charge'dot; +end architecture; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test113.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test113.ams new file mode 100644 index 000000000..0e3575822 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test113.ams @@ -0,0 +1,79 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test113.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +---------------------------------------------------------------------- +-- File : test113.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks the correctness of the Q'Tolerance for across qnty +-- and for the real quantity.The test checks for the simpel diode +-- implementation wherein the charge is evaluated wrt a relative +-- tolerance value +-- the test doesn't seem to take a tolerance associated with a +-- free quantity. we need to check on this!! (LRM : 4.3.1 spec +-- followed. +---------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +generic(a:real:=1.0e-10; b:real:=0.0); +port (terminal t1: electrical); + +end entity; + +architecture atest of test is +quantity vd across id through t1; -- to electrical'reference; +quantity charge:real tolerance "reltol=1.0e-2"; +--quantity ic : real; +constant rd: real:=1.0; +begin +e1: id== a*(sin((vd-id*rd)/0.5)-1.0); +e2: charge== b*id; +--e3: ic==charge'dot; +end architecture; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test114.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test114.ams new file mode 100644 index 000000000..7bd8078ae --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test114.ams @@ -0,0 +1,77 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test114.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : model.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks the correctness of the two currents associated +-- as through between same terminals.for eg: consider 2 resistors in +-- parallel.. here vd is same and id and ic are the currents. +-- the test checks for the simpel diode implementation +-- wherein the charge is evaluated wrt a relative tolerance value +---------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +entity test is + generic(a:real:=1.0e-10; b:real:=0.0); +end entity; + +architecture atest of test is + terminal t1:electrical; + quantity vd across id, ic through t1; + quantity charge: real; + --quantity ic : real; + constant rd: real:=1.0; +begin + e1: id== ((vd-id*rd)/0.5); + e2: charge== b*id; + e3: ic==charge'dot; +end architecture; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test115.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test115.ams new file mode 100644 index 000000000..c0232d059 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test115.ams @@ -0,0 +1,84 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test115.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test115.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks for the correctness of the interface declaration: +-- quantity : in| out. +-- ref LRM 4.3.2 +--------------------------------------------------------------------- +PACKAGE electricalSystem IS + subtype voltage is real; + subtype current is real; + NATURE electrical is voltage across current THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; + +entity test is + + port(quantity vout:out electrical); + +end entity test; + +architecture atest of test is +terminal t1,t2: electrical; + +quantity vin across iin through t1; +quantity vr across ir through t1 to t2; +quantity vout across t1 to t2; + +begin + +e1: vin== 5.0 * sin(2.0 * 3.1415 * 10000000.0 * real(time'pos(now)) *1.0e-15); + +e2: vr==ir*1.0; + +e3: vout== vr; + +end architecture; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test116.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test116.ams new file mode 100644 index 000000000..0ce660f14 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test116.ams @@ -0,0 +1,83 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test116.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test116.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks for the correctness of the interface declaration: +-- quantity : in| out. A simple R circuit with an ac voltage source +-- is used. +-- ref LRM 4.3.2 +--------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical is real across real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is + + port(quantity vout:out voltage); + +end entity test; + +architecture atest of test is +terminal t1,t2: electrical; + +quantity vin across iin through t1; +quantity vr across ir through t1 to t2; +quantity vout across t1 to t2; + +begin + +e1: vin== 5.0 * sin(2.0 * 3.1415 * 10000000.0 * real(time'pos(now)) *1.0e-15); + +e2: vr==ir*1.0; + +e3: vout== vr; + +end architecture; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test118.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test118.ams new file mode 100644 index 000000000..7e452987b --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test118.ams @@ -0,0 +1,91 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test118.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test118.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- + +-- the test checks for the correctness of the implemenatation of the case statement. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + + --ALIAS GND is electrical'reference; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; + +entity test is +end entity test; + +architecture atest of test is +terminal t1:electrical; +signal ison: boolean; +quantity vr across ir through t1; +constant vt:real:=0.0258; +begin + +process + variable off : boolean:=true; +begin + ison <= not off; + case off is + when true=> + ison<= not off; + when false=> + ison<=off; + end case; +end process; +source: vr==10.0 * sin(2.0 *(22.0/7.0)*100000.0*real(time'pos(now)) * 1.0e-15); +if ison use + ir== 5.0; --*(exp(vr/vt)-1.0); +else + ir==0.0; +end use; + +break on ison; +end architecture; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test119.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test119.ams new file mode 100644 index 000000000..ee7d1b60d --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test119.ams @@ -0,0 +1,93 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test119.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test1.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +-- Last modified : +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- This is the simple resistor model that sets the foundation on which +-- we build SIERRA, the VHDL AMS simulator. The circuit consists of 3 +-- resistors connected to a voltage source. +-- T1 R1 T2 +-- o-----/\/\----o-------- +-- | | | +-- ( ) > > +-- |Vs = 5sinwt >R2 >R3 +-- | > > +-- |_____________|____|___ +-- |gnd +-- ---- +-------------------------------------------------------------------------- +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is + +constant R1: real :=10.0; +constant R2: real :=5.0; +constant R3: real :=1.0; +terminal T1,T2:electrical; +quantity V1 across I1 through T1 to T2; +quantity V2 across I2 through T2 to electrical'reference; +quantity V3 across I3 through T2 to electrical'reference; +quantity VS across T1 to electrical'reference; + +begin + +e1: V1 == I1*R1; +e2: V2 == I2*R2; +e3: V3 == I3*R3; + +esource:VS == 5.0 * sin(2.0 * 3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; + diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test121.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test121.ams new file mode 100644 index 000000000..9da136bdf --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test121.ams @@ -0,0 +1,80 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test121.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test3.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- this is to check the quantity: q'dot in the lhs and rhs of the +-- simultaneous statements +--------------------------------------------------------------------- +PACKAGE electricalSystem is + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is + quantity x11: real; + constant x1:real:=2.0; + constant x2:real:=1.0; + constant m1 : real:=1.0; + quantity f : real; + quantity dx1 : real; + +begin +e1: f == 10.0* sin(2.0 * 3.141592 *10000.0 * real(time'pos(now))*1.0e-12); +e2: x11 == f*(x1-x2)/m1; +e3: dx1 == f'dot; + +-- x1'dot == f*(x1-x2)/m1; +-- x2'dot == f*(x1-x2)/m2; +-- xs == (m1*x1+m2*x2)/(m1+m2); +-- m3 == m1*x1'dot+ m2*x2'dot; +end atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test122.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test122.ams new file mode 100644 index 000000000..ad2ccd342 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test122.ams @@ -0,0 +1,79 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test122.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test122.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- + +-- to check for the correct implementation of the simple simultaneous +-- statements +---------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + + --ALIAS GND is electrical'reference; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity chk is + generic(i:real:=1.0e-9); + port(terminal t1, t2: electrical); +end chk; + +architecture achk of chk is + quantity vd across id through t1 to t2; + quantity q: real; + quantity ic:real; + constant vth : real:= 0.025; +begin + +e1: id == i*(exp(vd/vth)-1.0); +e2: q == id*0.25; +e3: ic == q'dot; + +end achk; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test124.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test124.ams new file mode 100644 index 000000000..41f8d2658 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test124.ams @@ -0,0 +1,79 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test124.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test124.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- this test is to chk the support of ALIAS, NATURE in the PACKAGE +-- declaration the test also chks the corrct use of quantity and terminal +-- declarations. +-------------------------------------------------------------------------- +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; +END PACKAGE electricalSystem; + +--entity declaration + +use work.electricalsystem.all; +ENTITY Rckt IS +END Rckt; + +--architecture declaration + +ARCHITECTURE aRckt OF Rckt IS + + terminal T1, T2 : electrical; + + quantity VR across IR through T1 to T2; + quantity VR1 across IR1 through T2; + quantity VS across T1; + constant R : REAL := 10.00; + +BEGIN + +eqn1 : VR == IR * R; +e2: VR1 == IR1 * R; +eqn2 : VS == 5.0; + +end arckt; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test128.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test128.ams new file mode 100644 index 000000000..c92536663 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test128.ams @@ -0,0 +1,86 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test128.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test104.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- this is a test that checks for the correct implementation of if use +-- end use. The condition is checked by comparing the quantity against a +-- known constant value. +----------------------------------------------------------------------- +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + + --ALIAS GND is electrical'reference; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is + terminal T1, T2:electrical; + +quantity vin across T1 to electrical'reference; +constant a:real:=1.0; +constant b:real:=2.0; + +quantity vin1 across iin1 through T1 to T2; +quantity vin2 across iin2 through T2 to electrical'reference; +begin + +eq1: vin==5.0* sin(2.0 * 3.141592 *1000.0 * real(time'pos(now))*1.0e-12); +eq2: vin1== iin1*a; +eq3: vin2== iin2*b; +if (vin1>5.0) and (vin1<10.0) use +e1: vin1==vin/a; +elsif (vin2<5.0) use +e2: vin2==vin/b; +else +e3: vin1==vin; +end use; +end atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test136.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test136.ams new file mode 100644 index 000000000..275aa7a86 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test136.ams @@ -0,0 +1,85 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test136.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test136.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +-- Last modified : +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A resistor bridge network... +-- the test is done for checking the correct implementation +-- of the simple simultaneous equation statement.it checks +-- nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture mesh of test is + +terminal t1, t2, t4 : electrical; +quantity v1 across i1 through t1 to t2; +quantity v2 across i2 through t2; +quantity v3 across i3 through t4; +quantity v4 across i4 through t1 to t4; +quantity v5 across i5 through t1; +quantity vs across t1; + +begin + +e1: v1== i1*10.0; +e2: v2== i2*10.0; +e3: v3== i3*10.0; +e4: v4== i4*10.0; +e5: v5== i5*20.0; + +esource: vs== 10.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-15); + +end architecture mesh; + + diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test141.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test141.ams new file mode 100644 index 000000000..215384db4 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test141.ams @@ -0,0 +1,75 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test141.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test141.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +-- this is the behavioral model of a simple error amplifier. +-- the entity consists of a quatity port and the architecture consists +-- of a simple simultaneos statement +---------------------------------------------------------------------- +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +-- subtype voltage is real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity ErrorAmplifier is + generic( Gain : REAL := 10.0 -- amplifier gain + ); + port( terminal P_T,N_T: electrical; -- analog input pins + quantity Vout : out real -- analog output + ); +end entity ErrorAmplifier; + +architecture Behavior of ErrorAmplifier is + +quantity DeltaV across P_T through N_T; -- differential input voltage +begin +e1: DeltaV== 1.0* sin(2.0 * 3.141592 *10000.0 * real(time'pos(now))*1.0e-12); +e2: Vout == Gain*DeltaV; + +end architecture Behavior; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test145.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test145.ams new file mode 100644 index 000000000..ff7ecdbb5 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test145.ams @@ -0,0 +1,359 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test145.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test145.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : June 2001 +---------------------------------------------------------------------- +-- Description : +--this is a mos model. It tests for the correctness of the procedural +--statement. +-- +--the model accepts the mos data as generic constants. The terminals +--are defined as of nature electrical. +--it also tests the alias declaration for real'low. +--Charges associated with the 4 terminals are declared as quantities. +--The voltage associated with each of them is also defined. +--a signal is used to drive i.e to carry out a generic initialization. +--The various mos equations are evaluated depending on the conditions. +--The equations for charges and currents are evaluated. +---------------------------------------------------------------------- + +package mosdata is + NATURE electrical is real across real through; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + alias undefined is real'low; + constant Temperature: real:=27.0; + constant eps0 : real :=8.85418e-12; + constant Ni : real :=1.45e16; + constant Boltzmann : real :=1.380662e-23; + constant echarge: real :=1.6021892e-19; + constant epsSiO2 : real :=3.9*eps0; + constant epsSi : real :=11.7*eps0; + constant kTQ : real :=Boltzmann*temperature/echarge; + constant pi: real := 3.14159; +end package mosdata; + +use work.mosdata.all; +entity mos is + + generic( + width : real:=1.0E-4; + length : real:=1.0E-4; + channel: real :=1.0; + kp :real:= 2.0E-5; + gamma :undefined; + phi :undefined; + tox :real:= 1.0E-7; + nsub :real:= 0.0; + nss :real:=0.0; + nfs :real:= 0.0; + tpg :real:= 1.0; + xj :real:=0.0; + ld :real:= 0.0; + u0 :real:= 600.0; + vmax :real:=0.0; + xqc :real:= 1.0; + kf :real:=0.0; + af :real:=1.0; + fc :real:=0.5; + delta :real:=0.0; + theta :real:=0.0; + eta :real:=0.0; + Sigma :real:=0.0; + kappa :real:=0.2 ); + + port ( terminal drain, gate, source, bulk : electrical); + +end entity mos; + +architecture amos of mos is + quantity Qc, Qb, Qg: real; + quantity Qcq, Qbq, Qgq : real; -- channel, bulk and gate charges + quantity Vdsq across drain to source; + quantity Vgsq across gate to source; + quantity Vbsq across bulk to source; + quantity Idq through drain; + quantity Igq through gate; + quantity Isq through source; + quantity Ibq through bulk; + + signal Initialized: boolean; -- use a signal as generic initialisation + +begin + MOSeqns: procedural is + variable + cox,vt,beta,sigma,nsub,Phi,Gamma,nss,ngate,A,B,C,D,Vfb,fshort, + wp,wc,sqwpxj,vbulk,delv,vth,Vgstos, Vgst, + Ueff,Tau,Vsat,Vpp,fdrain, + stfct,leff,xd,qnfscox,fn,dcrit,deltal,It,Ids,R,Vds,Vgs,Vbs, + forward ,egfet,fermig, mobdeg: real; + begin -- procedural statements + + if not Initialized then + if tox<=0.0 then + cox:=epsSiO2/1.0e-7; + else + cox:=epsSiO2/tox; + end if; + + if kp = 0.0 then + beta:=cox*u0; + else + beta:=kp; + end if; + + nsub := nsub * 1.0e6; -- scale nsub to SI units + + if (phi = undefined) then + if (nsub > 0.0) then + if (0.1<2.0*KTQ*(nsub/Ni)) then + Phi:=(2.0*kTQ*(nsub/Ni)); + else + Phi:=0.1; + end if; + else + Phi:=0.6; + end if; + else + Phi:=phi; + end if; + + if (gamma = undefined) then + if (nsub > 0.0) then + Gamma:=sqrt(2.0*epsSi*echarge*nsub)/cox; + else + Gamma:=0.0; + end if; + else + Gamma:=gamma; + end if; + + nss:=nss*1.0e4; -- Scale to SI + ngate:=gamma*1.0e4; -- Scale to SI + + leff:=length-2.0*ld; + if leff>0.0 then + Sigma:= eta * 8.15e-22/(cox*leff*leff*leff); + else + Sigma:=0.0; + end if; + + if nsub>0.0 then -- N.B. nsub was scaled, above. + xd:=sqrt(2.0*epsSi/(echarge*nsub)); + else + xd:=0.0; + end if; + + if (nfs>0.0) and(cox>0.0) then + qnfscox:=echarge*nfs/cox; + else + qnfscox:=0.0; + end if; + + if cox>0.0 then + fn:=delta*pi*epsSi*0.5/(cox*width); + else + fn:=delta*pi*epsSi*0.5*tox/epsSiO2; + end if; + + --Scale beta and convert cox from Fm^-2 to F + beta:=beta*width/leff; + cox:=cox*width*leff; + + Initialized <= true; + end if; -- not initialized + + Vds:=channel*Vdsq; + if Vds>=0.0 then + Vgs:=channel* Vgsq; + Vbs:=channel* Vbsq; + forward:=1.0; + else + Vds:=-Vds; + Vgs:=channel* Vgsq; + Vbs:=channel* Vbsq; + forward:=-1.0; + end if; + + if Vbs<=0.0 then + A:=Phi-Vbs; + D:=sqrt(A); + else + D:=2.0*sqrt(Phi)*Phi/(2.0*Phi+Vbs); + A:=D*D; + end if; + + Vfb:=Vt-Gamma*sqrt(Phi)-Sigma*Vds; + if (xd=0.0) OR (xj=0.0) then + fshort:=1.0; + else + wp:=xd*D; + wc:=0.0631353*xj+0.8013292*wp-0.01110777*wp*wp/xj; + sqwpxj:=sqrt(1.0-(wp*wp/((wp+xj)*(wp+xj)))); + fshort:=1.0-((ld+wc)*sqwpxj-ld)/leff; + end if; + + vbulk:=Gamma*fshort*D+fn*A; + if nfs=0.0 then + delv:=0.0; + else + delv:=kTQ*(1.0+qnfscox+vbulk*0.5/A); + end if; + + vth:=Vfb+vbulk; + Vgstos:=Vgs-Vfb; + + if (vgs-vth > delv) then + Vgst:=Vgs-vth; + else + Vgst:= delv; + end if; + + if (vgs>=vth) or (delv/=0.0) then + + if (Vbs<=0.0) or (Phi /= 0.0) then + B:=0.5*Gamma/D+fn; + else + B:=fn; + end if; + + mobdeg:=1.0/(1.0+theta*Vgst); + + if (vmax /=0.0) then + Ueff:=u0*mobdeg; + Tau:=Ueff/Leff*vmax; + else + Tau:=0.0; + end if; + + Vsat:=Vgst/(1.0+B); + Vsat:=Vsat*(1.0-0.5*Tau*Vsat); -- not quite the same as SPICE + if (vds<Vsat) then + Vpp:=vds; + else + Vpp:= Vsat; + end if; + + fdrain:=1.0/(1.0+Tau*Vpp); + if (Vgs<vth+delv) and (nfs>0.0) then + stfct:=exp((Vgs-vth-delv)/delv); + else + stfct:=1.0; + end if; + + if Vds>=Vsat then + if (kappa>0.0) and (xd>0.0) then + + if vmax=0.0 then + deltal:=sqrt(kappa*xd*xd*(Vds-Vsat)); + else + dcrit:=(xd*xd*vmax*0.5)/(Ueff*(1.0-fdrain)); + + deltal:=sqrt(kappa*xd*xd*(Vds-Vsat)+dcrit*dcrit)-dcrit; + end if; + + if deltal<=0.5*Leff then + C:=Leff/(Leff-deltal); + else + C:=4.0*deltal/Leff; + end if; + + else + C:=1.0; + end if; + + else + C:=1.0; + end if; + + It:=Vgst-Vpp*(1.0+B)*0.5; + Beta:=Beta*mobdeg; + Ids:=Beta*Vpp*It*C*fdrain*stfct; + else + -- Cutoff + Ids:=0.0; + end if; -- vgs >= vth + + if Cox /= 0.0 then + --Charges + if Vgs<=vth then + if Gamma /= 0.0 then + if Vgstos < -A then + Qg:=Cox*(Vgstos+A); -- Accumulation + else + Qg:=0.5*Gamma*Cox*(sqrt(4.0*(Vgstos+A)+Gamma*Gamma-Gamma)); + end if ; -- vgstos <-A + else-- Gamma = 0.0 + Qg:=0.0; + end if; -- gamma /= 0 + Qb:=-Qg; + Qc:=0.0; + else + -- depletion mode: + R:=(1.0+B)*Vpp*Vpp/(12.0*It); + Qg:=Cox*(Vgstos-Vpp*0.5+R); + Qc:=-Cox*(Vgst+(1.0+B)*(R-Vpp*0.5)); + Qb:=-(Qc+Qg); + end if; + + else + Qg:=0.0; + Qc:=0.0; + Qb:=0.0; + end if; -- cox /= 0 + + -- equations for charges (in a procedural we have assignments to + --quantitites): + Qcq := Qc; + Qgq := Qg; + Qbq := Qb; + + -- equations for currents: + Idq := channel*forward*Ids+channel*xqc*Qc'dot; + Igq := channel*Qg'dot; + Ibq := channel*Qb'dot; + Isq := -Idq - Igq - Ibq; + + end procedural; +end architecture amos; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test146.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test146.ams new file mode 100644 index 000000000..b4f95a02e --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test146.ams @@ -0,0 +1,113 @@ + +-- Copyright (C) 1998-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test146.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +--------------------------------------------------------------------- +-- Title : Half Wave Rectifier (Behavioral) +-- Project : Mixed signal simulation +---------------------------------------------------------------------- +-- File : hwr.vhd (Behavioral) +-- Author(s) : Vasudevan Shanmugasundaram(vasu@ececs.uc.edu) +-- Created : jan 16 1998 +-- Last modified : jan 16 1998 +---------------------------------------------------------------------- +-- Description : +-- Behavioral description of a half wave rectifier circuit in VHDL-AMS +---------------------------------------------------------------------- +-- Modification history : +-- 21.11.1997 : created +---------------------------------------------------------------------- +-- T1 diode D T2 +-- o-----|>|-----o-------o The circuit comprises: +-- | | i) A diode . +-- ( ) >R=100ohms ii) A sinusoidal voltage source. +-- |Vs = 5sinwt > iii)A resistor R. +-- | > +-- |_____________|_______o +-- |gnd +-- ----- +---------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH Ground reference; + FUNCTION SIN (X : real ) RETURN real; + FUNCTION COS (X : real ) RETURN real; + FUNCTION EXP (X : real ) RETURN real; +END PACKAGE electricalSystem; + +---------------------------------------------------------------------- + +USE work.electricalSystem.all; + +--entity declaration +ENTITY hwr IS +END hwr; + +--architecture declaration +ARCHITECTURE behavior OF hwr IS + + terminal t1, t2 : electrical; + quantity vDiode across iDiode through t1 TO t2; + quantity v2 across i2 through t2 TO electrical'reference; + quantity vs across t1 TO electrical'reference; + + CONSTANT saturation_current : real := 0.0000000000001; + CONSTANT Vt : real := 0.025; + + CONSTANT BV : real := 100.0; + CONSTANT neg_sat : real := -saturation_current; + +BEGIN -- behavior + + --diode equations + if( vDiode >= (-1.0 * Vt)) USE + + eqn1_1: iDiode == saturation_current * (exp(vDiode/Vt) - 1.0); + --eqn1_1: iDiode == 100.0 * exp(vDiode); + + ELSIF ((vDiode < (-3.0 * Vt)) AND (vDiode > -BV)) use + + eqn1_2: iDiode == neg_sat; + ELSE + + eqn1_3: iDiode == neg_sat * (exp(-(BV + vDiode)/Vt) - 1.0 + + saturation_current); + END USE ; + + --resistor equation + eqn2: v2 == 100.0 * i2; + + --voltage source equation + eqn4: vs == 5.0 * sin(2.0 * 3.14 * 100000.0 * + real(time'pos(now)) * 1.0e-15 ); + +END behavior ; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test147.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test147.ams new file mode 100644 index 000000000..0e077185f --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test147.ams @@ -0,0 +1,75 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test147.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test147.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- this checks for the corect implementation of the 'dot'dot and negation +-- operator implementation for simple simulataeous statements. +---------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity V1 across I1 through T1 to T2; +quantity V2: real; +quantity V3: real; +quantity VS across Isource through T1; + +begin + +--e1: I1 == V1'dot * 1.0; +--e2: V2 == VS'dot'dot; +e3: V3 == VS'dot; +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); +e4: V2 == -V3; +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test148.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test148.ams new file mode 100644 index 000000000..4645a85ac --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test148.ams @@ -0,0 +1,91 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test148.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test148.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +-- Last modified : +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks for the correctness of the quantity, terminal, nature +-- and package declarations. the terminals are assigned as terminals. +-- a simple V-R circuit is considered. +----------------------------------------------------------------------- + +PACKAGE electricalsystem IS + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + +NATURE electrical IS real ACROSS real THROUGH ; --ground reference; + +END PACKAGE electricalsystem; +use work.electricalsystem.all; + +ENTITY test IS + PORT (TERMINAL p: electrical); +END ENTITY test; + +architecture atest of test is +quantity vr across ir through p; +begin +e2: vr== ir*10.0; +end architecture atest; + +use work.electricalsystem.all; + +entity res is +end res; + +ARCHITECTURE ares OF res IS + component test is + port(terminal p:electrical); + end component; + for all : test use entity work.test(atest); + terminal x:electrical; + constant freq: real:=10000.0; + quantity v across i through x; +BEGIN +r1: test port map(p => x); +e1: v == 5.0 * sin(2.0 * 3.14159 * freq * real(time'pos(now))*1.0e-12); +END ARCHITECTURE ares; + diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test149.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test149.ams new file mode 100644 index 000000000..e2b121131 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test149.ams @@ -0,0 +1,113 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test149.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test149.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple resistor model... +-- the test is done for checking the correct implementation of the +-- componet declaration. The model consists of 2 resistor models which are +-- instantiated. + +package electricalSystem is + NATURE electrical IS real ACROSS real THROUGH Ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalsystem.all; + +entity test1 is + port (terminal P, N : electrical ); +end entity test1; + +architecture behav of test1 is + quantity Vt1 across It1 through P to N; +begin + res1 : Vt1 == It1 * 10.0 ; +end architecture behav; + +use work.electricalsystem.all; +entity test2 is + port (terminal P, N : electrical ); +end test2; + +architecture behav of test2 is + quantity Vt2 across It2 through P to N; +begin + res1 : Vt2 == It2 * 100.0 ; +end behav; + + +use work.electricalsystem.all; + +entity resistor_ckt is +end resistor_ckt; + +architecture ares_ckt of resistor_ckt is + + component test1 is + port (terminal P, N : electrical ); + end component; + + component test2 is + port (terminal P, N : electrical ); + end component; + + for all : test1 use entity work.test1(behav); + for all : test2 use entity work.test2(behav); + + terminal a,b,c,t1,t2 : electrical; + quantity vout across iout through t2 to electrical'reference; + quantity vs across a to electrical'reference; + +begin + e1 : test1 port map (P => a, N => b); + e2 : test2 port map (P => b, N => c); + e3 : vout == iout * 1200.0; + e4 : test1 port map (P => c, N => t1); + e5 : test1 port map (P => t1, N => t2); + source : vs == 5.0 * sin(2.0 * 3.1415 * 10000.0* real(time'pos(now)) * 1.0e-12); +end architecture ares_ckt; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test150.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test150.ams new file mode 100644 index 000000000..e36261f0a --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test150.ams @@ -0,0 +1,75 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test150.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test150.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple RC model... +-- the test is done for checking the correct implementation +-- of the simple simultaneous equation statement with 'dot expression on +-- RHS. it checks nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity V1 across I1 through T1 to T2; +quantity V2 across I2 through T2; +quantity VS across T1; + +begin + +e1: V1 == I1*10.0; +e2: I2 == 1.0e-12*V2'dot; + +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test151.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test151.ams new file mode 100644 index 000000000..cbdb39031 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test151.ams @@ -0,0 +1,76 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test151.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test151.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple resistor model...2 resistors in parallel +-- the test is done for checking the correct implementation of the simple +-- simultaneous equation statement with multiple expressions o RHS. +-- It checks nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1:electrical; +quantity V1 across I1 through T1 to electrical'reference; +quantity V2 across I2 through T1 to electrical'reference; +quantity VS across T1; +quantity I12 : real; +begin + +e1: V1 == I1*10.0; +e2: V2 == I2*10.0; +e3: I12 == I1+I2; + +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test152.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test152.ams new file mode 100644 index 000000000..533f315b5 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test152.ams @@ -0,0 +1,75 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test152.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test150.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple RC model... +-- the test is done for checking the correct implementation +-- of the simple simultaneous equation statement with 'dot expression on +-- RHS. it checks nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity V1 across I1 through T1 to T2; +quantity V2 across I2 through T2; +quantity VS across T1; + +begin + +e1: V1 == I1*10.0; +e2: I2 == V2'dot*1.0e-12; + +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test153.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test153.ams new file mode 100644 index 000000000..d7f05e578 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test153.ams @@ -0,0 +1,79 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test153.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +---------------------------------------------------------------------- +-- File : test153.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple model which has a voltage source. +-- The output voltage Vout is dependent on the value of vS at that point +-- of time. If the voltage is below Vref, the output is a 1 else output is +-- a 0. the test is done for checking the correct implementation of the +-- simple simultaneous if statement.it checks nature declaration, terminal +-- and quantity declarations. + + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity VS across T1; +quantity Vout: real; +constant Vref:real:=5.0; +begin + +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +if (VS <= Vref) use +e1: Vout == 1.0; +else +e2: Vout == 0.0; +end use; + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test154.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test154.ams new file mode 100644 index 000000000..2199502b1 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test154.ams @@ -0,0 +1,79 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test154.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test154.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple model which has a voltage source. +-- The output voltage Vout is dependent on the value of VS wrt Vref +-- If the voltage is below Vref, the output is a 0 else output is a 1. +-- the test is done for checking the correct implementation +-- of the simple simultaneous if statement.it checks +-- nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity VS across T1; +quantity Vout: real; +constant Vref:real:=5.0; +begin + +esource: VS == 5.0; + +if (VS<=Vref) use +e1: Vout == 1.0; +else +e2: Vout == 0.0; +end use; + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test155.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test155.ams new file mode 100644 index 000000000..9843d2c27 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test155.ams @@ -0,0 +1,81 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test155.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test155.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple model which has a voltage source. +-- The output voltage Vout is dependent on the value of VS wrt Vref +-- If the voltage is above/below Vref, the output is a 0 else output is a +-- 1. the test is done for checking the correct implementation of the +-- simple simultaneous if statement with multiple if conditions.it checks +-- nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity VS across T1; +quantity Vout: real; +constant Vref:real:=5.0; +begin + +esource: VS == 5.0; + +if (VS<Vref) use +e1: Vout == 0.0; +elsif (VS=Vref) use +e2: Vout == 1.0; +else +e3: Vout == 0.0; +end use; + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test156.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test156.ams new file mode 100644 index 000000000..8837429f1 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test156.ams @@ -0,0 +1,108 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test156.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +-- check the implemetatio of ports and generics. + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity inv is + port ( + x : in bit; + xout : out bit); +end inv; + +architecture inverter of inv is +begin + + xout <= not x after 100ns ; + +end inverter ; + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND reference; + FUNCTION SIN (X : real ) RETURN real; + FUNCTION EXP (X : real ) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; + +entity resistor is + generic ( res : real := 10.0 ) ; + port (terminal P, N : electrical ); +end resistor; + +architecture behav of resistor is + quantity VPTON across IPTON through P to N; +begin + res1 : VPTON == IPTON * res ; +end behav; + +use work.electricalSystem.all; + +ENTITY circuit1 IS +END circuit1; + +ARCHITECTURE behavior OF circuit1 IS + component inv is + port ( + x : in bit; + xout : out bit); + end component ; + for all : inv use entity work.inv(inverter) ; + + component resistor is + generic ( res : real := 10.0 ) ; + port (terminal P, N : electrical ); + end component; + for all : resistor use entity work.resistor(behav); + + terminal n1,n2 : electrical; + QUANTITY vIn ACROSS iIn THROUGH n1 ; + + signal y:bit:='0'; + +BEGIN + + D2 : inv port map(x=>y, xout=>y); + + testbench:PROCESS + BEGIN + WAIT ON y; + END PROCESS; + + R1 : resistor generic map ( res => 500.0) port map (P => n1, N => n2); + R2 : resistor port map (P => n2, N => ground); + vsource: vIn == 5.0 * sin(2.0 * 3.14 * 100000.0 * real(time'pos(now)) * 1.0e-15); + +END ARCHITECTURE behavior; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test157.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test157.ams new file mode 100644 index 000000000..f13d5c47b --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test157.ams @@ -0,0 +1,108 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test157.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +-- check the implemetation of ports and generics. + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +--entity inv is +-- port ( +-- x : in bit; +-- xout : out bit); +--end inv; + +--architecture inverter of inv is +--begin + +-- xout <= not x after 100ns ; + +--end inverter ; + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND reference; + FUNCTION SIN (X : real ) RETURN real; + FUNCTION EXP (X : real ) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; + +entity resistor is + generic ( res : real := 10.0 ) ; + port (terminal P, N : electrical ); +end resistor; + +architecture behav of resistor is + quantity VPTON across IPTON through P to N; +begin + res1 : VPTON == IPTON * res ; +end behav; + +use work.electricalSystem.all; + +ENTITY circuit1 IS +END circuit1; + +ARCHITECTURE behavior OF circuit1 IS +-- component inv is +-- port ( +-- x : in bit; +-- xout : out bit); +-- end component ; +-- for all : inv use entity work.inv(inverter) ; + + component resistor is + generic ( res : real := 10.0 ) ; + port (terminal P, N : electrical ); + end component; + for all : resistor use entity work.resistor(behav); + + terminal n1,n2 : electrical; + QUANTITY vIn ACROSS iIn THROUGH n1 ; + +-- signal y:bit:='0'; + +BEGIN + +-- D2 : inv port map(x=>y, xout=>y); + +-- testbench:PROCESS +-- BEGIN +-- WAIT ON y; +-- END PROCESS; + + R1 : resistor generic map ( res => 500.0) port map (P => n1, N => n2); + R2 : resistor port map (P => n2, N => ground); + vsource: vIn == 5.0 * sin(2.0 * 3.14 * 100000.0 * real(time'pos(now)) * 1.0e-15); + +END ARCHITECTURE behavior; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test161.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test161.ams new file mode 100644 index 000000000..1a0542e97 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test161.ams @@ -0,0 +1,74 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test161.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +---------------------------------------------------------------------- +-- File : test150.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple RC model... +-- the test is done for checking the correct implementation +--of the simple simultaneous equation statement with 'dot expression on RHS. +--it checks nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity V1 across I1 through T1 to T2; +quantity V2 across I2 through T2; +quantity VS across T1; + +begin + +e1: V1 == I1*10.0; +e2: V2 == I1'integ/1.0e-12; + +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test162.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test162.ams new file mode 100644 index 000000000..dbc7b3bac --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test162.ams @@ -0,0 +1,74 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test162.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test147.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- this checks for the corect implementation of the 'dot'dot and negation +-- operator implementation for simple simulataeous statements +---------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity V1 across I1 through T1 to T2; +quantity V2: real; +quantity i2 :real; +quantity VS across Isource through T1; + +begin + +e1: I1 == V1'dot*1.0e-15; +e2: V2 == V1'dot; +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test163.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test163.ams new file mode 100644 index 000000000..034a02a4b --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test163.ams @@ -0,0 +1,80 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test163.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +---------------------------------------------------------------------- +-- File : test162.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple rc model...with 2 res in parallel connected thru a capacitor +-- -------------||----- +-- | | +-- | R | R +-- -------------------- +-- the test is done for checking the correct implementation +-- of the simple simultaneous equation statement.it checks +-- nature declaration, terminal, 'dot and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity VR1 across IR1 through T1; +quantity VC across IC through T1 to T2; +quantity VR2 across IR2 through T2; +quantity VS across T1; + +begin + +e1: VR1 == IR1*100.0; +e2: IC == VC'dot *1.0e-12; +e3: VR2 == IR2*10.0; + +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test164.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test164.ams new file mode 100644 index 000000000..ca33cd6e2 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test164.ams @@ -0,0 +1,81 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test164.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test164.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple rc model...with 2 res in parallel connected thru a capacitor +-- -------------||----- +-- | | +-- | R | R +-- -------------------- +-- the test is done for checking the correct implementation of the simple +-- simultaneous equation statement.it checks nature declaration, terminal, +-- 'dot, 'integ and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity VR1 across IR1 through T1; +quantity VC across IC through T1 to T2; +quantity VR2 across IR2 through T2; +quantity VS across T1; + +begin + +e1: VR1 == IR1*100.0; +e2: IC == VC'dot *1.0e-12; +e3: VR2 == IR2*10.0; +e4: VC == IC'integ/1.0e15 +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test165.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test165.ams new file mode 100644 index 000000000..d3fd1b0ff --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test165.ams @@ -0,0 +1,79 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test165.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distributed Processing Laboratory +-- University of Cincinnati +---------------------------------------------------------------------- +-- File : test164.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple rl model... +-- -----^^^------------- +-- R | > +-- | L > R +-- -------------------- +-- the test is done for checking the correct implementation +-- of the simple simultaneous equation statement.it checks +-- nature declaration, terminal, 'dot, and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity VR1 across IR1 through T1 to T2; +quantity VL across IL through T2; +quantity VR2 across IR2 through T2; +quantity VS across T1; + +begin + +e1: VR1 == IR1*10.0; +e2: VL == IL'dot *1.0; +e3: VR2 == IR2*10.0; +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test166.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test166.ams new file mode 100644 index 000000000..d84a804c0 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test166.ams @@ -0,0 +1,79 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test166.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +---------------------------------------------------------------------- +-- File : test166.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple rl model... +-- -----^^^------------- +-- R | > +-- | L > R +-- -------------------- +-- the test is done for checking the correct implementation +--of the simple simultaneous equation statement.it checks +--nature declaration, terminal, 'dot,'integ and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity VR1 across IR1 through T1 to T2; +quantity VL across IL through T2; +quantity VR2 across IR2 through T2; +quantity VS across T1; + +begin + +e1: VR1 == IR1*10.0; +e2: VL == IL'dot *1.0; +e3: VR2 == IR2*10.0; +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); +e4: IL== 1.0* VL'integ; +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test167.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test167.ams new file mode 100644 index 000000000..def01db8b --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test167.ams @@ -0,0 +1,80 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test167.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +---------------------------------------------------------------------- +-- File : test167.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- An RC model... +-- the test is done for checking the correct implementation of the simple +-- simultaneous equation statement.it checks nature declaration, terminal, +-- 'dot, 'integ and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2, T3, T4:electrical; +quantity V1 across I1 through T1 to T2; +quantity V2 across I2 through T2 to T3; +quantity VC across IC through T3; +quantity VC1 across IC1 through T2 to T4; +quantity V3 across I3 through T4; +quantity VS across T1; + +begin + +e1: V1 == I1*1.0; +e2: V2 == I2*1.0; +e3: V3 == I3*10.0; +e4: IC == VC'dot*1.0e-12; +e5: IC1 == VC1'dot*1.0e-12; + +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test168.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test168.ams new file mode 100644 index 000000000..bf9e9af81 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test168.ams @@ -0,0 +1,80 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test168.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +---------------------------------------------------------------------- +-- File : test168.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- An RC model... +-- the test is done for checking the correct implementation +--of the simple simultaneous equation statement.it checks +--nature declaration, terminal, 'dot, 'integ and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2, T3, T4:electrical; +quantity V1 across I1 through T1 to T2; +quantity V2 across I2 through T2 to T3; +quantity VC across IC through T3; +quantity VC1 across IC1 through T2 to T4; +quantity V3 across I3 through T4; +quantity VS across T1; + +begin + +e1: V1 == I1*1.0; +e2: V2 == I2*1.0; +e3: V3 == I3*10.0; +e4: VC == IC'integ*1.0e12; +e5: VC1 == IC1'integ*1.0e12; + +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test169.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test169.ams new file mode 100644 index 000000000..18804f48f --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test169.ams @@ -0,0 +1,143 @@ + +-- Copyright (C) 1999-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test169.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +----------------------------------------------------------------------------- +-- Ebers-moll Model for a transistor -- +-- VHDL-AMS Implementation -- +-- Developed at the Distributed Processing Lab at the University -- +-- of Cincinnati -- +-- by VishwaShanth Kasula on May 10, 1999 -- +-------------------------------------------------------------------- +-- Circuit Topology -- +-- BJT Ebers-Moll static model +-- Testbench Ckt to evaluate the DC operatioing point of an npn BJT, +-- Sedra smith page no. 152, fig 4.9 +-------------------------------------------------------------------- + +-- Three regions are simulated +-- Active region, vbb = 4.0 V +-- Saturation region, vbb = 6.0 V +-- Cutoff region, vbb = 0.0; + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalsystem.all; + +entity bjt_npn is + generic(isat : real := 1.0e-16; -- Saturation Current + bf : real := 100.0; -- Ideal maximus forward current + br : real := 1.0; -- ideal maximum reverse current + rb : real := 1.0e-5; -- Base resistance + rc : real := 1.0e-5; -- collector resistance + re : real := 1.0e-5; -- emmiter resistance + vaf : real := 100.0); -- Forward Early Voltage + port(terminal e,b,c : electrical); +end bjt_npn; + +architecture structure of bjt_npn is + terminal b1, c1, e1 : electrical; + quantity vbo across ib through b to b1; + quantity vco across ic through c to c1; + quantity veo across ie through e to e1; + quantity vct across Ict through c1 to e1;--current source + quantity vbe across ibe through b1 to e1; + quantity vbc across ibc through b1 to c1; + quantity vce : real := 1.0; -- used to calculate VCE + constant gmin : real := 1.0e-12; -- condutsnce in parallel with every pn junction + constant vt : real := 0.02589; -- thermal voltage + +begin + brk : break vbe => 1.0, vbc => -1.0; + + diodecond1 : if(vbe > -5.0*vt) use + diodebef : ibe == ((isat*(exp(vbe/vt) - 1.0)) + (gmin*vbe))/bf; + elsif (vbe <= -5.0*vt ) use + diodeber: ibe == ((-1.0*isat) + (gmin*vbe))/bf; + end use; + diodecond2 : if(vbc > -5.0*vt) use + diodebcf : ibc == ((isat*(exp(vbc/vt) - 1.0)) + (gmin*vbc))/br; + elsif(vbc <= -5.0*vt) use + diodebcr : ibc == ((-1.0*isat) + (gmin*vbc))/br; + end use; + bres : vbo == ib * 1.0e-6; + cres : vco == ic * 1.0e-6; + eres : veo == ie * 1.0e-6; + kcl_eqn : ie == -1.0*(ib + ic); + vcevolt : vce == vbe - vbc; + ictdep : Ict == ((Ibe*bf) - (Ibc*br)) * (1.0 -(vbc/vaf)); + +end architecture structure; + + +--***************************************************** +--TEST BENCH +use std.textio.all; +use work.electricalsystem.all; + +entity bjt_testbench is +end bjt_testbench; + +architecture structure of bjt_testbench is + terminal t1, t2, t3, t4 : electrical ; + component bjt_npn_comp + generic(isat : real := 1.0e-16; -- Saturation Current + bf : real := 100.0; -- Ideal maximus forward current + br : real := 1.0; -- ideal maximum reverse current + rb : real := 1.0e-5; -- Base resistance + rc : real := 1.0e-5; -- collector resistance + re : real := 1.0e-5; -- emmiter resistance + vaf : real := 100.0); -- Forward Early Voltage + port(terminal e,b,c : electrical); + end component; + for all : bjt_npn_comp use entity work.bjt_npn(structure); + + quantity vcc across icc through t1 to electrical'reference; + quantity vrc across irc through t1 to t2; + quantity vbb across ibb through t3 to electrical'reference; + quantity vre across ire through t4 to electrical'reference; + +begin + + bjt : bjt_npn_comp + generic map (isat => 1.8104e-15, vaf => 100.0) + port map(t4,t3,t2); + emres : vre == ire * 3.3e3; + ccurr : vcc == 10.0; + ecurr : vbb == 6.0; + cores : vrc == irc * 4.7e3; + +end architecture structure; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test170.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test170.ams new file mode 100644 index 000000000..ab30845f0 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test170.ams @@ -0,0 +1,85 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test170.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +---------------------------------------------------------------------- +-- File : test106.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple resistor model... +-- the test is done for checking the correct implementation +-- of the simple simultaneous equation statement.it checks +-- nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2, T3, T4,T5,T6:electrical; +quantity VRgen across IRgen through T1 to T2; +quantity VLgen across ILgen through T2 to T3; +quantity VRin across IRin through T3; +quantity VR1 across IR1 through T4 to T5; +quantity VR1A across IR1A through T4 to T6; +quantity VC1A across IC1A through T6 to T5; +quantity VC1 across IC1 through T5; +quantity VS across T1; +constant C1: real:=3.5e-3; +constant C1A: real:=0.3e-3; +begin + +e1: VRgen == IRgen*10.0; +e2: VLgen == 0.5*ILgen'dot; +e3: VRin == IRin*500.0; +e4: VR1 == IR1*1.0; +e5: VR1A == IR1A*0.2; +e6: VC1 == C1 /IC1'integ; +e7: VC1A == C1A/IC1A'integ; + +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test172.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test172.ams new file mode 100644 index 000000000..d000ef44a --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test172.ams @@ -0,0 +1,97 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test172.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +---------------------------------------------------------------------- +-- File : test172.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test is done for checking the correct implementation +-- of the simultaneous if equation statement.it checks +-- nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +port (input: in bit; + output: out bit); +end entity; + +architecture atest of test is +terminal t1, t2: electrical; +quantity v1 across i1 through t1 to t2; +quantity v2 across t2; +begin + +e1: v1== 1.0; +e2: v2==0.0; + + if (v1==1.0) use + output <= '1'; + else + output <='0'; + end use; + + if (v2==2.0) use + output <='0'; + else + output <='1'; + end use; +end architecture atest; +use work.electricalSystem.all; +--entity tb is +--port (tinput: in bit; +-- toutput: out bit); +--end entity; +--architecture atb of tb is +--terminal tt1, tt2: electrical; +--quantity tv1 across ti1 through tt1 to tt2; +--quantity tv2 across tt2; +--begin + +--tv1==1.0; +--tv2==0.0; + +--end architecture atb; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test173.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test173.ams new file mode 100644 index 000000000..9dc65ca45 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test173.ams @@ -0,0 +1,76 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test173.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +---------------------------------------------------------------------- +-- File : test173.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test is done for checking the correct implementation +-- of the simultaneous if equation statement.it checks +-- nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal t1, t2: electrical; +quantity v1 across i1 through t1 to t2; +quantity v2 across t2; + +begin +e1: v1== 1.0; +e2: v2==0.0; + + if (v1==1.0) use + output <= '1'; + end use; + + if (v2==2.0) use + output <='1'; + end use; +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test174.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test174.ams new file mode 100644 index 000000000..a262a8e6c --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test174.ams @@ -0,0 +1,90 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test174.ams,v 1.1 2002-03-27 22:11:20 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +---------------------------------------------------------------------- +-- File : test174.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple resistor model... +-- the test is done for checking the correct implementation +--of the simultaneous case statement.it checks +--nature declaration, terminal and quantity declarations + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH Ground reference ; + FUNCTION SIN (X : real ) RETURN real; + FUNCTION EXP (X : real ) RETURN real; +END PACKAGE electricalSystem; + +USE work.electricalSystem.all; + +ENTITY simcase IS +END simcase; + +ARCHITECTURE asimcase OF simcase IS + + terminal T1, T2 : electrical; + + quantity v1 across i1 through T1 ; + quantity v2 across i2 through T1 to T2; + quantity v3 across i3 through T2 ; + +BEGIN + + eqn1 : v1 == 1.0; + +c1: case (v1*2.0) use + + when (2.0) => + v2 == i2 * 100.0; + v3 == i3 * 100.0; + when (6.0) => + v2 == i2 * 200.0; + v3 == i3 * 200.0; + when (10.0) => + v2 == i2 * 300.0; + v3 == i3 * 300.0; + when others => + v2 == i2 * 400.0; + v3 == i3 * 400.0; + end case c1; + +END asimcase ; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test175.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test175.ams new file mode 100644 index 000000000..4db174b60 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test175.ams @@ -0,0 +1,87 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test175.ams,v 1.1 2002-03-27 22:11:20 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +---------------------------------------------------------------------- +-- File : test175.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test is done for checking the correct implementation +-- of the simultaneous case statement.it checks +-- nature declaration, terminal and quantity declarations + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH Ground reference ; + FUNCTION SIN (X : real ) RETURN real; + FUNCTION EXP (X : real ) RETURN real; +END PACKAGE electricalSystem; + + +USE work.electricalSystem.all; + +ENTITY simcase IS +END simcase; + +ARCHITECTURE asimcase OF simcase IS + + terminal T1, T2 : electrical; + + quantity v1 across i1 through T1 ; + quantity v2 across i2 through T1 to T2; + quantity v3 across i3 through T2 ; + +BEGIN + + eqn1 : v1 == 1.0; + eqn2 : v2 == 2.0; +c1: case (v1*2.0) use + + when (2.0) use + if (v2==2.0) use + v2 == i2 * 100.0; + else + v2 ==i2*10.0; + end use; + when (6.0) use + v2 == i2 * 200.0; + when (10.0) use + v2 == i2 * 300.0; + end case c1; +END asimcase ; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test176.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test176.ams new file mode 100644 index 000000000..90fd6535e --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test176.ams @@ -0,0 +1,80 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test176.ams,v 1.1 2002-03-27 22:11:20 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +---------------------------------------------------------------------- +-- File : test176.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test is done for checking the correct implementation +--of the simultaneous null statement.it checks +--nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity V1 across I1 through T1 to T2; +quantity V2 across I2 through T2; +--quantity V3 across I3 through T2; +quantity VS across T1; + +begin + + V1==1.0; + if (V1<=1.1) use + NULL; + else + V2 == 1.0; + end use; + + +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; + diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test182.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test182.ams new file mode 100644 index 000000000..ee24ac1e1 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test182.ams @@ -0,0 +1,71 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test182.ams,v 1.1 2002-03-27 22:11:20 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +---------------------------------------------------------------------- +-- File : test182.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test is done for checking the correct implementation +-- of the 'above attribute. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN (X : real ) RETURN real; + FUNCTION EXP (X : real ) RETURN real; +END PACKAGE electricalSystem; + + +USE work.electricalSystem.all; + +entity test is +port(signal vout:out boolean); +end entity; + +architecture atest of test is + +terminal T1: electrical; +quantity vin across iin through T1; +--constant vt: real:=3.0; +begin +e2 : vout <= vin'above(0.0); +e1: vin == 5.0 * sin(2.0 *3.141592 *100000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test183.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test183.ams new file mode 100644 index 000000000..f0ea59d1c --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test183.ams @@ -0,0 +1,60 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test183.ams,v 1.1 2002-03-27 22:11:20 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +-- this model tests for the correst implementation of the 'above +-- statement. +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH; + FUNCTION SIN(X : real) RETURN real; + alias ground is electrical'reference; +END PACKAGE electricalSystem; + +use work.electricalsystem.all; + +entity product is +generic(bound:real:=1.0); +port( + quantity out1:real); +end product; + +architecture pro of product is +constant in1:real:=10.0; +constant in2:real:=1.0; +signal outofbound:out boolean; + +begin + outofbound<=true; + out1== in1*in2; + outofbound<=out1'above(bound); + +end pro; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test184.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test184.ams new file mode 100644 index 000000000..300528f86 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test184.ams @@ -0,0 +1,109 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test184.ams,v 1.1 2002-03-27 22:11:20 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +--------------------------------------------------------------------- +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +---------------------------------------------------------------------- +-- File : test100.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- half wave Rectifier model ... +-- the test is done for checking the correct implementation +-- of the simultaneous if statement.it checks +-- nature declaration, terminal and quantity declarations. + +---------------------------------------------------------------------- +-- T1 diode D T2 +-- o-----|>|-----o-------o The circuit comprises: +-- | | i) A diode . +-- ( ) >R=100ohms ii) A sinusoidal voltage source. +-- |Vs = 5sinwt > iii)A resistor R. +-- | > +-- |_____________|_______o +-- |gnd +-- ----- +---------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH; + FUNCTION SIN (X : real ) RETURN real; + FUNCTION EXP (X : real ) RETURN real; +END PACKAGE electricalSystem; + +---------------------------------------------------------------------- + +USE work.electricalSystem.all; + +ENTITY hwr IS +END hwr; + +ARCHITECTURE ahwr OF hwr IS + + terminal T1, T2 : electrical; + quantity VDiode across IDiode through T1 to T2; + quantity V2 across I2 through T2 to electrical'reference; + quantity VS across T1 to electrical'reference; + + CONSTANT saturation_current : real := 0.0000000000001; + CONSTANT Vt : real := 0.025; + + CONSTANT BV : real := 100.0; + CONSTANT neg_sat : real := -saturation_current; + +BEGIN + + --diode equations + if( vDiode >= (-1.0 * Vt)) USE + eq1: iDiode == saturation_current * (exp(vDiode/Vt) - 1.0); + + ELSIF ((vDiode < (-3.0 * Vt)) AND (vDiode > -BV)) use + eq2: iDiode == neg_sat; + + ELSE + eq3: iDiode == neg_sat * (exp(-(BV + vDiode)/Vt) - 1.0 + + saturation_current); + END USE ; + + eqn2: v2 == 100.0 * i2; + + eqn4: vs == 5.0 * sin(2.0 * 3.14 * 100000.0 * + real(time'pos(now)) * 1.0e-15 ); + +END ahwr ; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test185.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test185.ams new file mode 100644 index 000000000..6b5abf221 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test185.ams @@ -0,0 +1,56 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test185.ams,v 1.1 2002-03-27 22:11:20 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN (X : real ) RETURN real; + FUNCTION EXP (X : real ) RETURN real; +END PACKAGE electricalSystem; + +USE work.electricalSystem.all; + +ENTITY simcase IS +END simcase; + +ARCHITECTURE asimcase OF simcase IS + + terminal T1: electrical; + + quantity v1 across i1 through T1 ; + +BEGIN + eq1: v1==1.0; + if (v1<=1.0) use + e1: null; + end use; +END asimcase ; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/voltage_doubler.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/voltage_doubler.ams new file mode 100644 index 000000000..4213dbee6 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/voltage_doubler.ams @@ -0,0 +1,227 @@ + +-- Copyright (C) 1997-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: voltage_doubler.ams,v 1.1 2002-03-27 22:11:20 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- Title : Voltage doubler circuit +-- Project : Mixed signal simulation +---------------------------------------------------------------------- +-- File : voltageDoubler.ams +-- Author : Kathiresan Nellayappan <knellaya@ececs.uc.edu> +-- Chandrashekar L Chetput <cchetput@ececs.uc.edu> +-- Created : 26.11.1997 +---------------------------------------------------------------------- +-- Description : +-- VHDL-AMS description of a voltage doubler circuit +-- STRUCTURAL DESCRIPTION. +---------------------------------------------------------------------- +-- +-- The ciruit schematic for the voltage doubler circuit is as below: +-- ================================================================= +-- +-- T1 C1 T2 diode D2 T3 +-- o_________||_____o_____|<|________o_____o_ The circuit comprises: +-- | || | | i)A sinusoidal voltage +-- | 1microF | | source. +-- ( ) __ _____ ii) 2 capacitors. +-- |Vs \/diode ----- C2 = 1microF iii) 2 diodes. +-- |=10sinwt -- D1 | +-- | | | +-- | | | +-- o________________|________________|_____o_ +-- |gnd +-- ----- +-- The diode is modelled as a component and then instantiated twice. +-- The diode model used is a spice behavioral model of a real diode. +-- +---------------------------------------------------------------------- + + +--Package defining eleectrical nature and some functions... +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; + +---------------------------------------------------------------------- +-- The diode component definition..... +USE work.electricalSystem.ALL; + +---------------------------------------------------------------------- +-- Schematic of the diode component: +-- +-- Ta o----|>|----o Tb +-- +---------------------------------------------------------------------- + +ENTITY diodeReal IS + PORT( TERMINAL ta,tb : electrical); +END diodeReal; + + +ARCHITECTURE behavior OF diodeReal IS + + QUANTITY d_V ACROSS d_I THROUGH ta TO tb; + CONSTANT saturation_current : real := 0.0000000000001; + CONSTANT Vt : real := 0.025; + CONSTANT neg_sat : real := -saturation_current; + CONSTANT IBV : real := 0.001; + CONSTANT PI : real := 3.14159_26535_89793_23846; + CONSTANT BV : real := -100.0; + +BEGIN + + IF( d_V >= ((-5.0) * Vt) ) USE + diode1St1: d_I == saturation_current * (exp(d_V/Vt) - 1.0); + ELSIF( (d_V < ((-5.0) * Vt)) AND (d_V > BV)) USE + diode1St2: d_I == neg_sat; + ELSIF(d_V = BV) USE + diode1St3: d_I == -IBV; + ELSE + diode1St4: d_I == neg_sat * (exp((BV + d_V)/Vt) -1.0 +((-BV)/Vt)); + END USE; + +END ARCHITECTURE behavior; + +---------------------------------------------------------------------- +-- The capacitor definition begins..... +USE work.electricalSystem.ALL; +---------------------------------------------------------------------- +-- Schematic of the capacitor component: +-- +-- Ta1 o----||----o Tb1 +-- +---------------------------------------------------------------------- +--entity declaration. +ENTITY capacitor IS + --capacitance value given as a generic parameter. + GENERIC( C : real := 1.0e-6); + PORT( TERMINAL ta1,tb1 : electrical);--Interface ports. +END capacitor; + +--architecture declaration. +ARCHITECTURE capbehavior OF capacitor IS +--quantity declarations. +-- --voltage across and current through the capacitor. + quantity Vc across Ic through ta1 to tb1; + +BEGIN + + Ic == C*Vc'dot; -- The ohmic resistance equation. + +END ARCHITECTURE capbehavior; +---------------------------------------------------------------------- +-- The sinusoidal voltage source definition begins..... +USE work.electricalSystem.ALL; +---------------------------------------------------------------------- +-- Schematic of the sinusoidal voltage source: +-- ------------------------------------------- +-- +-- Ta2 o----(~)----o Tb2 a sinusoidal voltage of amplitude V +-- Vs and frequency 'f'. +---------------------------------------------------------------------- +--entity declaration. +ENTITY sineSource IS + --frequency value and voltage value given as generic parameters. + GENERIC( f : real := 100000.0; + v : real := 10.0 ); + PORT( TERMINAL ta2,tb2 : electrical);--Interface ports. +END sineSource; + +--architecture declaration. +ARCHITECTURE sinebehavior OF sineSource IS +--quantity declarations. + quantity Vsine across Isine through ta2 to tb2; + +BEGIN + + -- The sinusoidal voltage source equation. + vsource: Vsine == V * sin(2.0 * (22.0/7.0) * f * + real(time'pos(now)) * 1.0e-15); + +END ARCHITECTURE sinebehavior; + +---------------------------------------------------------------------- +--The description of the voltage doubler begins here..... + +USE work.electricalSystem.ALL; + +ENTITY voltage_doubler IS +END voltage_doubler; + +ARCHITECTURE vdBehavior OF voltage_doubler IS + + TERMINAL t1, t2, t3 : electrical; + + COMPONENT diodeRealComp + PORT(TERMINAL ta,tb : electrical); + END COMPONENT; + + FOR ALL : diodeRealComp USE ENTITY work.diodeReal(behavior); + + COMPONENT capacitorComp IS + GENERIC( C : real := 1.0e-6); + PORT( TERMINAL ta1,tb1 : electrical); + END COMPONENT; + + FOR ALL : capacitorComp USE ENTITY work.capacitor(capbehavior); + + COMPONENT sineSourceComp IS + GENERIC( f : real := 100000.0; + v : real := 10.0 ); + PORT( TERMINAL ta2,tb2 : electrical); + END COMPONENT; + + FOR ALL : sineSourceComp USE ENTITY work.sineSource(sinebehavior); + + CONSTANT C : real := 0.000001; + CONSTANT MATH_PI : real := 3.14159_26535_89793_23846; + +BEGIN + + C1: capacitorComp + PORT MAP(t1,t2); + + C2: capacitorComp + PORT MAP(t3,ground); + + d1: diodeRealComp + PORT MAP(t2,ground); + + d2: diodeRealComp + PORT MAP(t3,t2); + + vsource: sineSourceComp + PORT MAP(t1,ground); + +END ARCHITECTURE vdBehavior; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/wein_bridge.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/wein_bridge.ams new file mode 100644 index 000000000..5cf47ba8a --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/wein_bridge.ams @@ -0,0 +1,463 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: wein_bridge.ams,v 1.1 2002-03-27 22:11:20 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +-- REMARKS +-- ------- +-- TESTED : Works great for freq of 1.0 KHz - 30.0MHz +-- COMMENTS : The Values of R1_a and R1_b have to be 18.0k & 32.0K resp. +-- The freq. is given by the equation +-- F = 1/(2*PI*R*C) +-- where R=R3=R4 and +-- C=C3=C4. +--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +--************************************************************************* +-- Structural Level Model of a WEIN BRIDGE OSCILLATOR. +-- VHDL-AMS implementation +-- Developed at Distributed Processing Laboratory +-- University of Cincinnati +--************************************************************************* + +--######################################################################### +-- BLOCK DIAGRAM +-- ------------- +-- o V_out +-- | D1 +-- |__________|\_______________ +-- R1_a R1_b | |/ R2=10.0K | +-- -----^^^.^^^---o--------/\/\/\/\-----------| +-- | | T4 |__________/|_______________| +-- ------- | \| | +-- -- | D2 | +-- | |\ | +-- ------------------|-\ | +-- | \____________o T3 +-- | / | +-- -------------------|+/ | +-- | |/ | +-- |T1 T2 | +-- _________o__________||____o_____/\/\/\/\_____| +-- | | || +-- | | C4=16.0pF R4=10.0K +-- | < +-- C3 |16.0pF < R3=10.0K +-- ----- < +-- ----- | +-- | | +-- ------- ------- +-- -- -- +-- +--######################################################################### + + PACKAGE electricalsystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X:real) RETURN real; + FUNCTION COS(X:real) RETURN real; + FUNCTION EXP(X:real) RETURN real; + END PACKAGE electricalsystem; + +------------------------ RESISTOR --------------------------- + +use work.electricalsystem.all; + +entity resistor is + generic(res :real:=1.0 ); + port(terminal r_in,r_out: electrical); +end entity resistor; + +architecture behav of resistor is + quantity vr across ir through r_in to r_out; + +begin + vr==ir*res; +end architecture behav; + +------------------------ CAPACITOR--------------------------- +use work.electricalsystem.all; + +entity capacitor is + generic(cap :real:=1.0); + port(terminal c_in,c_out: electrical); +end entity capacitor; + +architecture behav of capacitor is + +quantity vc across ic through c_in to c_out; +begin + init: break vc=>0.0; + + ic==cap*vc'dot; +end architecture behav; + +---------------------------- Diode ----------------------------- +use work.electricalsystem.all; + +entity diode is +generic ( + Isat : real := 1.0e-14; -- saturatioin current + n : real := 1.0; -- emmission coefficient + bv : real := 1.0; -- reverse breakdown voltage + ibv : real := 1.0e-3; -- Breakdown current + rds : real := 1.0 -- Ohnic resistamce + ); +port (terminal pos, neg : electrical); +end diode; + +architecture behav of diode is + terminal td : electrical; + quantity vd across id through td to neg; + quantity vrd across ird through pos to td; + quantity vdiode : real := 2.0; + constant gmin : real := 1.0e-12; -- conductance + constant vt : real := 0.026; -- thermal voltage +begin -- behav + brk : break vd => 1.0; + diodecondition : if(vd >= -5.0*(vt*n)) use + dfow : id == ((isat*(exp(vd/(vt*n)) - 1.0)) + (gmin*vd)); + elsif(vd < -5.0*(vt*n) and (vd > -1.0*bv)) use + drev: id == ((-1.0*isat) + (gmin*vd)); + elsif vd = -1.0*bv use + dbv : id == -1.0*ibv; + elsif vd < -1.0*bv use + blbv : id == -1.0*Isat*(exp(-1.0*((bv + vd)/vt)) - 1.0 + (bv/vt)); + end use; + diododeres : vrd == ird * rds; + diodevolt : vdiode == vd + vrd; + +end behav; + +-------------------- NPN transistor --------------------------- +use work.electricalsystem.all; + +entity trans_npn is + port( terminal emitter,base,collector : electrical); +end trans_npn; + +architecture trans_behav of trans_npn is + +terminal t1,t2,t3,t4,t5,e,b :electrical; + +constant Lb :real:=0.5e-9; +constant rb1 :real:=1.0; +constant rb2 :real:=3.1; +constant rb3 :real:=2.7; +constant r_pi :real:=110.0; +constant c_pi :real:=18.0e-12; +constant gm :real:=0.88; +constant cc1 :real:=0.091e-12; +constant cc2 :real:=0.048e-12; +constant cc3 :real:=0.023e-12; +constant Le :real:=0.2e-9; +constant Rbase:real:=22.0; +constant Remit:real:=0.6; + + +quantity v1 across i1 through b to t1; +quantity v2 across i2 through t1 to t2; +quantity v3 across i3 through t2 to t3; +quantity v4 across i4 through t3 to t4; +quantity v_pi across i5 through t4 to t5; +quantity i6 through t4 to t5; +quantity v7 across i7 through t1 to collector; +quantity v8 across i8 through t2 to collector; +quantity v9 across i9 through t3 to collector; +quantity v10 across i10 through t5 to e; +quantity v11 across i11 through collector to t5; +quantity v_base across i_base through base to b; +quantity v_emit across i_emit through e to emitter; + + +BEGIN + + v1 ==Lb*i1'dot; + v2 ==i2*rb1; + v3 ==i3*rb2; + v4 ==i4*rb3; + v_pi==i5*r_pi; + i6 ==c_pi*v_pi'dot; + i7 ==cc1*v7'dot; + i8 ==cc2*v8'dot; + i9 ==cc3*v9'dot; + v10 ==Le*i10'dot; + i11 ==gm*v_pi; + v_base==rbase*i_base; + v_emit==remit*i_emit; + +end architecture trans_behav; + + +-------------------- PNP transistor --------------------------- +use work.electricalsystem.all; + +entity trans_pnp is + port( terminal emitter,base,collector : electrical); +end trans_pnp; + +architecture trans_behav of trans_pnp is + +terminal t1,t2,t3,t4,t5,e,b :electrical; + +constant Lb :real:=0.5e-9; +constant rb1 :real:=1.0; +constant rb2 :real:=3.1; +constant rb3 :real:=2.7; +constant r_pi :real:=110.0; +constant c_pi :real:=18.0e-12; +constant gm :real:=0.88; +constant cc1 :real:=0.091e-12; +constant cc2 :real:=0.048e-12; +constant cc3 :real:=0.023e-12; +constant Le :real:=0.2e-9; +constant Rbase:real:=22.0; +constant Remit:real:=0.6; + + +quantity v1 across i1 through t1 to b; +quantity v2 across i2 through t2 to t1; +quantity v3 across i3 through t3 to t2; +quantity v4 across i4 through t4 to t3; +quantity v_pi across i5 through t5 to t4; +quantity i6 through t5 to t4; +quantity v7 across i7 through collector to t1; +quantity v8 across i8 through collector to t2; +quantity v9 across i9 through collector to t3; +quantity v10 across i10 through e to t5; +quantity v11 across i11 through t5 to collector; +quantity v_base across i_base through b to base; +quantity v_emit across i_emit through emitter to e; + + +BEGIN + + v1 ==Lb*i1'dot; + v2 ==i2*rb1; + v3 ==i3*rb2; + v4 ==i4*rb3; + v_pi==i5*r_pi; + i6 ==c_pi*v_pi'dot; + i7 ==cc1*v7'dot; + i8 ==cc2*v8'dot; + i9 ==cc3*v9'dot; + v10 ==Le*i10'dot; + i11 ==gm*v_pi; + v_base==rbase*i_base; + v_emit==remit*i_emit; + +end architecture trans_behav; + + +--> Constant Voltage source +--------------------------- +use work.electricalsystem.all; +ENTITY voltSource IS + generic(amp:real:=22.0); + PORT( TERMINAL ta2,tb2 : electrical); +END voltSource; + +ARCHITECTURE voltbehavior OF voltSource IS + +terminal t1: electrical; +quantity V_volt across i_volt through t1 to tb2; +quantity V_drop across i_drop through ta2 to t1; + +BEGIN + V_volt == amp; + V_drop == i_drop*100.0; + +END ARCHITECTURE voltbehavior; + +-- ********* Structural Model Of a simple High Frequency OpAmp *********-- + +use work.electricalsystem.all; +entity op_amp is +port(terminal inverting_ip,non_inverting_ip,output :electrical); +end entity op_amp; + +architecture struct of op_amp is + +--> components + +COMPONENT trans_pnp is + port( terminal emitter,base,collector : electrical); +end component; +for all : trans_pnp use entity work.trans_pnp(trans_behav); + +COMPONENT trans_npn is + port( terminal emitter,base,collector : electrical); +end component; +for all : trans_npn use entity work.trans_npn(trans_behav); + +component resistor is +generic(res :real:=1.0 ); +port(terminal r_in,r_out: electrical); +end component; +for all: resistor use entity work.resistor(behav); + +component voltsource is +generic(amp:real:=22.0); +PORT( TERMINAL ta2,tb2 : electrical); +end component; +for all: voltsource use entity work.voltsource(voltbehavior); + +terminal t1,t2,t3,t4,t5,t6,t7,t8,t9,t10:electrical; +terminal V_pos,V_neg: electrical; + +BEGIN + + Q01_npn: trans_npn port map(emitter=>T2 ,base=>T1 ,collector=>T9); + Q02_npn: trans_npn port map(emitter=>T2 ,base=>T3 ,collector=>T4); + Q03_npn: trans_npn port map(emitter=>T5 ,base=>T6 ,collector=>T2); + Q04_npn: trans_pnp port map(emitter=>T7 ,base=>T4 ,collector=>T8); + Q05_npn: trans_npn port map(emitter=>output,base=>T8 ,collector=>V_pos); + + Res_i1 : resistor generic map(1.0e3) + port map(inverting_ip,T1); + Res_i2 : resistor generic map(1.0e3) + port map(non_inverting_ip,T3); + Res_a : resistor generic map(220.0e3) + port map(T6,V_pos); + Res_c1 : resistor generic map(13.0e3) + port map(T9,V_pos); + Res_c2 : resistor generic map(13.0e3) + port map(V_pos,T4); + Res_e4 : resistor generic map(10.0e3) + port map(V_pos,T7); + Res_b : resistor generic map(20.0e3) + port map(T6,V_neg); + Res_e3 : resistor generic map(1.3e3) + port map(T5,V_neg); + Res_c4 : resistor generic map(21.0e3) + port map(T8,V_neg); + Res_e5 : resistor generic map(12.0e3) + port map(output,V_neg); + + vpos : voltsource generic map(amp=>15.0) -- test case + port map(V_pos,ground); + vneg : voltsource generic map(amp=>-15.0) -- test case + port map(V_neg,ground); + +end architecture struct; + +--------------------------------------------------------------------- +------------------- WEIN BRIDGE OSCILLATOR --------------------- +--------------------------------------------------------------------- +use work.electricalsystem.all; + +entity wein_bridge_osc is +port( terminal signal_out :electrical); +end entity wein_bridge_osc; + +architecture struct of wein_bridge_osc is + +--> components +component op_amp is +port(terminal inverting_ip,non_inverting_ip,output :electrical); +end component; +for all:op_amp use entity work.op_amp(struct); + +component diode +generic ( + Isat : real := 1.0e-14; -- saturatioin current + n : real := 1.0; -- emmission coefficient + bv : real := 1.0; -- reverse breakdown voltage + ibv : real := 1.0e-3; -- Breakdown current + rds : real := 1.0 -- Ohnic resistamce + ); +port (terminal pos, neg : electrical); +end component; +for all : diode use entity work.Diode(behav); + +component capacitor is +generic(cap :real:=1.0); +port(terminal c_in,c_out: electrical); +end component; +for all: capacitor use entity work.capacitor(behav); + +component resistor is +generic(res :real:=1.0 ); +port(terminal r_in,r_out: electrical); +end component; +for all: resistor use entity work.resistor(behav); + +terminal t1,t2,t3,t4: electrical; + +begin + +op_amplifier : op_amp port map(inverting_ip=>t4,non_inverting_ip=>t1,output=>t3); + +D1 : diode port map(t3,signal_out); +D2 : diode port map(signal_out,t3); + +R1_a : resistor generic map(18.0e3) + port map(t4, ground); +R1_b : resistor generic map(32.0e3) + port map(t4,signal_out); +R2 : resistor generic map(10.0e3) + port map(signal_out,t3); +R3 : resistor generic map(10.0e3) + port map(t1,ground); +R4 : resistor generic map(10.0e3) + port map(t2,t3); + +C3 : capacitor generic map(16.0e-12) + port map(T1,ground); +C4 : capacitor generic map(16.0e-12) + port map(T1,T2); +end struct; + +---------------------------- Test Bench ----------------------------- + +use work.electricalsystem.all; + +entity testbench is +end entity; + +architecture basic of testbench is + +-->components +component wein_bridge_osc is +port( terminal signal_out :electrical); +end component; +for all: wein_bridge_osc use entity work.wein_bridge_osc(struct); + +terminal t1: electrical; + +quantity V_out across i_out through t1 to ground; + +BEGIN + +osc: wein_bridge_osc port map(T1); + +V_out == i_out*1.0e6; + +end basic; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/subtype_test/test112.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/subtype_test/test112.ams new file mode 100644 index 000000000..a463e8e42 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/subtype_test/test112.ams @@ -0,0 +1,87 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test112.ams,v 1.1 2002-03-27 22:11:20 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : model.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +-- Last modified : +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks the correctness of the subtype declarations for the +-- through and across quantities. +---------------------------------------------------------------------- +PACKAGE electricalSystem IS + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + subtype voltage is real; + subtype current is real; + nature electrical is voltage across current through ground reference; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is + +end entity; + +architecture atest of test is + +constant R1: real :=10.0; +constant R2: real :=5.0; +constant R3: real :=1.0; +terminal T1,T2:electrical; +quantity V1 across I1 through T1 to T2; +quantity V2 across I2 through T2 to electrical'reference; +quantity V3 across I3 through T2 to electrical'reference; +quantity VS across T1 to electrical'reference; + +begin + +e1: V1 == I1*R1; +e2: V2 == I2*R2; +e3: V3 == I3*R3; + +esource:VS == 5.0 * sin(2.0 * 3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; + + diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/subtype_test/test117.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/subtype_test/test117.ams new file mode 100644 index 000000000..acff53241 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/subtype_test/test117.ams @@ -0,0 +1,65 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test117.ams,v 1.1 2002-03-27 22:11:20 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Developed at: +-- Distributed Processing Laboratory +-- University of Cincinnati +---------------------------------------------------------------------- + +Package electricalsystem is + FUNCTION SIN(X : real) RETURN real; + +subtype voltage is real tolerance "abstol=1.0e-3"; +subtype current is real; +subtype resistance is real; + +nature electrical is voltage across current through ground reference; +end package electricalsystem; + +use work.electricalsystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal t1, t2: electrical; +quantity vr across ir through t1 ; +quantity vs across t1; +constant r:resistance; +begin +e1: vs==5.0 *sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); +e2: vr==ir*1.0; + +end architecture; |