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+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test117.ams,v 1.1 2002-03-27 22:11:20 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Developed at:
+-- Distributed Processing Laboratory
+-- University of Cincinnati
+----------------------------------------------------------------------
+
+Package electricalsystem is
+ FUNCTION SIN(X : real) RETURN real;
+
+subtype voltage is real tolerance "abstol=1.0e-3";
+subtype current is real; 
+subtype resistance is real;
+
+nature electrical is voltage across current through ground reference;
+end package electricalsystem;
+
+use work.electricalsystem.all;
+
+entity test is
+end entity;
+
+architecture atest of test is
+terminal t1, t2: electrical;
+quantity vr  across ir through t1 ;
+quantity vs across t1;
+constant r:resistance;
+begin
+e1: vs==5.0 *sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
+e2: vr==ir*1.0;
+
+end architecture;