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Diffstat (limited to 'testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts')
63 files changed, 6534 insertions, 0 deletions
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/clipper.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/clipper.ams new file mode 100644 index 000000000..dac895383 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/clipper.ams @@ -0,0 +1,100 @@ + +-- Copyright (C) 1998-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: clipper.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +------------------------------------------------------------------------ +-- Title : Single diode clipper circuit +-- Project : Mixed signal simulation +------------------------------------------------------------------------ +-- File : diode_clipper1.vhd +-- Author(s) : Vasudevan Shanmugasundaram(vasu@ececs.uc.edu) +-- Created : jan 16 1998 +------------------------------------------------------------------------ +-- Description : +-- Behavioral description of a single diode clipper circuit. +------------------------------------------------------------------------ +-- circuit diagram for the diode clipper: +-- the circuit comprises: +-- o______|l______o____|>|______o i) a diode D. +-- | |l | diode D ii) a constant voltage source vd. +-- | const | iii)a sinusoidal voltage source. +-- ( ) Vsource > iv) a resistor R. +-- |Vs >R +-- | > +-- o______________|_____________o +-- +------------------------------------------------------------------------ + +--package definition +PACKAGE electricalSystem IS +NATURE electrical IS real ACROSS real THROUGH ground reference; +FUNCTION SIN (X : real ) RETURN real; +FUNCTION EXP (X : real ) RETURN real; +END PACKAGE electricalSystem; +------------------------------------------------------------------------------- + +USE work.electricalSystem.all; + +ENTITY diode_clipper IS +END diode_clipper; + +ARCHITECTURE behav OF diode_clipper IS + --terminal declarations + terminal t1, t2, t3 : electrical; + --quantity declarations + quantity vDiode across iDiode through t1 TO t2; + quantity v2 across i2 through t2 TO t3; + quantity vd across electrical'reference TO t1; + quantity vs across electrical'reference TO t3; + --constants + CONSTANT saturation_current : real := 0.0000000000001; + CONSTANT Vt : real := 0.025; + CONSTANT BV : real := 100.0; + CONSTANT neg_sat : real := -saturation_current; + +BEGIN -- behav + if( vDiode >= (-1.0 * Vt)) USE --diode equations + eqn1_1: iDiode == saturation_current * ( exp(vDiode/Vt) - 1.0 ); + ELSIF ((vDiode < (-3.0 * Vt)) AND (vDiode > -BV)) use + eqn1_2: iDiode == neg_sat; + ELSE + eqn1_3: iDiode == neg_sat * (exp(-(BV + vDiode)/Vt) - 1.0 + + saturation_current); + END USE ; + + eqn2: v2 == i2 * 100.0; -- resistor eqn. + + eqn3: vs == 20.0 * sin(2.0 * 3.1415 * 10000.0 * real(time'pos(now)) * + 1.0e-15); -- source + + eqn4: vd == 5.0; -- dc source +END behav; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/double_tuned.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/double_tuned.ams new file mode 100644 index 000000000..d76b33795 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/double_tuned.ams @@ -0,0 +1,201 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: double_tuned.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +--************************************************************************ +-- Structural Model of a DOUBLED TUNED TRANSFORMER +-- VHDL-AMS implementation +-- Developed at Distributed Processing Laboratory +-- University of Cincinnati +--************************************************************************ + +--************************************************************************ +-- +-- ________________________________ +-- V_in | | +-- o-----|-------- ------------|---o V_out +-- | | | | | | +-- | | | | | | +-- | | | | | | +-- | | >rp rs< | | +-- | | > < --- | +-- FM | _|_ | . | --- | FM & AM Signal +-- Signal | ___ ( ) ( ) |Cs | +-- | | ( ) || ( ) | | +-- | |Cp ( ) || ( ) | | +-- | | | Lp Ls | | | +-- o-----|-------- ------------|---o V_out_gnd +-- Vin_gnd |________________________________| +-- +--************************************************************************ + +PACKAGE electricalSystem IS +NATURE electrical IS real ACROSS real THROUGH ground reference; +FUNCTION SIN (X : real ) RETURN real; +FUNCTION COS (X : real ) RETURN real; +FUNCTION EXP (X : real ) RETURN real; +FUNCTION SQRT (X : real) RETURN real; +END PACKAGE electricalSystem; + +------------------------------------------------------------------------------ +---------------------- TUNED TRANSFORMER ------------------------------------ +------------------------------------------------------------------------------ + +USE work.electricalSystem.all; + +ENTITY FM_2_AM_Converter IS +generic (freq_fm : real := 1.0); +port (terminal Signal_in, Signal_out : electrical); +END FM_2_AM_Converter; + +ARCHITECTURE behav OF FM_2_AM_Converter IS + + CONSTANT k :real:=0.4; + CONSTANT lp :real:=1.0e-3; + CONSTANT ls :real:=1.0e-3; + CONSTANT rp :real:=10.0; + CONSTANT rs :real:=10.0; + +--> Q = 2*PI*Freq*L/R : for 10.7 MHz -> q=6723 + + terminal temp1,temp2: electrical; + + quantity v_rp across i_rp through Signal_in to temp1; + quantity v_rs across i_rs through temp2 to Signal_out; + + quantity V_cp across i_cp through Signal_in to ground; + quantity V_cs across i_cs through Signal_out to ground; + + QUANTITY V_lp ACROSS i_lp Through temp1 to ground; + quantity v_ls across i_ls through temp2 to ground; + + quantity m : real ; -- mutual inductance; + + +BEGIN -- behavior + + brk : break i_lp => 0.0, i_ls => 0.0,v_cp=>0.0,v_cs=>0.0; + + mutual : m == k * sqrt(lp*ls); + voltp : v_lp == lp * i_lp'dot + m * i_ls'dot; + volts : v_ls == ls * i_ls'dot + m * i_lp'dot; + + i_cp == (25.331/(freq_fm*freq_fm))*v_cp'dot; -- cal. using the value of Inductance + i_cs == (25.331/(freq_fm*freq_fm))*v_cs'dot; -- as 1.0e-3. + -- modify this if u want to use another + v_rp == rp *i_rp; -- value of Lp and ls + v_rs == rs *i_rs; -- c =1/(2*PI*F)*(2*PI*F)*L + +END behav; + +------------------------------Test Waveforms----------------------- + +--> FM wave generator +---------------------- + +use work.electricalsystem.all; + +ENTITY fm_source IS +generic(c_freq:real:=100.0e6; -- carrier frequency + s_freq:real:=25.0e3; -- modulating(signal) frequency + V_fm :real:=1.0 -- Peak voltage of FM signal + ); +PORT(TERMINAL fm_out,fm_gnd : electrical); +END fm_source; + +ARCHITECTURE fm_behavior OF fm_source IS + +quantity V_fm_signal across i_fm_signal through fm_out to fm_gnd; + +BEGIN + +--- the max. freq. deviation is 75.0Khz for FM Signal. + + V_fm_signal == (V_fm*sin((2.0*22.0/7.0*c_freq*real(time'pos(now))*1.0e-15)+(75.0e3/s_freq*sin(2.0*22.0/7.0*s_freq*real(time'pos(now))*1.0e-15)))); + +END ARCHITECTURE fm_behavior; + +-------------------------------- TEST BENCH -------------------------- + +use work.electricalSystem.all; + +entity test is +end test; + +architecture structure of test is + + terminal t1,t2,t3 : electrical; + +--> Component Declarations + +component fm_source is +generic(c_freq:real:=100.0e6; -- carrier frequency + s_freq:real:=25.0e3; -- modulating(signal) frequency + V_fm:real:=1.0 -- Peak Voltage of FM Signal + ); +PORT( TERMINAL fm_out,fm_gnd : electrical); +end component; +for all: fm_source use entity work.fm_source(fm_behavior); + +component FM_2_AM_Converter IS +generic (freq_fm : real := 1.0); +port (terminal Signal_in, Signal_out : electrical); +end component; +for all : FM_2_AM_Converter use entity work.FM_2_AM_Converter(behav); + +quantity v_out across i_out through t2 to ground; + +begin + + FM_AM : FM_2_AM_Converter generic map(freq_fm=>10.7816e6) + port map(t1,t2); + + fm_ip : fm_source generic map(10.7e6,10.0e3,1.0) + port map(t1,ground); + + resout : v_out == i_out * 1.0e6; + +end structure; + +------------------------------ NOTES ------------------------------------- +-- It is a tuned transformer with the resonant freq. slighty higher +-- than the carrier freq. +-- +-- Q = 2*PI*Freq*L/Rl BandWidth = F_carrier/Q +-- F_carrier = 1/2*PI*sqrt(L*C) +-- +-- Tune the Transformer to a frequency of (All quantities in MHz) +-- ( F_carrier + 0.075 + 0.005 + Band_width ) +-- | +-- | +-- *-> Max Deviation +---------------------------------------------------------------------------- diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/hwr_filter.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/hwr_filter.ams new file mode 100644 index 000000000..ec678f192 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/hwr_filter.ams @@ -0,0 +1,109 @@ + +-- Copyright (C) 1998-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: hwr_filter.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- Title : Half Wave Rectifier with capacitor filter +-- Project : Mixed signal simulation +---------------------------------------------------------------------- +-- File : hwr.vhd (Behavioral) +-- Author(s) : Vasudevan Shanmugasundaram(vasu@ececs.uc.edu) +-- Created : jan 16 1998 +---------------------------------------------------------------------- +-- Description : +-- Behavioral description of a half wave rectifier circuit with a +-- capacitor filter. +---------------------------------------------------------------------- +-- T1 diode D T2 +-- o-----|>|-----o----o-------o The circuit comprises: +-- | | | i) A diode . +-- ( ) | >R=100ohms ii) A sinusoidal voltage source +-- |Vs = 5sinwt __ > iii)A resistor R. +-- | -- > iv) A capacitor C. +-- | |C | +-- |_____________|____|_______o +-- |gnd +-- ----- +---------------------------------------------------------------------- + +PACKAGE electricalSystem IS + + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN (X : real ) RETURN real; + FUNCTION EXP (X : real ) RETURN real; + +END PACKAGE electricalSystem; + +---------------------------------------------------------------------- + +USE work.electricalSystem.all; + +ENTITY hwr_filter IS +END hwr_filter; + +-- purpose: a capacitor filtered half wave rectifier +ARCHITECTURE behav OF hwr_filter IS + + terminal t1, t2 : electrical; + quantity vDiode across iDiode through t1 TO t2; + quantity v2 across i2 through t2 TO electrical'reference; + quantity vc across ic through t2 TO electrical'reference; + quantity vs across t1 TO electrical'reference; + + CONSTANT saturation_current : real := 0.0000000000001; + CONSTANT Vt : real := 0.025; + + CONSTANT BV : real := 100.0; + CONSTANT neg_sat : real := -saturation_current; + +BEGIN -- behav + + -- diode behavior equation + if( vDiode >= (-1.0 * Vt)) USE + eqn1_1: iDiode == saturation_current * (exp(vDiode/Vt) - 1.0); + + ELSIF ((vDiode < (-3.0 * Vt)) AND (vDiode > -BV)) use + eqn1_2: iDiode == neg_sat; + + ELSE + eqn1_3: iDiode == neg_sat * (exp(-(BV + vDiode)/Vt) - 1.0 + saturation_current); + + END USE ; + + eqn2: v2 == 100.0 * i2; -- resistor + + eqn4: vs == 5.0 * sin(2.0 * 3.1415 * 10000.0 --sine source + * real(time'pos(now)) * 1.0e-15); + + eqn6: ic == 0.000005 * vc'dot; -- capacitor + +END behav; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/limiter.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/limiter.ams new file mode 100644 index 000000000..3e605b442 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/limiter.ams @@ -0,0 +1,153 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: limiter.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +-- +-- R1(10.0) R2(10.0) +-- o----^^^^^^^^------o-^^^--o--------------o +-- V_in T1| | V_out +-- | | +-- | | +-- _|_ --- +-- \ / / \ +-- --- --- +-- | | +-- T2 o o T3 +-- | | +-- ----- --- +-- --- ----- +-- | | +-- | | +-- V_in_gnd | | V_out_gnd +-- o----------------------------------------o + + + PACKAGE electricalsystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X:real) RETURN real; + FUNCTION EXP(X:real) RETURN real; + END PACKAGE electricalsystem; + +-------------------------- LIMITER ------------------------------ +use work.electricalsystem.all; + +entity limiter is +generic (lim:real:=1.0); +port (terminal v_in,v_out :electrical); +end entity limiter; + +architecture behav of limiter is + +terminal t1,t2,t3 :electrical; + +constant k:real := 0.02586; -- thermal voltage +constant iss:real := 1.8104e-15; +constant gmin:real := 1.0e-12; + +quantity vd1 across id1 through t1 to t2; +quantity vd2 across id2 through t3 to v_out; +quantity V_volt1 across i_volt1 through t2 to ground ; +quantity V_volt2 across i_volt2 through ground to t3; +quantity v_r1 across i_r1 through V_in to T1; +quantity v_r2 across i_r2 through T1 to V_out; + +BEGIN + + if (vd1 >= (-5.0*k)) use + id1 == iss * (exp(vd1/k)-1.0) + vd1*gmin; + elsif (vd1<-5.0*k) use + id1 == -1.0*iss + vd1*gmin; + end use; + + if (vd2 >= (-5.0*k)) use + id2 == iss * (exp(vd2/k)-1.0) + vd2*gmin; + elsif (vd2<-5.0*k) use + id2 == -1.0*iss + vd2*gmin; + end use; + V_volt1 == (lim); + V_volt2 == (lim); + V_r1 == i_r1*10.0; + V_r2 == i_r2*10.0; + +end architecture behav; + + +--------------------------- Test Waveforms ----------------------------- + +use work.electricalsystem.all; +ENTITY sineSource IS +generic( amp:real:=1.0); + PORT( TERMINAL ta2,tb2 : electrical); +END sineSource; + +ARCHITECTURE sinebehavior OF sineSource IS +quantity Vsine across isine through ta2 to tb2; + +BEGIN + Vsine == (amp*sin((2.0*22.0/7.0*10.7e6)*real(time'pos(now))*1.0e-15)); + +END ARCHITECTURE sinebehavior; + + +------------------------------ Test Case ------------------------------- +use work.electricalsystem.all; +entity testbench is +end entity; + +architecture basic of testbench is + + +terminal t1,t2 :electrical; + +quantity v_out across i_out through t2 to ground; + +component limiter is +generic (lim:real:=1.0); +port(terminal v_in,v_out :electrical); +end component; + +component sinesource is +generic( amp:real:=1.0); + PORT( TERMINAL ta2,tb2 : electrical); +end component; + +BEGIN + +lim : limiter generic map(lim=>3.0) + port map(t1,t2); + +sine: sinesource generic map(amp=>6.0) + port map(t1,ground); + +v_out ==i_out*1.0e3; + +end basic; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/peak_detector.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/peak_detector.ams new file mode 100644 index 000000000..9e23e20b1 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/peak_detector.ams @@ -0,0 +1,274 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: peak_detector.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +-- Change the values of res. and cap for various freq.'s + + + +--************************************************************************* +-- Conceptual Level Model of a Peak Detector +-- VHDL-AMS implementation +-- Developed at Distributed Processing Laboratory +-- University of Cincinnati +-- by Murthy Revanuru on October 27, 2000. +--************************************************************************* + +--######################################################################### +-- R2= 10.0e3 +-- --------/\/\/\---------- +-- | |\ | +-- .-------|-\ Diode | +-- | \________|\___|_____o V_out +-- 10K | / |/ | +-- V_in o---^^^-|+/ |-------- +-- R1 |/ | | +-- _____ \ +-- Cap _____ / Res +-- | \ +-- | / +-- | | +-- --------- ----- +-- --- - +-- +--######################################################################### + + PACKAGE electricalsystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X:real) RETURN real; + FUNCTION COS(X:real) RETURN real; + FUNCTION EXP(X:real) RETURN real; + FUNCTION SQRT(X:real) RETURN real; + END PACKAGE electricalsystem; + +---------------------------- Diode ----------------------------- +use work.electricalsystem.all; + +entity diode is +port (terminal t21,t22:electrical); +end diode; + +architecture behavior of diode is + +quantity vd across id through t21 to t22; +constant k:real:=0.02586; -- thermal voltage +constant iss:real:=1.8104e-15; +constant gmin:real:=1.0e-12; + +begin + +if (vd >= (-5.0*k)) use + id == iss * (exp(vd/k)-1.0) + vd*gmin; +elsif (vd<-5.0*k) use + id == -1.0*iss + vd*gmin; +end use; +end architecture behavior; + +------------------------ RESISTOR--------------------------- +use work.electricalsystem.all; + +entity resistor is + generic(res :real:=1.0 ); + port(terminal r_in,r_out: electrical); +end entity resistor; + +architecture behav of resistor is + quantity vr across ir through r_in to r_out; + +begin + vr==ir*res; +end architecture behav; + +------------------------ CAPACITOR--------------------------- +use work.electricalsystem.all; + +entity capacitor is + generic(cap :real:=1.0;v_init:real:=0.0); + port(terminal c_in,c_out: electrical); +end entity capacitor; + +architecture behav of capacitor is + +quantity vc across ic through c_in to c_out; + +begin + break vc=>v_init; + ic==cap*vc'dot; +end architecture behav; + +------------------------- OP AMP ------------------------- +use work.electricalsystem.all; + +entity op_amp is +port(terminal inverting_ip,non_inverting_ip,output :electrical); +end entity op_amp; + +architecture struct of op_amp is + +Constant R_in:real:=1.0e6; +Constant R_out:real:=1.0; + +terminal t1:electrical; + +quantity v_in across i_in through non_inverting_ip to inverting_ip; +quantity v_gain across i_gain through t1 to ground; +quantity v_drop across i_drop through t1 to output; + +BEGIN + + V_in==i_in*R_in; + V_gain==V_in*(100.0); + V_drop==i_drop*R_out; + +end architecture struct; + +---------------------- PEAK DETECTOR --------------------- +use work.electricalsystem.all; + +entity peak_detector is +port (terminal v_in,v_out: electrical); +end entity peak_detector; + +architecture struct of peak_detector is + +component capacitor is + generic(cap :real:=1.0;v_init:real:=0.0); + port(terminal c_in,c_out: electrical); +end component; +for all: capacitor use entity work.capacitor(behav); + +component resistor is + generic(res :real:=1.0 ); + port(terminal r_in,r_out: electrical); +end component; +for all: resistor use entity work.resistor(behav); + +component diode is +port (terminal t21,t22:electrical); +end component; +for all: diode use entity work.diode(behavior); + +component op_amp is +port(terminal inverting_ip,non_inverting_ip,output :electrical); +end component; +for all:op_amp use entity work.op_amp(struct); + +terminal t11,t12,t13,t14: electrical; + + +begin + + D1: diode port map(t12,t13); + + R1: resistor generic map(10.0e3) + port map(v_in,T11); + R2: resistor generic map(10.0e3) + port map(T13,T14); + Rs: resistor generic map(1.0e-3) + port map(T13,V_out); + + C1: capacitor generic map(1.0e-9) + port map(T13,ground); + + op: op_amp port map(inverting_ip=>T14,non_inverting_ip=>T11,output=>T12); + +end struct; + +-- ################### TEST WAVE FORMS ####################### +-- Sine Source +-------------- +use work.electricalsystem.all; +ENTITY sineSource IS +generic (amp:real:=1.0; freq:real:=1.0); + PORT( TERMINAL ta2,tb2 : electrical); +END sineSource; + +ARCHITECTURE sinebehavior OF sineSource IS +quantity Vsine across isine through ta2 to tb2; + +BEGIN + Vsine ==(amp*sin((2.0*22.0/7.0*freq)*real(time'pos(now))*1.0e-15)); + +END ARCHITECTURE sinebehavior; + +-- AM Source +-------------- +use work.electricalsystem.all; +ENTITY amSource IS +generic (amp:real:=1.0; wc:real:=1.0;wm:real:=1.0); + PORT( TERMINAL ta2,tb2 : electrical); +END amSource; + +ARCHITECTURE ambehavior OF amSource IS +quantity V_am across i_am through ta2 to tb2; + +BEGIN + V_am == (amp*cos((2.0*22.0/7.0*wc)*real(time'pos(now))*1.0e-15)) +(amp/2.0*cos((2.0*22.0/7.0*(wc+wm))*real(time'pos(now))*1.0e-15)) + + (cos((2.0*22.0/7.0*(wc-wm))*real(time'pos(now))*1.0e-15)); + +END ARCHITECTURE ambehavior; + +------------------------- Test bench ------------------------- + +use work.electricalsystem.all; + +entity rf_test_bench is +end entity rf_test_bench; + +architecture basic of rf_test_bench is + +terminal t1,t2,t3,t4 : electrical; + +----> Components are declared here + +component peak_detector is +port(terminal v_in,v_out :electrical); +end component; +for all: peak_detector use entity work.peak_detector(struct); + +COMPONENT sineSource IS +generic (amp:real:=1.0; freq:real:=1.0); + PORT( TERMINAL ta2,tb2 : electrical);--Interface ports. +end COMPONENT; +for all : sinesource use entity work.sinesource(sinebehavior); + +quantity volt_op across i_op through t4 to ground; + +begin + + op_1 : volt_op==i_op*10000.0; + + peak_det : peak_detector port map(t1,t4); + sine_ip : sinesource generic map(1.0,455.0e3) + port map(t1,ground); + +end architecture basic; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/power_supply.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/power_supply.ams new file mode 100644 index 000000000..c83db0b57 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/power_supply.ams @@ -0,0 +1,138 @@ + +-- Copyright (C) 1997-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: power_supply.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- Title : Power supply circuit (Behavioral) +-- Project : Mixed signal simulation +---------------------------------------------------------------------- +-- File : power_supply.ams +-- Author : Kathiresan Nellayappan <knellaya@ececs.uc.edu> +-- Chandrashekar L Chetput <cchetput@ececs.uc.edu> +-- Created : 26.11.1997 +---------------------------------------------------------------------- +-- Description : +-- VHDL-AMS description of a power supply circuit. +-- BEHAVIORAL DESCRIPTION. +---------------------------------------------------------------------- +-- The ciruit schematic for the power supply circuit is as below: +-- ============================================================== +-- It comprises: +-- diode D1 inductor i) a sinusoidal +-- T2 _____|\|____ T3 L1 T4 voltage source +-- o______| |/| |____o______()()()____o______o ii) a diode D1 +-- | | | | 0.1H | | iii)3 capacitors +-- < | | | | | iv) inductor L1 +-- < R1 |_____||_____| | | | v) source and +-- < 5ohms || _____ _____ < load resistances +-- < C1 ----- ----- < RL +-- | 1microF | | < +-- o T1 | | < +-- | |C2 |C3 < 1K +-- ( )Vin |1mf |1mf < +-- | 10(sinwt) | | | +-- o________________________|________________|______| +-- |gnd +-- ----- +---------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN (X : real ) RETURN real; + FUNCTION EXP (X : real ) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; + +--Entity declaration: +ENTITY power_supply IS +END ENTITY power_supply; + + +--Architecture declaration: +ARCHITECTURE behavior OF power_supply IS + + CONSTANT Capacitance1 : real := 0.000001; -- value of C1 + CONSTANT Capacitance2 : real := 0.001; -- value of C2 + CONSTANT resistance1 : real := 5.0; -- value of R1 + CONSTANT load_resistance : real := 1000.0; -- value of RL + CONSTANT inductance : real := 0.1; -- value of L1 + CONSTANT BV : real := 100.0; -- Diode Breakdown voltage + CONSTANT saturation_current : real + := 0.0000000000001; -- Diode saturation current value. + CONSTANT Vt : real := 0.025; -- Vt = KT/q (thermal voltage) + CONSTANT neg_sat : real + := -saturation_current; -- Negative of the saturation current + CONSTANT MATH_PI : real := 3.14159_26535_89793_23846; + + terminal t1, t2, t3, t4 : electrical; + + +--quantity declarations: + QUANTITY Vin ACROSS Iin THROUGH T1; + QUANTITY vr1 ACROSS ir1 THROUGH T2 TO T1; + QUANTITY d1_v ACROSS d1_i THROUGH T2 TO T3; + QUANTITY vc1 ACROSS ic1 THROUGH T2 TO T3; + QUANTITY vc2 ACROSS ic2 THROUGH T3; + QUANTITY vl ACROSS il THROUGH T3 TO T4; + QUANTITY vc3 ACROSS ic3 THROUGH T4; + QUANTITY vr2 ACROSS ir2 THROUGH T4; + QUANTITY phi : real; --free quantity. + + +BEGIN + + C1: ic1 == vc1'dot * Capacitance1; -- capacitance equation: ic = c*dv/dt. + C2: ic2 == vc2'dot * Capacitance2; -- capacitance equation for C2. + C3: ic3 == vc3'dot * Capacitance2; -- capacitance equation for C3. + res_stmt1: vr1 == ir1 * resistance1; -- resistance equation: v = i*r. + res_stmt2: vr2 == ir2 * load_resistance; -- resistance equation. + induct_stmt: phi == inductance * il; -- inductance equation: flux = L*I + aux_stmt: vl == phi'dot; -- inductance equation: VL = dflux/dt. + + -- the diode equations: + diode1Cond1: IF( d1_V >= (-3.0 * Vt) ) USE + --active region: + diode1St1: d1_I == saturation_current * (exp(d1_V/Vt) - 1.0); + ELSIF( (d1_V < (-3.0 * Vt)) AND (d1_V > -BV)) USE + -- + diode1St2: d1_I == neg_sat; + ELSE + diode1St3: d1_I == neg_sat * (exp(-(BV + d1_V)/Vt) -1.0 + + saturation_current); + END USE; + + --Sinusoidal voltage source: + vsource: Vin == 10.0 * sin(2.0 * 3.14 * 60.0 * real(time'pos(now)) * + 1.0e-15); + +END ARCHITECTURE behavior; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test100.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test100.ams new file mode 100644 index 000000000..eba8a87cf --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test100.ams @@ -0,0 +1,77 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test100.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test100.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple resistor model... +-- the test is done for checking the correct implementation +-- of the simple simultaneous equation statement.it checks +-- nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity V1 across I1 through T1 to T2; +quantity V2 across I2 through T2; +quantity V3 across I3 through T2; +quantity VS across T1; + +begin + +e1: V1 == I1*100.0; +e2: V2 == I2*10.0; +e3: V3 == I3*10.0; + +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test101.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test101.ams new file mode 100644 index 000000000..daf5ffbb7 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test101.ams @@ -0,0 +1,70 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test101.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +---------------------------------------------------------------------- +-- File : test101.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- this test checks teh correctness of the 'integ implementation. +-- it finds the integral of teh source voltage. +-- the input is a sine wave. +--------------------------------------------------------------------- +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity test; + +architecture atest of test is +quantity vs : real; +quantity vout: real; +begin +vs== 5.0 * sin(2.0 * 3.1415 * 10.0 * real(time'pos(now)) * + 1.0e-15); +vout == vs'integ; +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test102.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test102.ams new file mode 100644 index 000000000..db2b9758f --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test102.ams @@ -0,0 +1,82 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test102.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test102.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks the correctness of the Q'integ usage on the RHS of +-- the simple simultaneous eqn. +-------------------------------------------------------------------- +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + + --ALIAS GND is electrical'reference; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity tank is +end tank; + +architecture atank of tank is + +terminal t1,t2 : electrical; + +constant r: real :=10.00; +constant c: real:=0.00000003; + +quantity vin across t1 to electrical'reference; +quantity vr across ir through t1 to t2; +quantity vc across ic through t2 to electrical'reference; +quantity q : real; +begin + + vr == ir*r; + q==c*vc; + ic==q'integ; + vin == 5.0 * sin(2.0 * 3.1415 * 10.0 * real(time'pos(now)) * + 1.0e-15); +end atank; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test103.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test103.ams new file mode 100644 index 000000000..805fac66e --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test103.ams @@ -0,0 +1,84 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test103.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test103.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks the correctness of the simple simultaneous eqn. +-- implementation. This is also a test for the lexical analysis. +-------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUD REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2,T3,T4,T5:electrical; +quantity v1 across i1 through T1 to T2; +quantity v2 across i2 through T2 to T4; +quantity v3 across i3 through T4 to T3; +quantity v4 across i4 through T2 to T5; +quantity v5 across i5 through T5 to T3; +quantity v6 across i6 through T2 to T3; +quantity vS across T1 to electrical'reference; + +begin + +e1: v1==i1*1.0; +e2: v2==i2*1.0; +e3: v3==i3*1.0; +e4: v4==i4*1.0; +e5: v5==i5*1.0; +e6: v6==i6*1.0; +es: vS==5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test104.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test104.ams new file mode 100644 index 000000000..72f1b4e9b --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test104.ams @@ -0,0 +1,90 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test104.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test104.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- this is a test that checks for the correct implementation of if use +-- end use. The condition is checked by comparing the quantity against a +-- known constant value. +----------------------------------------------------------------------- +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is + generic (vmax :real:=10.0); +end entity; + +architecture atest of test is +terminal T1:electrical; +quantity vin across T1; +constant a:real:=1.0; +constant b:real:=2.0; +quantity vin1:real; +quantity vin2:real; + +begin + +vin == vmax/a; + +if (vin==10.0) use +e1: vin1==vmax*b; +else +e2: vin2==vmax; +end use; + + +--if(vin<vmax) use +--e3: vin==vmax/b; +--else +--e4: vin==vmax; +--end use; + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test105.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test105.ams new file mode 100644 index 000000000..7b426ba97 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test105.ams @@ -0,0 +1,79 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test105.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test105.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks for the correctness of quantity as a port declaration. +-- the circuit is a simple RC network with vout acting as thge output port. +-- a sine input is applied to the network. +------------------------------------------------------------------------- +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + FUNCTION COS(X : real) RETURN real; + --ALIAS GND is electrical'reference; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +entity test is + port(quantity vout:out real); +end entity; + +architecture atest of test is + terminal T1,T2:electrical; + quantity VR across IR through T1 to T2; + constant R:real:=100.0; + constant C:real:=1.0e-9; + quantity vout across T2; + quantity vin across T1; +begin + vsource: vin==5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + + vres: IR== VR/R; + cap: vout==C*IR'integ; + +end atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test106.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test106.ams new file mode 100644 index 000000000..c548b2bf0 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test106.ams @@ -0,0 +1,85 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test106.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +---------------------------------------------------------------------- +-- File : test106.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple resistor model... +-- the test is done for checking the correct implementation +-- of the simple simultaneous equation statement.it checks +-- nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2, T3, T4,T5,T6:electrical; +quantity VRgen across IRgen through T1 to T2; +quantity VLgen across ILgen through T2 to T3; +quantity VRin across IRin through T3; +quantity VR1 across IR1 through T4 to T5; +quantity VR1A across IR1A through T4 to T6; +quantity VC1A across IC1A through T6 to T5; +quantity VC1 across IC1 through T5; +quantity VS across T1; +constant C1: real:=3.5e-3; +constant C1A: real:=0.3e-3; +begin + +e1: VRgen == IRgen*10.0; +e2: VLgen == 0.5*ILgen'dot; +e3: VRin == IRin*500.0; +e4: VR1 == IR1*1.0; +e5: VR1A == IR1A*0.2; +e6: IC1 == C1 * VC1'dot; +e7: IC1A == C1A*VC1A'dot; + +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test108.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test108.ams new file mode 100644 index 000000000..6bfad5b19 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test108.ams @@ -0,0 +1,74 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test108.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test100.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple resistor model... +-- the test is done for checking the correct implementation +-- of the simple simultaneous equation statement.it checks +-- nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; +architecture atest of test is +terminal t1, t2: electrical; +quantity vd across id through T1; -- to T2; +quantity charge :real; +constant vt:real:=0.02; + +begin + +p1: procedural is +begin + vd:=1.0*id; +end procedural; + +end architecture; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test109.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test109.ams new file mode 100644 index 000000000..0a2f21ae2 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test109.ams @@ -0,0 +1,80 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test109.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test109.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks for the correctness of the procedural statements. +-- multiple terms on the RHS +---------------------------------------------------------------------- +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUD REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + + --ALIAS GND is electrical'reference; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal t1,t2: electrical; +quantity vd across id through t1 to t2; +quantity charge:real; +constant vt:real:=0.0258; +constant x:real:=1.0; +quantity ic:real; + +begin +p1: procedural +begin +id:=0.1*(exp((vd-1.0*id)/vt)-1.0); +charge := x*id; +ic:= charge'dot; +end procedural; + +end architecture; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test110.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test110.ams new file mode 100644 index 000000000..96052a1e8 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test110.ams @@ -0,0 +1,69 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test110.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +-- an example of a model having both a signal assignment statement +-- as well as a simple simultaneous statement. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND reference; + FUNCTION SIN (X : real ) RETURN real; + FUNCTION EXP (X : real ) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +use std.textio.all; +ENTITY test IS +END test; + +ARCHITECTURE behavior OF test IS + CONSTANT r1 : real := 100.0; -- value of R1 + terminal t1 : electrical; + QUANTITY vIn ACROSS t1; + QUANTITY vR ACROSS iR THROUGH t1 ; + signal y:bit:='0'; +BEGIN + +process(y) +begin + y <= not(y) after 100 ns; + +end process; + + testbench:PROCESS + BEGIN + WAIT ON y; + END PROCESS; + res_stmt1: vR == iR * r1 ; + vsource: vIn == 5.0 * sin(2.0 * 3.14 * 100000.0 * real(time'pos(now)) * 1.0e-15); + +END ARCHITECTURE behavior; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test111.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test111.ams new file mode 100644 index 000000000..4f86612ba --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test111.ams @@ -0,0 +1,75 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test111.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : model.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks the correctness of the Q'Tolerance. +-- the test checks for the simpel diode implementation +-- wherein the charge is evaluated wrt a relative tolerance value +---------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +entity test is + generic(a:real:=1.0e-10; b:real:=0.0); + port (terminal t1: electrical); +end entity; + +architecture atest of test is + quantity vd tolerance "reltol=1.0e-2" across id through t1; + quantity charge: real; + quantity ic : real; + constant rd: real:=1.0; +begin + e1: id== a*(sin((vd-id*rd)/0.5)-1.0); + e2: charge== b*id; + e3: ic==charge'dot; +end architecture; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test113.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test113.ams new file mode 100644 index 000000000..0e3575822 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test113.ams @@ -0,0 +1,79 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test113.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +---------------------------------------------------------------------- +-- File : test113.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks the correctness of the Q'Tolerance for across qnty +-- and for the real quantity.The test checks for the simpel diode +-- implementation wherein the charge is evaluated wrt a relative +-- tolerance value +-- the test doesn't seem to take a tolerance associated with a +-- free quantity. we need to check on this!! (LRM : 4.3.1 spec +-- followed. +---------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +generic(a:real:=1.0e-10; b:real:=0.0); +port (terminal t1: electrical); + +end entity; + +architecture atest of test is +quantity vd across id through t1; -- to electrical'reference; +quantity charge:real tolerance "reltol=1.0e-2"; +--quantity ic : real; +constant rd: real:=1.0; +begin +e1: id== a*(sin((vd-id*rd)/0.5)-1.0); +e2: charge== b*id; +--e3: ic==charge'dot; +end architecture; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test114.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test114.ams new file mode 100644 index 000000000..7bd8078ae --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test114.ams @@ -0,0 +1,77 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test114.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : model.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks the correctness of the two currents associated +-- as through between same terminals.for eg: consider 2 resistors in +-- parallel.. here vd is same and id and ic are the currents. +-- the test checks for the simpel diode implementation +-- wherein the charge is evaluated wrt a relative tolerance value +---------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +entity test is + generic(a:real:=1.0e-10; b:real:=0.0); +end entity; + +architecture atest of test is + terminal t1:electrical; + quantity vd across id, ic through t1; + quantity charge: real; + --quantity ic : real; + constant rd: real:=1.0; +begin + e1: id== ((vd-id*rd)/0.5); + e2: charge== b*id; + e3: ic==charge'dot; +end architecture; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test115.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test115.ams new file mode 100644 index 000000000..c0232d059 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test115.ams @@ -0,0 +1,84 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test115.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test115.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks for the correctness of the interface declaration: +-- quantity : in| out. +-- ref LRM 4.3.2 +--------------------------------------------------------------------- +PACKAGE electricalSystem IS + subtype voltage is real; + subtype current is real; + NATURE electrical is voltage across current THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; + +entity test is + + port(quantity vout:out electrical); + +end entity test; + +architecture atest of test is +terminal t1,t2: electrical; + +quantity vin across iin through t1; +quantity vr across ir through t1 to t2; +quantity vout across t1 to t2; + +begin + +e1: vin== 5.0 * sin(2.0 * 3.1415 * 10000000.0 * real(time'pos(now)) *1.0e-15); + +e2: vr==ir*1.0; + +e3: vout== vr; + +end architecture; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test116.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test116.ams new file mode 100644 index 000000000..0ce660f14 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test116.ams @@ -0,0 +1,83 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test116.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test116.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks for the correctness of the interface declaration: +-- quantity : in| out. A simple R circuit with an ac voltage source +-- is used. +-- ref LRM 4.3.2 +--------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical is real across real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is + + port(quantity vout:out voltage); + +end entity test; + +architecture atest of test is +terminal t1,t2: electrical; + +quantity vin across iin through t1; +quantity vr across ir through t1 to t2; +quantity vout across t1 to t2; + +begin + +e1: vin== 5.0 * sin(2.0 * 3.1415 * 10000000.0 * real(time'pos(now)) *1.0e-15); + +e2: vr==ir*1.0; + +e3: vout== vr; + +end architecture; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test118.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test118.ams new file mode 100644 index 000000000..7e452987b --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test118.ams @@ -0,0 +1,91 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test118.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test118.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- + +-- the test checks for the correctness of the implemenatation of the case statement. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + + --ALIAS GND is electrical'reference; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; + +entity test is +end entity test; + +architecture atest of test is +terminal t1:electrical; +signal ison: boolean; +quantity vr across ir through t1; +constant vt:real:=0.0258; +begin + +process + variable off : boolean:=true; +begin + ison <= not off; + case off is + when true=> + ison<= not off; + when false=> + ison<=off; + end case; +end process; +source: vr==10.0 * sin(2.0 *(22.0/7.0)*100000.0*real(time'pos(now)) * 1.0e-15); +if ison use + ir== 5.0; --*(exp(vr/vt)-1.0); +else + ir==0.0; +end use; + +break on ison; +end architecture; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test119.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test119.ams new file mode 100644 index 000000000..ee7d1b60d --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test119.ams @@ -0,0 +1,93 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test119.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test1.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +-- Last modified : +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- This is the simple resistor model that sets the foundation on which +-- we build SIERRA, the VHDL AMS simulator. The circuit consists of 3 +-- resistors connected to a voltage source. +-- T1 R1 T2 +-- o-----/\/\----o-------- +-- | | | +-- ( ) > > +-- |Vs = 5sinwt >R2 >R3 +-- | > > +-- |_____________|____|___ +-- |gnd +-- ---- +-------------------------------------------------------------------------- +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is + +constant R1: real :=10.0; +constant R2: real :=5.0; +constant R3: real :=1.0; +terminal T1,T2:electrical; +quantity V1 across I1 through T1 to T2; +quantity V2 across I2 through T2 to electrical'reference; +quantity V3 across I3 through T2 to electrical'reference; +quantity VS across T1 to electrical'reference; + +begin + +e1: V1 == I1*R1; +e2: V2 == I2*R2; +e3: V3 == I3*R3; + +esource:VS == 5.0 * sin(2.0 * 3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; + diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test121.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test121.ams new file mode 100644 index 000000000..9da136bdf --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test121.ams @@ -0,0 +1,80 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test121.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test3.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- this is to check the quantity: q'dot in the lhs and rhs of the +-- simultaneous statements +--------------------------------------------------------------------- +PACKAGE electricalSystem is + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is + quantity x11: real; + constant x1:real:=2.0; + constant x2:real:=1.0; + constant m1 : real:=1.0; + quantity f : real; + quantity dx1 : real; + +begin +e1: f == 10.0* sin(2.0 * 3.141592 *10000.0 * real(time'pos(now))*1.0e-12); +e2: x11 == f*(x1-x2)/m1; +e3: dx1 == f'dot; + +-- x1'dot == f*(x1-x2)/m1; +-- x2'dot == f*(x1-x2)/m2; +-- xs == (m1*x1+m2*x2)/(m1+m2); +-- m3 == m1*x1'dot+ m2*x2'dot; +end atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test122.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test122.ams new file mode 100644 index 000000000..ad2ccd342 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test122.ams @@ -0,0 +1,79 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test122.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test122.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- + +-- to check for the correct implementation of the simple simultaneous +-- statements +---------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + + --ALIAS GND is electrical'reference; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity chk is + generic(i:real:=1.0e-9); + port(terminal t1, t2: electrical); +end chk; + +architecture achk of chk is + quantity vd across id through t1 to t2; + quantity q: real; + quantity ic:real; + constant vth : real:= 0.025; +begin + +e1: id == i*(exp(vd/vth)-1.0); +e2: q == id*0.25; +e3: ic == q'dot; + +end achk; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test124.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test124.ams new file mode 100644 index 000000000..41f8d2658 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test124.ams @@ -0,0 +1,79 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test124.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test124.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- this test is to chk the support of ALIAS, NATURE in the PACKAGE +-- declaration the test also chks the corrct use of quantity and terminal +-- declarations. +-------------------------------------------------------------------------- +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; +END PACKAGE electricalSystem; + +--entity declaration + +use work.electricalsystem.all; +ENTITY Rckt IS +END Rckt; + +--architecture declaration + +ARCHITECTURE aRckt OF Rckt IS + + terminal T1, T2 : electrical; + + quantity VR across IR through T1 to T2; + quantity VR1 across IR1 through T2; + quantity VS across T1; + constant R : REAL := 10.00; + +BEGIN + +eqn1 : VR == IR * R; +e2: VR1 == IR1 * R; +eqn2 : VS == 5.0; + +end arckt; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test128.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test128.ams new file mode 100644 index 000000000..c92536663 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test128.ams @@ -0,0 +1,86 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test128.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test104.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- this is a test that checks for the correct implementation of if use +-- end use. The condition is checked by comparing the quantity against a +-- known constant value. +----------------------------------------------------------------------- +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + + --ALIAS GND is electrical'reference; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is + terminal T1, T2:electrical; + +quantity vin across T1 to electrical'reference; +constant a:real:=1.0; +constant b:real:=2.0; + +quantity vin1 across iin1 through T1 to T2; +quantity vin2 across iin2 through T2 to electrical'reference; +begin + +eq1: vin==5.0* sin(2.0 * 3.141592 *1000.0 * real(time'pos(now))*1.0e-12); +eq2: vin1== iin1*a; +eq3: vin2== iin2*b; +if (vin1>5.0) and (vin1<10.0) use +e1: vin1==vin/a; +elsif (vin2<5.0) use +e2: vin2==vin/b; +else +e3: vin1==vin; +end use; +end atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test136.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test136.ams new file mode 100644 index 000000000..275aa7a86 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test136.ams @@ -0,0 +1,85 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test136.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test136.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +-- Last modified : +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A resistor bridge network... +-- the test is done for checking the correct implementation +-- of the simple simultaneous equation statement.it checks +-- nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture mesh of test is + +terminal t1, t2, t4 : electrical; +quantity v1 across i1 through t1 to t2; +quantity v2 across i2 through t2; +quantity v3 across i3 through t4; +quantity v4 across i4 through t1 to t4; +quantity v5 across i5 through t1; +quantity vs across t1; + +begin + +e1: v1== i1*10.0; +e2: v2== i2*10.0; +e3: v3== i3*10.0; +e4: v4== i4*10.0; +e5: v5== i5*20.0; + +esource: vs== 10.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-15); + +end architecture mesh; + + diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test141.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test141.ams new file mode 100644 index 000000000..215384db4 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test141.ams @@ -0,0 +1,75 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test141.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test141.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +-- this is the behavioral model of a simple error amplifier. +-- the entity consists of a quatity port and the architecture consists +-- of a simple simultaneos statement +---------------------------------------------------------------------- +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +-- subtype voltage is real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity ErrorAmplifier is + generic( Gain : REAL := 10.0 -- amplifier gain + ); + port( terminal P_T,N_T: electrical; -- analog input pins + quantity Vout : out real -- analog output + ); +end entity ErrorAmplifier; + +architecture Behavior of ErrorAmplifier is + +quantity DeltaV across P_T through N_T; -- differential input voltage +begin +e1: DeltaV== 1.0* sin(2.0 * 3.141592 *10000.0 * real(time'pos(now))*1.0e-12); +e2: Vout == Gain*DeltaV; + +end architecture Behavior; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test145.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test145.ams new file mode 100644 index 000000000..ff7ecdbb5 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test145.ams @@ -0,0 +1,359 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test145.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test145.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : June 2001 +---------------------------------------------------------------------- +-- Description : +--this is a mos model. It tests for the correctness of the procedural +--statement. +-- +--the model accepts the mos data as generic constants. The terminals +--are defined as of nature electrical. +--it also tests the alias declaration for real'low. +--Charges associated with the 4 terminals are declared as quantities. +--The voltage associated with each of them is also defined. +--a signal is used to drive i.e to carry out a generic initialization. +--The various mos equations are evaluated depending on the conditions. +--The equations for charges and currents are evaluated. +---------------------------------------------------------------------- + +package mosdata is + NATURE electrical is real across real through; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + alias undefined is real'low; + constant Temperature: real:=27.0; + constant eps0 : real :=8.85418e-12; + constant Ni : real :=1.45e16; + constant Boltzmann : real :=1.380662e-23; + constant echarge: real :=1.6021892e-19; + constant epsSiO2 : real :=3.9*eps0; + constant epsSi : real :=11.7*eps0; + constant kTQ : real :=Boltzmann*temperature/echarge; + constant pi: real := 3.14159; +end package mosdata; + +use work.mosdata.all; +entity mos is + + generic( + width : real:=1.0E-4; + length : real:=1.0E-4; + channel: real :=1.0; + kp :real:= 2.0E-5; + gamma :undefined; + phi :undefined; + tox :real:= 1.0E-7; + nsub :real:= 0.0; + nss :real:=0.0; + nfs :real:= 0.0; + tpg :real:= 1.0; + xj :real:=0.0; + ld :real:= 0.0; + u0 :real:= 600.0; + vmax :real:=0.0; + xqc :real:= 1.0; + kf :real:=0.0; + af :real:=1.0; + fc :real:=0.5; + delta :real:=0.0; + theta :real:=0.0; + eta :real:=0.0; + Sigma :real:=0.0; + kappa :real:=0.2 ); + + port ( terminal drain, gate, source, bulk : electrical); + +end entity mos; + +architecture amos of mos is + quantity Qc, Qb, Qg: real; + quantity Qcq, Qbq, Qgq : real; -- channel, bulk and gate charges + quantity Vdsq across drain to source; + quantity Vgsq across gate to source; + quantity Vbsq across bulk to source; + quantity Idq through drain; + quantity Igq through gate; + quantity Isq through source; + quantity Ibq through bulk; + + signal Initialized: boolean; -- use a signal as generic initialisation + +begin + MOSeqns: procedural is + variable + cox,vt,beta,sigma,nsub,Phi,Gamma,nss,ngate,A,B,C,D,Vfb,fshort, + wp,wc,sqwpxj,vbulk,delv,vth,Vgstos, Vgst, + Ueff,Tau,Vsat,Vpp,fdrain, + stfct,leff,xd,qnfscox,fn,dcrit,deltal,It,Ids,R,Vds,Vgs,Vbs, + forward ,egfet,fermig, mobdeg: real; + begin -- procedural statements + + if not Initialized then + if tox<=0.0 then + cox:=epsSiO2/1.0e-7; + else + cox:=epsSiO2/tox; + end if; + + if kp = 0.0 then + beta:=cox*u0; + else + beta:=kp; + end if; + + nsub := nsub * 1.0e6; -- scale nsub to SI units + + if (phi = undefined) then + if (nsub > 0.0) then + if (0.1<2.0*KTQ*(nsub/Ni)) then + Phi:=(2.0*kTQ*(nsub/Ni)); + else + Phi:=0.1; + end if; + else + Phi:=0.6; + end if; + else + Phi:=phi; + end if; + + if (gamma = undefined) then + if (nsub > 0.0) then + Gamma:=sqrt(2.0*epsSi*echarge*nsub)/cox; + else + Gamma:=0.0; + end if; + else + Gamma:=gamma; + end if; + + nss:=nss*1.0e4; -- Scale to SI + ngate:=gamma*1.0e4; -- Scale to SI + + leff:=length-2.0*ld; + if leff>0.0 then + Sigma:= eta * 8.15e-22/(cox*leff*leff*leff); + else + Sigma:=0.0; + end if; + + if nsub>0.0 then -- N.B. nsub was scaled, above. + xd:=sqrt(2.0*epsSi/(echarge*nsub)); + else + xd:=0.0; + end if; + + if (nfs>0.0) and(cox>0.0) then + qnfscox:=echarge*nfs/cox; + else + qnfscox:=0.0; + end if; + + if cox>0.0 then + fn:=delta*pi*epsSi*0.5/(cox*width); + else + fn:=delta*pi*epsSi*0.5*tox/epsSiO2; + end if; + + --Scale beta and convert cox from Fm^-2 to F + beta:=beta*width/leff; + cox:=cox*width*leff; + + Initialized <= true; + end if; -- not initialized + + Vds:=channel*Vdsq; + if Vds>=0.0 then + Vgs:=channel* Vgsq; + Vbs:=channel* Vbsq; + forward:=1.0; + else + Vds:=-Vds; + Vgs:=channel* Vgsq; + Vbs:=channel* Vbsq; + forward:=-1.0; + end if; + + if Vbs<=0.0 then + A:=Phi-Vbs; + D:=sqrt(A); + else + D:=2.0*sqrt(Phi)*Phi/(2.0*Phi+Vbs); + A:=D*D; + end if; + + Vfb:=Vt-Gamma*sqrt(Phi)-Sigma*Vds; + if (xd=0.0) OR (xj=0.0) then + fshort:=1.0; + else + wp:=xd*D; + wc:=0.0631353*xj+0.8013292*wp-0.01110777*wp*wp/xj; + sqwpxj:=sqrt(1.0-(wp*wp/((wp+xj)*(wp+xj)))); + fshort:=1.0-((ld+wc)*sqwpxj-ld)/leff; + end if; + + vbulk:=Gamma*fshort*D+fn*A; + if nfs=0.0 then + delv:=0.0; + else + delv:=kTQ*(1.0+qnfscox+vbulk*0.5/A); + end if; + + vth:=Vfb+vbulk; + Vgstos:=Vgs-Vfb; + + if (vgs-vth > delv) then + Vgst:=Vgs-vth; + else + Vgst:= delv; + end if; + + if (vgs>=vth) or (delv/=0.0) then + + if (Vbs<=0.0) or (Phi /= 0.0) then + B:=0.5*Gamma/D+fn; + else + B:=fn; + end if; + + mobdeg:=1.0/(1.0+theta*Vgst); + + if (vmax /=0.0) then + Ueff:=u0*mobdeg; + Tau:=Ueff/Leff*vmax; + else + Tau:=0.0; + end if; + + Vsat:=Vgst/(1.0+B); + Vsat:=Vsat*(1.0-0.5*Tau*Vsat); -- not quite the same as SPICE + if (vds<Vsat) then + Vpp:=vds; + else + Vpp:= Vsat; + end if; + + fdrain:=1.0/(1.0+Tau*Vpp); + if (Vgs<vth+delv) and (nfs>0.0) then + stfct:=exp((Vgs-vth-delv)/delv); + else + stfct:=1.0; + end if; + + if Vds>=Vsat then + if (kappa>0.0) and (xd>0.0) then + + if vmax=0.0 then + deltal:=sqrt(kappa*xd*xd*(Vds-Vsat)); + else + dcrit:=(xd*xd*vmax*0.5)/(Ueff*(1.0-fdrain)); + + deltal:=sqrt(kappa*xd*xd*(Vds-Vsat)+dcrit*dcrit)-dcrit; + end if; + + if deltal<=0.5*Leff then + C:=Leff/(Leff-deltal); + else + C:=4.0*deltal/Leff; + end if; + + else + C:=1.0; + end if; + + else + C:=1.0; + end if; + + It:=Vgst-Vpp*(1.0+B)*0.5; + Beta:=Beta*mobdeg; + Ids:=Beta*Vpp*It*C*fdrain*stfct; + else + -- Cutoff + Ids:=0.0; + end if; -- vgs >= vth + + if Cox /= 0.0 then + --Charges + if Vgs<=vth then + if Gamma /= 0.0 then + if Vgstos < -A then + Qg:=Cox*(Vgstos+A); -- Accumulation + else + Qg:=0.5*Gamma*Cox*(sqrt(4.0*(Vgstos+A)+Gamma*Gamma-Gamma)); + end if ; -- vgstos <-A + else-- Gamma = 0.0 + Qg:=0.0; + end if; -- gamma /= 0 + Qb:=-Qg; + Qc:=0.0; + else + -- depletion mode: + R:=(1.0+B)*Vpp*Vpp/(12.0*It); + Qg:=Cox*(Vgstos-Vpp*0.5+R); + Qc:=-Cox*(Vgst+(1.0+B)*(R-Vpp*0.5)); + Qb:=-(Qc+Qg); + end if; + + else + Qg:=0.0; + Qc:=0.0; + Qb:=0.0; + end if; -- cox /= 0 + + -- equations for charges (in a procedural we have assignments to + --quantitites): + Qcq := Qc; + Qgq := Qg; + Qbq := Qb; + + -- equations for currents: + Idq := channel*forward*Ids+channel*xqc*Qc'dot; + Igq := channel*Qg'dot; + Ibq := channel*Qb'dot; + Isq := -Idq - Igq - Ibq; + + end procedural; +end architecture amos; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test146.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test146.ams new file mode 100644 index 000000000..b4f95a02e --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test146.ams @@ -0,0 +1,113 @@ + +-- Copyright (C) 1998-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test146.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +--------------------------------------------------------------------- +-- Title : Half Wave Rectifier (Behavioral) +-- Project : Mixed signal simulation +---------------------------------------------------------------------- +-- File : hwr.vhd (Behavioral) +-- Author(s) : Vasudevan Shanmugasundaram(vasu@ececs.uc.edu) +-- Created : jan 16 1998 +-- Last modified : jan 16 1998 +---------------------------------------------------------------------- +-- Description : +-- Behavioral description of a half wave rectifier circuit in VHDL-AMS +---------------------------------------------------------------------- +-- Modification history : +-- 21.11.1997 : created +---------------------------------------------------------------------- +-- T1 diode D T2 +-- o-----|>|-----o-------o The circuit comprises: +-- | | i) A diode . +-- ( ) >R=100ohms ii) A sinusoidal voltage source. +-- |Vs = 5sinwt > iii)A resistor R. +-- | > +-- |_____________|_______o +-- |gnd +-- ----- +---------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH Ground reference; + FUNCTION SIN (X : real ) RETURN real; + FUNCTION COS (X : real ) RETURN real; + FUNCTION EXP (X : real ) RETURN real; +END PACKAGE electricalSystem; + +---------------------------------------------------------------------- + +USE work.electricalSystem.all; + +--entity declaration +ENTITY hwr IS +END hwr; + +--architecture declaration +ARCHITECTURE behavior OF hwr IS + + terminal t1, t2 : electrical; + quantity vDiode across iDiode through t1 TO t2; + quantity v2 across i2 through t2 TO electrical'reference; + quantity vs across t1 TO electrical'reference; + + CONSTANT saturation_current : real := 0.0000000000001; + CONSTANT Vt : real := 0.025; + + CONSTANT BV : real := 100.0; + CONSTANT neg_sat : real := -saturation_current; + +BEGIN -- behavior + + --diode equations + if( vDiode >= (-1.0 * Vt)) USE + + eqn1_1: iDiode == saturation_current * (exp(vDiode/Vt) - 1.0); + --eqn1_1: iDiode == 100.0 * exp(vDiode); + + ELSIF ((vDiode < (-3.0 * Vt)) AND (vDiode > -BV)) use + + eqn1_2: iDiode == neg_sat; + ELSE + + eqn1_3: iDiode == neg_sat * (exp(-(BV + vDiode)/Vt) - 1.0 + + saturation_current); + END USE ; + + --resistor equation + eqn2: v2 == 100.0 * i2; + + --voltage source equation + eqn4: vs == 5.0 * sin(2.0 * 3.14 * 100000.0 * + real(time'pos(now)) * 1.0e-15 ); + +END behavior ; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test147.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test147.ams new file mode 100644 index 000000000..0e077185f --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test147.ams @@ -0,0 +1,75 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test147.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test147.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- this checks for the corect implementation of the 'dot'dot and negation +-- operator implementation for simple simulataeous statements. +---------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity V1 across I1 through T1 to T2; +quantity V2: real; +quantity V3: real; +quantity VS across Isource through T1; + +begin + +--e1: I1 == V1'dot * 1.0; +--e2: V2 == VS'dot'dot; +e3: V3 == VS'dot; +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); +e4: V2 == -V3; +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test148.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test148.ams new file mode 100644 index 000000000..4645a85ac --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test148.ams @@ -0,0 +1,91 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test148.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test148.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +-- Last modified : +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks for the correctness of the quantity, terminal, nature +-- and package declarations. the terminals are assigned as terminals. +-- a simple V-R circuit is considered. +----------------------------------------------------------------------- + +PACKAGE electricalsystem IS + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + +NATURE electrical IS real ACROSS real THROUGH ; --ground reference; + +END PACKAGE electricalsystem; +use work.electricalsystem.all; + +ENTITY test IS + PORT (TERMINAL p: electrical); +END ENTITY test; + +architecture atest of test is +quantity vr across ir through p; +begin +e2: vr== ir*10.0; +end architecture atest; + +use work.electricalsystem.all; + +entity res is +end res; + +ARCHITECTURE ares OF res IS + component test is + port(terminal p:electrical); + end component; + for all : test use entity work.test(atest); + terminal x:electrical; + constant freq: real:=10000.0; + quantity v across i through x; +BEGIN +r1: test port map(p => x); +e1: v == 5.0 * sin(2.0 * 3.14159 * freq * real(time'pos(now))*1.0e-12); +END ARCHITECTURE ares; + diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test149.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test149.ams new file mode 100644 index 000000000..e2b121131 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test149.ams @@ -0,0 +1,113 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test149.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test149.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple resistor model... +-- the test is done for checking the correct implementation of the +-- componet declaration. The model consists of 2 resistor models which are +-- instantiated. + +package electricalSystem is + NATURE electrical IS real ACROSS real THROUGH Ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalsystem.all; + +entity test1 is + port (terminal P, N : electrical ); +end entity test1; + +architecture behav of test1 is + quantity Vt1 across It1 through P to N; +begin + res1 : Vt1 == It1 * 10.0 ; +end architecture behav; + +use work.electricalsystem.all; +entity test2 is + port (terminal P, N : electrical ); +end test2; + +architecture behav of test2 is + quantity Vt2 across It2 through P to N; +begin + res1 : Vt2 == It2 * 100.0 ; +end behav; + + +use work.electricalsystem.all; + +entity resistor_ckt is +end resistor_ckt; + +architecture ares_ckt of resistor_ckt is + + component test1 is + port (terminal P, N : electrical ); + end component; + + component test2 is + port (terminal P, N : electrical ); + end component; + + for all : test1 use entity work.test1(behav); + for all : test2 use entity work.test2(behav); + + terminal a,b,c,t1,t2 : electrical; + quantity vout across iout through t2 to electrical'reference; + quantity vs across a to electrical'reference; + +begin + e1 : test1 port map (P => a, N => b); + e2 : test2 port map (P => b, N => c); + e3 : vout == iout * 1200.0; + e4 : test1 port map (P => c, N => t1); + e5 : test1 port map (P => t1, N => t2); + source : vs == 5.0 * sin(2.0 * 3.1415 * 10000.0* real(time'pos(now)) * 1.0e-12); +end architecture ares_ckt; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test150.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test150.ams new file mode 100644 index 000000000..e36261f0a --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test150.ams @@ -0,0 +1,75 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test150.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test150.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple RC model... +-- the test is done for checking the correct implementation +-- of the simple simultaneous equation statement with 'dot expression on +-- RHS. it checks nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity V1 across I1 through T1 to T2; +quantity V2 across I2 through T2; +quantity VS across T1; + +begin + +e1: V1 == I1*10.0; +e2: I2 == 1.0e-12*V2'dot; + +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test151.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test151.ams new file mode 100644 index 000000000..cbdb39031 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test151.ams @@ -0,0 +1,76 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test151.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test151.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple resistor model...2 resistors in parallel +-- the test is done for checking the correct implementation of the simple +-- simultaneous equation statement with multiple expressions o RHS. +-- It checks nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1:electrical; +quantity V1 across I1 through T1 to electrical'reference; +quantity V2 across I2 through T1 to electrical'reference; +quantity VS across T1; +quantity I12 : real; +begin + +e1: V1 == I1*10.0; +e2: V2 == I2*10.0; +e3: I12 == I1+I2; + +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test152.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test152.ams new file mode 100644 index 000000000..533f315b5 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test152.ams @@ -0,0 +1,75 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test152.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test150.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple RC model... +-- the test is done for checking the correct implementation +-- of the simple simultaneous equation statement with 'dot expression on +-- RHS. it checks nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity V1 across I1 through T1 to T2; +quantity V2 across I2 through T2; +quantity VS across T1; + +begin + +e1: V1 == I1*10.0; +e2: I2 == V2'dot*1.0e-12; + +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test153.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test153.ams new file mode 100644 index 000000000..d7f05e578 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test153.ams @@ -0,0 +1,79 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test153.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +---------------------------------------------------------------------- +-- File : test153.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple model which has a voltage source. +-- The output voltage Vout is dependent on the value of vS at that point +-- of time. If the voltage is below Vref, the output is a 1 else output is +-- a 0. the test is done for checking the correct implementation of the +-- simple simultaneous if statement.it checks nature declaration, terminal +-- and quantity declarations. + + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity VS across T1; +quantity Vout: real; +constant Vref:real:=5.0; +begin + +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +if (VS <= Vref) use +e1: Vout == 1.0; +else +e2: Vout == 0.0; +end use; + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test154.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test154.ams new file mode 100644 index 000000000..2199502b1 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test154.ams @@ -0,0 +1,79 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test154.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test154.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple model which has a voltage source. +-- The output voltage Vout is dependent on the value of VS wrt Vref +-- If the voltage is below Vref, the output is a 0 else output is a 1. +-- the test is done for checking the correct implementation +-- of the simple simultaneous if statement.it checks +-- nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity VS across T1; +quantity Vout: real; +constant Vref:real:=5.0; +begin + +esource: VS == 5.0; + +if (VS<=Vref) use +e1: Vout == 1.0; +else +e2: Vout == 0.0; +end use; + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test155.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test155.ams new file mode 100644 index 000000000..9843d2c27 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test155.ams @@ -0,0 +1,81 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test155.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test155.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple model which has a voltage source. +-- The output voltage Vout is dependent on the value of VS wrt Vref +-- If the voltage is above/below Vref, the output is a 0 else output is a +-- 1. the test is done for checking the correct implementation of the +-- simple simultaneous if statement with multiple if conditions.it checks +-- nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity VS across T1; +quantity Vout: real; +constant Vref:real:=5.0; +begin + +esource: VS == 5.0; + +if (VS<Vref) use +e1: Vout == 0.0; +elsif (VS=Vref) use +e2: Vout == 1.0; +else +e3: Vout == 0.0; +end use; + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test156.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test156.ams new file mode 100644 index 000000000..8837429f1 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test156.ams @@ -0,0 +1,108 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test156.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +-- check the implemetatio of ports and generics. + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity inv is + port ( + x : in bit; + xout : out bit); +end inv; + +architecture inverter of inv is +begin + + xout <= not x after 100ns ; + +end inverter ; + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND reference; + FUNCTION SIN (X : real ) RETURN real; + FUNCTION EXP (X : real ) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; + +entity resistor is + generic ( res : real := 10.0 ) ; + port (terminal P, N : electrical ); +end resistor; + +architecture behav of resistor is + quantity VPTON across IPTON through P to N; +begin + res1 : VPTON == IPTON * res ; +end behav; + +use work.electricalSystem.all; + +ENTITY circuit1 IS +END circuit1; + +ARCHITECTURE behavior OF circuit1 IS + component inv is + port ( + x : in bit; + xout : out bit); + end component ; + for all : inv use entity work.inv(inverter) ; + + component resistor is + generic ( res : real := 10.0 ) ; + port (terminal P, N : electrical ); + end component; + for all : resistor use entity work.resistor(behav); + + terminal n1,n2 : electrical; + QUANTITY vIn ACROSS iIn THROUGH n1 ; + + signal y:bit:='0'; + +BEGIN + + D2 : inv port map(x=>y, xout=>y); + + testbench:PROCESS + BEGIN + WAIT ON y; + END PROCESS; + + R1 : resistor generic map ( res => 500.0) port map (P => n1, N => n2); + R2 : resistor port map (P => n2, N => ground); + vsource: vIn == 5.0 * sin(2.0 * 3.14 * 100000.0 * real(time'pos(now)) * 1.0e-15); + +END ARCHITECTURE behavior; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test157.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test157.ams new file mode 100644 index 000000000..f13d5c47b --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test157.ams @@ -0,0 +1,108 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test157.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +-- check the implemetation of ports and generics. + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +--entity inv is +-- port ( +-- x : in bit; +-- xout : out bit); +--end inv; + +--architecture inverter of inv is +--begin + +-- xout <= not x after 100ns ; + +--end inverter ; + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND reference; + FUNCTION SIN (X : real ) RETURN real; + FUNCTION EXP (X : real ) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; + +entity resistor is + generic ( res : real := 10.0 ) ; + port (terminal P, N : electrical ); +end resistor; + +architecture behav of resistor is + quantity VPTON across IPTON through P to N; +begin + res1 : VPTON == IPTON * res ; +end behav; + +use work.electricalSystem.all; + +ENTITY circuit1 IS +END circuit1; + +ARCHITECTURE behavior OF circuit1 IS +-- component inv is +-- port ( +-- x : in bit; +-- xout : out bit); +-- end component ; +-- for all : inv use entity work.inv(inverter) ; + + component resistor is + generic ( res : real := 10.0 ) ; + port (terminal P, N : electrical ); + end component; + for all : resistor use entity work.resistor(behav); + + terminal n1,n2 : electrical; + QUANTITY vIn ACROSS iIn THROUGH n1 ; + +-- signal y:bit:='0'; + +BEGIN + +-- D2 : inv port map(x=>y, xout=>y); + +-- testbench:PROCESS +-- BEGIN +-- WAIT ON y; +-- END PROCESS; + + R1 : resistor generic map ( res => 500.0) port map (P => n1, N => n2); + R2 : resistor port map (P => n2, N => ground); + vsource: vIn == 5.0 * sin(2.0 * 3.14 * 100000.0 * real(time'pos(now)) * 1.0e-15); + +END ARCHITECTURE behavior; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test161.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test161.ams new file mode 100644 index 000000000..1a0542e97 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test161.ams @@ -0,0 +1,74 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test161.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +---------------------------------------------------------------------- +-- File : test150.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple RC model... +-- the test is done for checking the correct implementation +--of the simple simultaneous equation statement with 'dot expression on RHS. +--it checks nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity V1 across I1 through T1 to T2; +quantity V2 across I2 through T2; +quantity VS across T1; + +begin + +e1: V1 == I1*10.0; +e2: V2 == I1'integ/1.0e-12; + +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test162.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test162.ams new file mode 100644 index 000000000..dbc7b3bac --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test162.ams @@ -0,0 +1,74 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test162.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test147.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- this checks for the corect implementation of the 'dot'dot and negation +-- operator implementation for simple simulataeous statements +---------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity V1 across I1 through T1 to T2; +quantity V2: real; +quantity i2 :real; +quantity VS across Isource through T1; + +begin + +e1: I1 == V1'dot*1.0e-15; +e2: V2 == V1'dot; +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test163.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test163.ams new file mode 100644 index 000000000..034a02a4b --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test163.ams @@ -0,0 +1,80 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test163.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +---------------------------------------------------------------------- +-- File : test162.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple rc model...with 2 res in parallel connected thru a capacitor +-- -------------||----- +-- | | +-- | R | R +-- -------------------- +-- the test is done for checking the correct implementation +-- of the simple simultaneous equation statement.it checks +-- nature declaration, terminal, 'dot and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity VR1 across IR1 through T1; +quantity VC across IC through T1 to T2; +quantity VR2 across IR2 through T2; +quantity VS across T1; + +begin + +e1: VR1 == IR1*100.0; +e2: IC == VC'dot *1.0e-12; +e3: VR2 == IR2*10.0; + +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test164.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test164.ams new file mode 100644 index 000000000..ca33cd6e2 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test164.ams @@ -0,0 +1,81 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test164.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test164.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple rc model...with 2 res in parallel connected thru a capacitor +-- -------------||----- +-- | | +-- | R | R +-- -------------------- +-- the test is done for checking the correct implementation of the simple +-- simultaneous equation statement.it checks nature declaration, terminal, +-- 'dot, 'integ and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity VR1 across IR1 through T1; +quantity VC across IC through T1 to T2; +quantity VR2 across IR2 through T2; +quantity VS across T1; + +begin + +e1: VR1 == IR1*100.0; +e2: IC == VC'dot *1.0e-12; +e3: VR2 == IR2*10.0; +e4: VC == IC'integ/1.0e15 +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test165.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test165.ams new file mode 100644 index 000000000..d3fd1b0ff --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test165.ams @@ -0,0 +1,79 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test165.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distributed Processing Laboratory +-- University of Cincinnati +---------------------------------------------------------------------- +-- File : test164.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple rl model... +-- -----^^^------------- +-- R | > +-- | L > R +-- -------------------- +-- the test is done for checking the correct implementation +-- of the simple simultaneous equation statement.it checks +-- nature declaration, terminal, 'dot, and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity VR1 across IR1 through T1 to T2; +quantity VL across IL through T2; +quantity VR2 across IR2 through T2; +quantity VS across T1; + +begin + +e1: VR1 == IR1*10.0; +e2: VL == IL'dot *1.0; +e3: VR2 == IR2*10.0; +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test166.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test166.ams new file mode 100644 index 000000000..d84a804c0 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test166.ams @@ -0,0 +1,79 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test166.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +---------------------------------------------------------------------- +-- File : test166.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple rl model... +-- -----^^^------------- +-- R | > +-- | L > R +-- -------------------- +-- the test is done for checking the correct implementation +--of the simple simultaneous equation statement.it checks +--nature declaration, terminal, 'dot,'integ and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity VR1 across IR1 through T1 to T2; +quantity VL across IL through T2; +quantity VR2 across IR2 through T2; +quantity VS across T1; + +begin + +e1: VR1 == IR1*10.0; +e2: VL == IL'dot *1.0; +e3: VR2 == IR2*10.0; +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); +e4: IL== 1.0* VL'integ; +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test167.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test167.ams new file mode 100644 index 000000000..def01db8b --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test167.ams @@ -0,0 +1,80 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test167.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +---------------------------------------------------------------------- +-- File : test167.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- An RC model... +-- the test is done for checking the correct implementation of the simple +-- simultaneous equation statement.it checks nature declaration, terminal, +-- 'dot, 'integ and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2, T3, T4:electrical; +quantity V1 across I1 through T1 to T2; +quantity V2 across I2 through T2 to T3; +quantity VC across IC through T3; +quantity VC1 across IC1 through T2 to T4; +quantity V3 across I3 through T4; +quantity VS across T1; + +begin + +e1: V1 == I1*1.0; +e2: V2 == I2*1.0; +e3: V3 == I3*10.0; +e4: IC == VC'dot*1.0e-12; +e5: IC1 == VC1'dot*1.0e-12; + +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test168.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test168.ams new file mode 100644 index 000000000..bf9e9af81 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test168.ams @@ -0,0 +1,80 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test168.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +---------------------------------------------------------------------- +-- File : test168.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- An RC model... +-- the test is done for checking the correct implementation +--of the simple simultaneous equation statement.it checks +--nature declaration, terminal, 'dot, 'integ and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2, T3, T4:electrical; +quantity V1 across I1 through T1 to T2; +quantity V2 across I2 through T2 to T3; +quantity VC across IC through T3; +quantity VC1 across IC1 through T2 to T4; +quantity V3 across I3 through T4; +quantity VS across T1; + +begin + +e1: V1 == I1*1.0; +e2: V2 == I2*1.0; +e3: V3 == I3*10.0; +e4: VC == IC'integ*1.0e12; +e5: VC1 == IC1'integ*1.0e12; + +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test169.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test169.ams new file mode 100644 index 000000000..18804f48f --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test169.ams @@ -0,0 +1,143 @@ + +-- Copyright (C) 1999-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test169.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +----------------------------------------------------------------------------- +-- Ebers-moll Model for a transistor -- +-- VHDL-AMS Implementation -- +-- Developed at the Distributed Processing Lab at the University -- +-- of Cincinnati -- +-- by VishwaShanth Kasula on May 10, 1999 -- +-------------------------------------------------------------------- +-- Circuit Topology -- +-- BJT Ebers-Moll static model +-- Testbench Ckt to evaluate the DC operatioing point of an npn BJT, +-- Sedra smith page no. 152, fig 4.9 +-------------------------------------------------------------------- + +-- Three regions are simulated +-- Active region, vbb = 4.0 V +-- Saturation region, vbb = 6.0 V +-- Cutoff region, vbb = 0.0; + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalsystem.all; + +entity bjt_npn is + generic(isat : real := 1.0e-16; -- Saturation Current + bf : real := 100.0; -- Ideal maximus forward current + br : real := 1.0; -- ideal maximum reverse current + rb : real := 1.0e-5; -- Base resistance + rc : real := 1.0e-5; -- collector resistance + re : real := 1.0e-5; -- emmiter resistance + vaf : real := 100.0); -- Forward Early Voltage + port(terminal e,b,c : electrical); +end bjt_npn; + +architecture structure of bjt_npn is + terminal b1, c1, e1 : electrical; + quantity vbo across ib through b to b1; + quantity vco across ic through c to c1; + quantity veo across ie through e to e1; + quantity vct across Ict through c1 to e1;--current source + quantity vbe across ibe through b1 to e1; + quantity vbc across ibc through b1 to c1; + quantity vce : real := 1.0; -- used to calculate VCE + constant gmin : real := 1.0e-12; -- condutsnce in parallel with every pn junction + constant vt : real := 0.02589; -- thermal voltage + +begin + brk : break vbe => 1.0, vbc => -1.0; + + diodecond1 : if(vbe > -5.0*vt) use + diodebef : ibe == ((isat*(exp(vbe/vt) - 1.0)) + (gmin*vbe))/bf; + elsif (vbe <= -5.0*vt ) use + diodeber: ibe == ((-1.0*isat) + (gmin*vbe))/bf; + end use; + diodecond2 : if(vbc > -5.0*vt) use + diodebcf : ibc == ((isat*(exp(vbc/vt) - 1.0)) + (gmin*vbc))/br; + elsif(vbc <= -5.0*vt) use + diodebcr : ibc == ((-1.0*isat) + (gmin*vbc))/br; + end use; + bres : vbo == ib * 1.0e-6; + cres : vco == ic * 1.0e-6; + eres : veo == ie * 1.0e-6; + kcl_eqn : ie == -1.0*(ib + ic); + vcevolt : vce == vbe - vbc; + ictdep : Ict == ((Ibe*bf) - (Ibc*br)) * (1.0 -(vbc/vaf)); + +end architecture structure; + + +--***************************************************** +--TEST BENCH +use std.textio.all; +use work.electricalsystem.all; + +entity bjt_testbench is +end bjt_testbench; + +architecture structure of bjt_testbench is + terminal t1, t2, t3, t4 : electrical ; + component bjt_npn_comp + generic(isat : real := 1.0e-16; -- Saturation Current + bf : real := 100.0; -- Ideal maximus forward current + br : real := 1.0; -- ideal maximum reverse current + rb : real := 1.0e-5; -- Base resistance + rc : real := 1.0e-5; -- collector resistance + re : real := 1.0e-5; -- emmiter resistance + vaf : real := 100.0); -- Forward Early Voltage + port(terminal e,b,c : electrical); + end component; + for all : bjt_npn_comp use entity work.bjt_npn(structure); + + quantity vcc across icc through t1 to electrical'reference; + quantity vrc across irc through t1 to t2; + quantity vbb across ibb through t3 to electrical'reference; + quantity vre across ire through t4 to electrical'reference; + +begin + + bjt : bjt_npn_comp + generic map (isat => 1.8104e-15, vaf => 100.0) + port map(t4,t3,t2); + emres : vre == ire * 3.3e3; + ccurr : vcc == 10.0; + ecurr : vbb == 6.0; + cores : vrc == irc * 4.7e3; + +end architecture structure; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test170.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test170.ams new file mode 100644 index 000000000..ab30845f0 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test170.ams @@ -0,0 +1,85 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test170.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +---------------------------------------------------------------------- +-- File : test106.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple resistor model... +-- the test is done for checking the correct implementation +-- of the simple simultaneous equation statement.it checks +-- nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2, T3, T4,T5,T6:electrical; +quantity VRgen across IRgen through T1 to T2; +quantity VLgen across ILgen through T2 to T3; +quantity VRin across IRin through T3; +quantity VR1 across IR1 through T4 to T5; +quantity VR1A across IR1A through T4 to T6; +quantity VC1A across IC1A through T6 to T5; +quantity VC1 across IC1 through T5; +quantity VS across T1; +constant C1: real:=3.5e-3; +constant C1A: real:=0.3e-3; +begin + +e1: VRgen == IRgen*10.0; +e2: VLgen == 0.5*ILgen'dot; +e3: VRin == IRin*500.0; +e4: VR1 == IR1*1.0; +e5: VR1A == IR1A*0.2; +e6: VC1 == C1 /IC1'integ; +e7: VC1A == C1A/IC1A'integ; + +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test172.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test172.ams new file mode 100644 index 000000000..d000ef44a --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test172.ams @@ -0,0 +1,97 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test172.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +---------------------------------------------------------------------- +-- File : test172.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test is done for checking the correct implementation +-- of the simultaneous if equation statement.it checks +-- nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +port (input: in bit; + output: out bit); +end entity; + +architecture atest of test is +terminal t1, t2: electrical; +quantity v1 across i1 through t1 to t2; +quantity v2 across t2; +begin + +e1: v1== 1.0; +e2: v2==0.0; + + if (v1==1.0) use + output <= '1'; + else + output <='0'; + end use; + + if (v2==2.0) use + output <='0'; + else + output <='1'; + end use; +end architecture atest; +use work.electricalSystem.all; +--entity tb is +--port (tinput: in bit; +-- toutput: out bit); +--end entity; +--architecture atb of tb is +--terminal tt1, tt2: electrical; +--quantity tv1 across ti1 through tt1 to tt2; +--quantity tv2 across tt2; +--begin + +--tv1==1.0; +--tv2==0.0; + +--end architecture atb; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test173.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test173.ams new file mode 100644 index 000000000..9dc65ca45 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test173.ams @@ -0,0 +1,76 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test173.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +---------------------------------------------------------------------- +-- File : test173.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test is done for checking the correct implementation +-- of the simultaneous if equation statement.it checks +-- nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal t1, t2: electrical; +quantity v1 across i1 through t1 to t2; +quantity v2 across t2; + +begin +e1: v1== 1.0; +e2: v2==0.0; + + if (v1==1.0) use + output <= '1'; + end use; + + if (v2==2.0) use + output <='1'; + end use; +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test174.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test174.ams new file mode 100644 index 000000000..a262a8e6c --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test174.ams @@ -0,0 +1,90 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test174.ams,v 1.1 2002-03-27 22:11:20 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +---------------------------------------------------------------------- +-- File : test174.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple resistor model... +-- the test is done for checking the correct implementation +--of the simultaneous case statement.it checks +--nature declaration, terminal and quantity declarations + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH Ground reference ; + FUNCTION SIN (X : real ) RETURN real; + FUNCTION EXP (X : real ) RETURN real; +END PACKAGE electricalSystem; + +USE work.electricalSystem.all; + +ENTITY simcase IS +END simcase; + +ARCHITECTURE asimcase OF simcase IS + + terminal T1, T2 : electrical; + + quantity v1 across i1 through T1 ; + quantity v2 across i2 through T1 to T2; + quantity v3 across i3 through T2 ; + +BEGIN + + eqn1 : v1 == 1.0; + +c1: case (v1*2.0) use + + when (2.0) => + v2 == i2 * 100.0; + v3 == i3 * 100.0; + when (6.0) => + v2 == i2 * 200.0; + v3 == i3 * 200.0; + when (10.0) => + v2 == i2 * 300.0; + v3 == i3 * 300.0; + when others => + v2 == i2 * 400.0; + v3 == i3 * 400.0; + end case c1; + +END asimcase ; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test175.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test175.ams new file mode 100644 index 000000000..4db174b60 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test175.ams @@ -0,0 +1,87 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test175.ams,v 1.1 2002-03-27 22:11:20 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +---------------------------------------------------------------------- +-- File : test175.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test is done for checking the correct implementation +-- of the simultaneous case statement.it checks +-- nature declaration, terminal and quantity declarations + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH Ground reference ; + FUNCTION SIN (X : real ) RETURN real; + FUNCTION EXP (X : real ) RETURN real; +END PACKAGE electricalSystem; + + +USE work.electricalSystem.all; + +ENTITY simcase IS +END simcase; + +ARCHITECTURE asimcase OF simcase IS + + terminal T1, T2 : electrical; + + quantity v1 across i1 through T1 ; + quantity v2 across i2 through T1 to T2; + quantity v3 across i3 through T2 ; + +BEGIN + + eqn1 : v1 == 1.0; + eqn2 : v2 == 2.0; +c1: case (v1*2.0) use + + when (2.0) use + if (v2==2.0) use + v2 == i2 * 100.0; + else + v2 ==i2*10.0; + end use; + when (6.0) use + v2 == i2 * 200.0; + when (10.0) use + v2 == i2 * 300.0; + end case c1; +END asimcase ; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test176.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test176.ams new file mode 100644 index 000000000..90fd6535e --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test176.ams @@ -0,0 +1,80 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test176.ams,v 1.1 2002-03-27 22:11:20 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +---------------------------------------------------------------------- +-- File : test176.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test is done for checking the correct implementation +--of the simultaneous null statement.it checks +--nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity V1 across I1 through T1 to T2; +quantity V2 across I2 through T2; +--quantity V3 across I3 through T2; +quantity VS across T1; + +begin + + V1==1.0; + if (V1<=1.1) use + NULL; + else + V2 == 1.0; + end use; + + +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; + diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test182.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test182.ams new file mode 100644 index 000000000..ee24ac1e1 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test182.ams @@ -0,0 +1,71 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test182.ams,v 1.1 2002-03-27 22:11:20 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +---------------------------------------------------------------------- +-- File : test182.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test is done for checking the correct implementation +-- of the 'above attribute. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN (X : real ) RETURN real; + FUNCTION EXP (X : real ) RETURN real; +END PACKAGE electricalSystem; + + +USE work.electricalSystem.all; + +entity test is +port(signal vout:out boolean); +end entity; + +architecture atest of test is + +terminal T1: electrical; +quantity vin across iin through T1; +--constant vt: real:=3.0; +begin +e2 : vout <= vin'above(0.0); +e1: vin == 5.0 * sin(2.0 *3.141592 *100000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test183.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test183.ams new file mode 100644 index 000000000..f0ea59d1c --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test183.ams @@ -0,0 +1,60 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test183.ams,v 1.1 2002-03-27 22:11:20 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +-- this model tests for the correst implementation of the 'above +-- statement. +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH; + FUNCTION SIN(X : real) RETURN real; + alias ground is electrical'reference; +END PACKAGE electricalSystem; + +use work.electricalsystem.all; + +entity product is +generic(bound:real:=1.0); +port( + quantity out1:real); +end product; + +architecture pro of product is +constant in1:real:=10.0; +constant in2:real:=1.0; +signal outofbound:out boolean; + +begin + outofbound<=true; + out1== in1*in2; + outofbound<=out1'above(bound); + +end pro; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test184.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test184.ams new file mode 100644 index 000000000..300528f86 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test184.ams @@ -0,0 +1,109 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test184.ams,v 1.1 2002-03-27 22:11:20 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +--------------------------------------------------------------------- +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +---------------------------------------------------------------------- +-- File : test100.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- half wave Rectifier model ... +-- the test is done for checking the correct implementation +-- of the simultaneous if statement.it checks +-- nature declaration, terminal and quantity declarations. + +---------------------------------------------------------------------- +-- T1 diode D T2 +-- o-----|>|-----o-------o The circuit comprises: +-- | | i) A diode . +-- ( ) >R=100ohms ii) A sinusoidal voltage source. +-- |Vs = 5sinwt > iii)A resistor R. +-- | > +-- |_____________|_______o +-- |gnd +-- ----- +---------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH; + FUNCTION SIN (X : real ) RETURN real; + FUNCTION EXP (X : real ) RETURN real; +END PACKAGE electricalSystem; + +---------------------------------------------------------------------- + +USE work.electricalSystem.all; + +ENTITY hwr IS +END hwr; + +ARCHITECTURE ahwr OF hwr IS + + terminal T1, T2 : electrical; + quantity VDiode across IDiode through T1 to T2; + quantity V2 across I2 through T2 to electrical'reference; + quantity VS across T1 to electrical'reference; + + CONSTANT saturation_current : real := 0.0000000000001; + CONSTANT Vt : real := 0.025; + + CONSTANT BV : real := 100.0; + CONSTANT neg_sat : real := -saturation_current; + +BEGIN + + --diode equations + if( vDiode >= (-1.0 * Vt)) USE + eq1: iDiode == saturation_current * (exp(vDiode/Vt) - 1.0); + + ELSIF ((vDiode < (-3.0 * Vt)) AND (vDiode > -BV)) use + eq2: iDiode == neg_sat; + + ELSE + eq3: iDiode == neg_sat * (exp(-(BV + vDiode)/Vt) - 1.0 + + saturation_current); + END USE ; + + eqn2: v2 == 100.0 * i2; + + eqn4: vs == 5.0 * sin(2.0 * 3.14 * 100000.0 * + real(time'pos(now)) * 1.0e-15 ); + +END ahwr ; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test185.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test185.ams new file mode 100644 index 000000000..6b5abf221 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test185.ams @@ -0,0 +1,56 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test185.ams,v 1.1 2002-03-27 22:11:20 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN (X : real ) RETURN real; + FUNCTION EXP (X : real ) RETURN real; +END PACKAGE electricalSystem; + +USE work.electricalSystem.all; + +ENTITY simcase IS +END simcase; + +ARCHITECTURE asimcase OF simcase IS + + terminal T1: electrical; + + quantity v1 across i1 through T1 ; + +BEGIN + eq1: v1==1.0; + if (v1<=1.0) use + e1: null; + end use; +END asimcase ; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/voltage_doubler.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/voltage_doubler.ams new file mode 100644 index 000000000..4213dbee6 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/voltage_doubler.ams @@ -0,0 +1,227 @@ + +-- Copyright (C) 1997-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: voltage_doubler.ams,v 1.1 2002-03-27 22:11:20 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- Title : Voltage doubler circuit +-- Project : Mixed signal simulation +---------------------------------------------------------------------- +-- File : voltageDoubler.ams +-- Author : Kathiresan Nellayappan <knellaya@ececs.uc.edu> +-- Chandrashekar L Chetput <cchetput@ececs.uc.edu> +-- Created : 26.11.1997 +---------------------------------------------------------------------- +-- Description : +-- VHDL-AMS description of a voltage doubler circuit +-- STRUCTURAL DESCRIPTION. +---------------------------------------------------------------------- +-- +-- The ciruit schematic for the voltage doubler circuit is as below: +-- ================================================================= +-- +-- T1 C1 T2 diode D2 T3 +-- o_________||_____o_____|<|________o_____o_ The circuit comprises: +-- | || | | i)A sinusoidal voltage +-- | 1microF | | source. +-- ( ) __ _____ ii) 2 capacitors. +-- |Vs \/diode ----- C2 = 1microF iii) 2 diodes. +-- |=10sinwt -- D1 | +-- | | | +-- | | | +-- o________________|________________|_____o_ +-- |gnd +-- ----- +-- The diode is modelled as a component and then instantiated twice. +-- The diode model used is a spice behavioral model of a real diode. +-- +---------------------------------------------------------------------- + + +--Package defining eleectrical nature and some functions... +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; + +---------------------------------------------------------------------- +-- The diode component definition..... +USE work.electricalSystem.ALL; + +---------------------------------------------------------------------- +-- Schematic of the diode component: +-- +-- Ta o----|>|----o Tb +-- +---------------------------------------------------------------------- + +ENTITY diodeReal IS + PORT( TERMINAL ta,tb : electrical); +END diodeReal; + + +ARCHITECTURE behavior OF diodeReal IS + + QUANTITY d_V ACROSS d_I THROUGH ta TO tb; + CONSTANT saturation_current : real := 0.0000000000001; + CONSTANT Vt : real := 0.025; + CONSTANT neg_sat : real := -saturation_current; + CONSTANT IBV : real := 0.001; + CONSTANT PI : real := 3.14159_26535_89793_23846; + CONSTANT BV : real := -100.0; + +BEGIN + + IF( d_V >= ((-5.0) * Vt) ) USE + diode1St1: d_I == saturation_current * (exp(d_V/Vt) - 1.0); + ELSIF( (d_V < ((-5.0) * Vt)) AND (d_V > BV)) USE + diode1St2: d_I == neg_sat; + ELSIF(d_V = BV) USE + diode1St3: d_I == -IBV; + ELSE + diode1St4: d_I == neg_sat * (exp((BV + d_V)/Vt) -1.0 +((-BV)/Vt)); + END USE; + +END ARCHITECTURE behavior; + +---------------------------------------------------------------------- +-- The capacitor definition begins..... +USE work.electricalSystem.ALL; +---------------------------------------------------------------------- +-- Schematic of the capacitor component: +-- +-- Ta1 o----||----o Tb1 +-- +---------------------------------------------------------------------- +--entity declaration. +ENTITY capacitor IS + --capacitance value given as a generic parameter. + GENERIC( C : real := 1.0e-6); + PORT( TERMINAL ta1,tb1 : electrical);--Interface ports. +END capacitor; + +--architecture declaration. +ARCHITECTURE capbehavior OF capacitor IS +--quantity declarations. +-- --voltage across and current through the capacitor. + quantity Vc across Ic through ta1 to tb1; + +BEGIN + + Ic == C*Vc'dot; -- The ohmic resistance equation. + +END ARCHITECTURE capbehavior; +---------------------------------------------------------------------- +-- The sinusoidal voltage source definition begins..... +USE work.electricalSystem.ALL; +---------------------------------------------------------------------- +-- Schematic of the sinusoidal voltage source: +-- ------------------------------------------- +-- +-- Ta2 o----(~)----o Tb2 a sinusoidal voltage of amplitude V +-- Vs and frequency 'f'. +---------------------------------------------------------------------- +--entity declaration. +ENTITY sineSource IS + --frequency value and voltage value given as generic parameters. + GENERIC( f : real := 100000.0; + v : real := 10.0 ); + PORT( TERMINAL ta2,tb2 : electrical);--Interface ports. +END sineSource; + +--architecture declaration. +ARCHITECTURE sinebehavior OF sineSource IS +--quantity declarations. + quantity Vsine across Isine through ta2 to tb2; + +BEGIN + + -- The sinusoidal voltage source equation. + vsource: Vsine == V * sin(2.0 * (22.0/7.0) * f * + real(time'pos(now)) * 1.0e-15); + +END ARCHITECTURE sinebehavior; + +---------------------------------------------------------------------- +--The description of the voltage doubler begins here..... + +USE work.electricalSystem.ALL; + +ENTITY voltage_doubler IS +END voltage_doubler; + +ARCHITECTURE vdBehavior OF voltage_doubler IS + + TERMINAL t1, t2, t3 : electrical; + + COMPONENT diodeRealComp + PORT(TERMINAL ta,tb : electrical); + END COMPONENT; + + FOR ALL : diodeRealComp USE ENTITY work.diodeReal(behavior); + + COMPONENT capacitorComp IS + GENERIC( C : real := 1.0e-6); + PORT( TERMINAL ta1,tb1 : electrical); + END COMPONENT; + + FOR ALL : capacitorComp USE ENTITY work.capacitor(capbehavior); + + COMPONENT sineSourceComp IS + GENERIC( f : real := 100000.0; + v : real := 10.0 ); + PORT( TERMINAL ta2,tb2 : electrical); + END COMPONENT; + + FOR ALL : sineSourceComp USE ENTITY work.sineSource(sinebehavior); + + CONSTANT C : real := 0.000001; + CONSTANT MATH_PI : real := 3.14159_26535_89793_23846; + +BEGIN + + C1: capacitorComp + PORT MAP(t1,t2); + + C2: capacitorComp + PORT MAP(t3,ground); + + d1: diodeRealComp + PORT MAP(t2,ground); + + d2: diodeRealComp + PORT MAP(t3,t2); + + vsource: sineSourceComp + PORT MAP(t1,ground); + +END ARCHITECTURE vdBehavior; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/wein_bridge.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/wein_bridge.ams new file mode 100644 index 000000000..5cf47ba8a --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/wein_bridge.ams @@ -0,0 +1,463 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: wein_bridge.ams,v 1.1 2002-03-27 22:11:20 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +-- REMARKS +-- ------- +-- TESTED : Works great for freq of 1.0 KHz - 30.0MHz +-- COMMENTS : The Values of R1_a and R1_b have to be 18.0k & 32.0K resp. +-- The freq. is given by the equation +-- F = 1/(2*PI*R*C) +-- where R=R3=R4 and +-- C=C3=C4. +--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +--************************************************************************* +-- Structural Level Model of a WEIN BRIDGE OSCILLATOR. +-- VHDL-AMS implementation +-- Developed at Distributed Processing Laboratory +-- University of Cincinnati +--************************************************************************* + +--######################################################################### +-- BLOCK DIAGRAM +-- ------------- +-- o V_out +-- | D1 +-- |__________|\_______________ +-- R1_a R1_b | |/ R2=10.0K | +-- -----^^^.^^^---o--------/\/\/\/\-----------| +-- | | T4 |__________/|_______________| +-- ------- | \| | +-- -- | D2 | +-- | |\ | +-- ------------------|-\ | +-- | \____________o T3 +-- | / | +-- -------------------|+/ | +-- | |/ | +-- |T1 T2 | +-- _________o__________||____o_____/\/\/\/\_____| +-- | | || +-- | | C4=16.0pF R4=10.0K +-- | < +-- C3 |16.0pF < R3=10.0K +-- ----- < +-- ----- | +-- | | +-- ------- ------- +-- -- -- +-- +--######################################################################### + + PACKAGE electricalsystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X:real) RETURN real; + FUNCTION COS(X:real) RETURN real; + FUNCTION EXP(X:real) RETURN real; + END PACKAGE electricalsystem; + +------------------------ RESISTOR --------------------------- + +use work.electricalsystem.all; + +entity resistor is + generic(res :real:=1.0 ); + port(terminal r_in,r_out: electrical); +end entity resistor; + +architecture behav of resistor is + quantity vr across ir through r_in to r_out; + +begin + vr==ir*res; +end architecture behav; + +------------------------ CAPACITOR--------------------------- +use work.electricalsystem.all; + +entity capacitor is + generic(cap :real:=1.0); + port(terminal c_in,c_out: electrical); +end entity capacitor; + +architecture behav of capacitor is + +quantity vc across ic through c_in to c_out; +begin + init: break vc=>0.0; + + ic==cap*vc'dot; +end architecture behav; + +---------------------------- Diode ----------------------------- +use work.electricalsystem.all; + +entity diode is +generic ( + Isat : real := 1.0e-14; -- saturatioin current + n : real := 1.0; -- emmission coefficient + bv : real := 1.0; -- reverse breakdown voltage + ibv : real := 1.0e-3; -- Breakdown current + rds : real := 1.0 -- Ohnic resistamce + ); +port (terminal pos, neg : electrical); +end diode; + +architecture behav of diode is + terminal td : electrical; + quantity vd across id through td to neg; + quantity vrd across ird through pos to td; + quantity vdiode : real := 2.0; + constant gmin : real := 1.0e-12; -- conductance + constant vt : real := 0.026; -- thermal voltage +begin -- behav + brk : break vd => 1.0; + diodecondition : if(vd >= -5.0*(vt*n)) use + dfow : id == ((isat*(exp(vd/(vt*n)) - 1.0)) + (gmin*vd)); + elsif(vd < -5.0*(vt*n) and (vd > -1.0*bv)) use + drev: id == ((-1.0*isat) + (gmin*vd)); + elsif vd = -1.0*bv use + dbv : id == -1.0*ibv; + elsif vd < -1.0*bv use + blbv : id == -1.0*Isat*(exp(-1.0*((bv + vd)/vt)) - 1.0 + (bv/vt)); + end use; + diododeres : vrd == ird * rds; + diodevolt : vdiode == vd + vrd; + +end behav; + +-------------------- NPN transistor --------------------------- +use work.electricalsystem.all; + +entity trans_npn is + port( terminal emitter,base,collector : electrical); +end trans_npn; + +architecture trans_behav of trans_npn is + +terminal t1,t2,t3,t4,t5,e,b :electrical; + +constant Lb :real:=0.5e-9; +constant rb1 :real:=1.0; +constant rb2 :real:=3.1; +constant rb3 :real:=2.7; +constant r_pi :real:=110.0; +constant c_pi :real:=18.0e-12; +constant gm :real:=0.88; +constant cc1 :real:=0.091e-12; +constant cc2 :real:=0.048e-12; +constant cc3 :real:=0.023e-12; +constant Le :real:=0.2e-9; +constant Rbase:real:=22.0; +constant Remit:real:=0.6; + + +quantity v1 across i1 through b to t1; +quantity v2 across i2 through t1 to t2; +quantity v3 across i3 through t2 to t3; +quantity v4 across i4 through t3 to t4; +quantity v_pi across i5 through t4 to t5; +quantity i6 through t4 to t5; +quantity v7 across i7 through t1 to collector; +quantity v8 across i8 through t2 to collector; +quantity v9 across i9 through t3 to collector; +quantity v10 across i10 through t5 to e; +quantity v11 across i11 through collector to t5; +quantity v_base across i_base through base to b; +quantity v_emit across i_emit through e to emitter; + + +BEGIN + + v1 ==Lb*i1'dot; + v2 ==i2*rb1; + v3 ==i3*rb2; + v4 ==i4*rb3; + v_pi==i5*r_pi; + i6 ==c_pi*v_pi'dot; + i7 ==cc1*v7'dot; + i8 ==cc2*v8'dot; + i9 ==cc3*v9'dot; + v10 ==Le*i10'dot; + i11 ==gm*v_pi; + v_base==rbase*i_base; + v_emit==remit*i_emit; + +end architecture trans_behav; + + +-------------------- PNP transistor --------------------------- +use work.electricalsystem.all; + +entity trans_pnp is + port( terminal emitter,base,collector : electrical); +end trans_pnp; + +architecture trans_behav of trans_pnp is + +terminal t1,t2,t3,t4,t5,e,b :electrical; + +constant Lb :real:=0.5e-9; +constant rb1 :real:=1.0; +constant rb2 :real:=3.1; +constant rb3 :real:=2.7; +constant r_pi :real:=110.0; +constant c_pi :real:=18.0e-12; +constant gm :real:=0.88; +constant cc1 :real:=0.091e-12; +constant cc2 :real:=0.048e-12; +constant cc3 :real:=0.023e-12; +constant Le :real:=0.2e-9; +constant Rbase:real:=22.0; +constant Remit:real:=0.6; + + +quantity v1 across i1 through t1 to b; +quantity v2 across i2 through t2 to t1; +quantity v3 across i3 through t3 to t2; +quantity v4 across i4 through t4 to t3; +quantity v_pi across i5 through t5 to t4; +quantity i6 through t5 to t4; +quantity v7 across i7 through collector to t1; +quantity v8 across i8 through collector to t2; +quantity v9 across i9 through collector to t3; +quantity v10 across i10 through e to t5; +quantity v11 across i11 through t5 to collector; +quantity v_base across i_base through b to base; +quantity v_emit across i_emit through emitter to e; + + +BEGIN + + v1 ==Lb*i1'dot; + v2 ==i2*rb1; + v3 ==i3*rb2; + v4 ==i4*rb3; + v_pi==i5*r_pi; + i6 ==c_pi*v_pi'dot; + i7 ==cc1*v7'dot; + i8 ==cc2*v8'dot; + i9 ==cc3*v9'dot; + v10 ==Le*i10'dot; + i11 ==gm*v_pi; + v_base==rbase*i_base; + v_emit==remit*i_emit; + +end architecture trans_behav; + + +--> Constant Voltage source +--------------------------- +use work.electricalsystem.all; +ENTITY voltSource IS + generic(amp:real:=22.0); + PORT( TERMINAL ta2,tb2 : electrical); +END voltSource; + +ARCHITECTURE voltbehavior OF voltSource IS + +terminal t1: electrical; +quantity V_volt across i_volt through t1 to tb2; +quantity V_drop across i_drop through ta2 to t1; + +BEGIN + V_volt == amp; + V_drop == i_drop*100.0; + +END ARCHITECTURE voltbehavior; + +-- ********* Structural Model Of a simple High Frequency OpAmp *********-- + +use work.electricalsystem.all; +entity op_amp is +port(terminal inverting_ip,non_inverting_ip,output :electrical); +end entity op_amp; + +architecture struct of op_amp is + +--> components + +COMPONENT trans_pnp is + port( terminal emitter,base,collector : electrical); +end component; +for all : trans_pnp use entity work.trans_pnp(trans_behav); + +COMPONENT trans_npn is + port( terminal emitter,base,collector : electrical); +end component; +for all : trans_npn use entity work.trans_npn(trans_behav); + +component resistor is +generic(res :real:=1.0 ); +port(terminal r_in,r_out: electrical); +end component; +for all: resistor use entity work.resistor(behav); + +component voltsource is +generic(amp:real:=22.0); +PORT( TERMINAL ta2,tb2 : electrical); +end component; +for all: voltsource use entity work.voltsource(voltbehavior); + +terminal t1,t2,t3,t4,t5,t6,t7,t8,t9,t10:electrical; +terminal V_pos,V_neg: electrical; + +BEGIN + + Q01_npn: trans_npn port map(emitter=>T2 ,base=>T1 ,collector=>T9); + Q02_npn: trans_npn port map(emitter=>T2 ,base=>T3 ,collector=>T4); + Q03_npn: trans_npn port map(emitter=>T5 ,base=>T6 ,collector=>T2); + Q04_npn: trans_pnp port map(emitter=>T7 ,base=>T4 ,collector=>T8); + Q05_npn: trans_npn port map(emitter=>output,base=>T8 ,collector=>V_pos); + + Res_i1 : resistor generic map(1.0e3) + port map(inverting_ip,T1); + Res_i2 : resistor generic map(1.0e3) + port map(non_inverting_ip,T3); + Res_a : resistor generic map(220.0e3) + port map(T6,V_pos); + Res_c1 : resistor generic map(13.0e3) + port map(T9,V_pos); + Res_c2 : resistor generic map(13.0e3) + port map(V_pos,T4); + Res_e4 : resistor generic map(10.0e3) + port map(V_pos,T7); + Res_b : resistor generic map(20.0e3) + port map(T6,V_neg); + Res_e3 : resistor generic map(1.3e3) + port map(T5,V_neg); + Res_c4 : resistor generic map(21.0e3) + port map(T8,V_neg); + Res_e5 : resistor generic map(12.0e3) + port map(output,V_neg); + + vpos : voltsource generic map(amp=>15.0) -- test case + port map(V_pos,ground); + vneg : voltsource generic map(amp=>-15.0) -- test case + port map(V_neg,ground); + +end architecture struct; + +--------------------------------------------------------------------- +------------------- WEIN BRIDGE OSCILLATOR --------------------- +--------------------------------------------------------------------- +use work.electricalsystem.all; + +entity wein_bridge_osc is +port( terminal signal_out :electrical); +end entity wein_bridge_osc; + +architecture struct of wein_bridge_osc is + +--> components +component op_amp is +port(terminal inverting_ip,non_inverting_ip,output :electrical); +end component; +for all:op_amp use entity work.op_amp(struct); + +component diode +generic ( + Isat : real := 1.0e-14; -- saturatioin current + n : real := 1.0; -- emmission coefficient + bv : real := 1.0; -- reverse breakdown voltage + ibv : real := 1.0e-3; -- Breakdown current + rds : real := 1.0 -- Ohnic resistamce + ); +port (terminal pos, neg : electrical); +end component; +for all : diode use entity work.Diode(behav); + +component capacitor is +generic(cap :real:=1.0); +port(terminal c_in,c_out: electrical); +end component; +for all: capacitor use entity work.capacitor(behav); + +component resistor is +generic(res :real:=1.0 ); +port(terminal r_in,r_out: electrical); +end component; +for all: resistor use entity work.resistor(behav); + +terminal t1,t2,t3,t4: electrical; + +begin + +op_amplifier : op_amp port map(inverting_ip=>t4,non_inverting_ip=>t1,output=>t3); + +D1 : diode port map(t3,signal_out); +D2 : diode port map(signal_out,t3); + +R1_a : resistor generic map(18.0e3) + port map(t4, ground); +R1_b : resistor generic map(32.0e3) + port map(t4,signal_out); +R2 : resistor generic map(10.0e3) + port map(signal_out,t3); +R3 : resistor generic map(10.0e3) + port map(t1,ground); +R4 : resistor generic map(10.0e3) + port map(t2,t3); + +C3 : capacitor generic map(16.0e-12) + port map(T1,ground); +C4 : capacitor generic map(16.0e-12) + port map(T1,T2); +end struct; + +---------------------------- Test Bench ----------------------------- + +use work.electricalsystem.all; + +entity testbench is +end entity; + +architecture basic of testbench is + +-->components +component wein_bridge_osc is +port( terminal signal_out :electrical); +end component; +for all: wein_bridge_osc use entity work.wein_bridge_osc(struct); + +terminal t1: electrical; + +quantity V_out across i_out through t1 to ground; + +BEGIN + +osc: wein_bridge_osc port map(T1); + +V_out == i_out*1.0e6; + +end basic; |