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Diffstat (limited to 'testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test')
80 files changed, 7125 insertions, 0 deletions
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test100.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test100.ams new file mode 100644 index 000000000..a3d35b4e0 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test100.ams @@ -0,0 +1,77 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test100.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test100.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple resistor model... +-- the test is done for checking the correct implementation +--of the simple simultaneous equation statement.it checks +--nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity V1 across I1 through T1 to T2; +quantity V2 across I2 through T2; +quantity V3 across I3 through T2; +quantity VS across T1; + +begin + +e1: V1 == I1*100.0; +e2: V2 == I2*10.0; +e3: V3 == I3*10.0; + +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test101.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test101.ams new file mode 100644 index 000000000..64a81a499 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test101.ams @@ -0,0 +1,76 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test101.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test101.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- this test checks teh correctness of the 'integ implementation. +-- it finds the integral of teh source voltage. +-- the input is a sine wave. +--------------------------------------------------------------------- +PACKAGE electricalSystem IS + + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +entity test is +end entity test; + +architecture atest of test is + + quantity vs : real; + quantity vout: real; + +begin + + vs== 5.0 * sin(2.0 * 3.1415 * 10.0 * real(time'pos(now)) * + 1.0e-15); + vout == vs'integ; + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test102.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test102.ams new file mode 100644 index 000000000..430b9b47b --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test102.ams @@ -0,0 +1,82 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test102.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test102.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks the correctness of the Q'integ usage on the RHS of +-- the simple simultaneous eqn. +-------------------------------------------------------------------- +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + + --ALIAS GND is electrical'reference; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +entity tank is +end tank; + +architecture atank of tank is + + terminal t1,t2 : electrical; + + constant r: real :=10.00; + constant c: real:=0.00000003; + + quantity vin across t1 to electrical'reference; + quantity vr across ir through t1 to t2; + quantity vc across ic through t2 to electrical'reference; + quantity q : real; + +begin + vr == ir*r; + q==c*vc; + ic==q'integ; + vin == 5.0 * sin(2.0 * 3.1415 * 10.0 * real(time'pos(now)) * + 1.0e-15); +end atank; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test103.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test103.ams new file mode 100644 index 000000000..880ea33d8 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test103.ams @@ -0,0 +1,85 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test103.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test103.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks the correctness of the simple simultaneous eqn. +-- implementation. This is also a test for the lexical analysis. +-------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUD REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +entity test is +end entity; + +architecture atest of test is + + terminal T1,T2,T3,T4,T5:electrical; + quantity v1 across i1 through T1 to T2; + quantity v2 across i2 through T2 to T4; + quantity v3 across i3 through T4 to T3; + quantity v4 across i4 through T2 to T5; + quantity v5 across i5 through T5 to T3; + quantity v6 across i6 through T2 to T3; + quantity vS across T1 to electrical'reference; + +begin + +e1: v1==i1*1.0; +e2: v2==i2*1.0; +e3: v3==i3*1.0; +e4: v4==i4*1.0; +e5: v5==i5*1.0; +e6: v6==i6*1.0; +es: vS==5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test104.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test104.ams new file mode 100644 index 000000000..d23ea0335 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test104.ams @@ -0,0 +1,91 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test104.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test104.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- this is a test that checks for the correct implementation of if use +--end use. The condition is checked by comparing the quantity against a +--known constant value. +----------------------------------------------------------------------- +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +entity test is + generic (vmax :real:=10.0); + port(terminal T1:electrical); +end entity; + +architecture atest of test is + +quantity vin across T1; +constant a:real:=1.0; +constant b:real:=2.0; +quantity vin1:real; +quantity vin2:real; + +begin + +vin == vmax/a; + +if (vin==10.0) use +e1: vin1==vmax*b; +else +e2: vin2==vmax; +end use; + + +--if(vin<vmax) use +--e3: vin==vmax/b; +--else +--e4: vin==vmax; +--end use; + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test105.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test105.ams new file mode 100644 index 000000000..d146c52ec --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test105.ams @@ -0,0 +1,79 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test105.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test105.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks for the correctness of quantity as a port declaration. +-- the circuit is a simple RC network with vout acting as thge output port. +-- a sine input is applied to the network. +------------------------------------------------------------------------- +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + FUNCTION COS(X : real) RETURN real; + --ALIAS GND is electrical'reference; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +entity test is + port(quantity vout:out real); +end entity; + +architecture atest of test is + terminal T1,T2:electrical; + quantity VR across IR through T1 to T2; + constant R:real:=100.0; + constant C:real:=1.0e-9; + quantity vout across T2; + quantity vin across T1; +begin + vsource: vin==5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + + vres: IR== VR/R; + cap: vout==C*IR'integ; + +end atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test106.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test106.ams new file mode 100644 index 000000000..c887f76c5 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test106.ams @@ -0,0 +1,86 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test106.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test106.ams +-- Author(s) : Geeta Balarkishnan (gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple resistor model... +-- the test is done for checking the correct implementation +--of the simple simultaneous equation statement.it checks +--nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +entity test is +end entity; + +architecture atest of test is + terminal T1,T2, T3, T4,T5,T6:electrical; + quantity VRgen across IRgen through T1 to T2; + quantity VLgen across ILgen through T2 to T3; + quantity VRin across IRin through T3; + quantity VR1 across IR1 through T4 to T5; + quantity VR1A across IR1A through T4 to T6; + quantity VC1A across IC1A through T6 to T5; + quantity VC1 across IC1 through T5; + quantity VS across T1; + constant C1: real:=3.5e-3; + constant C1A: real:=0.3e-3; +begin + + e1: VRgen == IRgen*10.0; + e2: VLgen == 0.5*ILgen'dot; + e3: VRin == IRin*500.0; + e4: VR1 == IR1*1.0; + e5: VR1A == IR1A*0.2; + e6: IC1 == C1 * VC1'dot; + e7: IC1A == C1A*VC1A'dot; + + esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test107.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test107.ams new file mode 100644 index 000000000..03d2eaa54 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test107.ams @@ -0,0 +1,152 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test107.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test107.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks for the correct impelmentation of the port terminal +-- decl. signal decl. of type real, type array decl. +-- the test performs a 4 bit digital to analog conversion. +---------------------------------------------------------------------- + +PACKAGE electricalsystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; +END electricalsystem; + +USE work.electricalsystem.all; +ENTITY dac is + port(inputvector : in bit_vector(3 downto 0); --inputvector is an array of 16 bits + terminal T1, T2: electrical); --terminal declarations +END dac; + +ARCHITECTURE behavior OF dac IS + + type temp_array is array(0 to 3) of integer; -- temp to store the array values + quantity vout across T1 to T2; --output of the dac + + signal vout_sig, vcopy : real; +BEGIN + + dac_process: PROCESS(inputvector) + variable a : temp_array := (0,0,0,0); + variable tmp : real; + + BEGIN + for index in 3 downto 0 loop + if inputvector(index) = '0' then + a(index) := 0; --bit to integer conversion done here + else a(index) := 1; + end if; + end loop; + + tmp := real(a(3)*8) + real(a(2)*4) + real(a(1)*2 + a(0)); --find the corresponding value of the binary + vout_sig <= tmp; + + END PROCESS dac_process; + + -- digital to analog conversion is done here + vout == vcopy; + + convert: process(vout_sig) + begin + vcopy <= TRANSPORT vout_sig; + end process; + +END behavior; +use work.electricalsystem.all; +ENTITY tb_dac is +end tb_dac; + +architecture stimuli of tb_dac is + signal myinputvector : bit_vector(3 downto 0); + terminal tout : electrical; + component dac port( inputvector : in bit_vector(3 downto 0); + terminal T1, T2: electrical); + end component; + for all: dac use entity work.dac(behavior); + +BEGIN + + unit:dac port map (myinputvector, tout, electrical'reference); + + stimuli_process: process + BEGIN + + myinputvector <= "0000"; + wait for 10 ns; + + myinputvector <= "0001"; + wait for 10 ns; + + myinputvector <= "0010"; + wait for 10 ns; + + myinputvector <= "0100"; + wait for 10 ns; + + myinputvector <= "1000"; + wait for 10 ns; + + myinputvector <= "1100"; + wait for 10 ns; + + myinputvector <= "1110"; + wait for 10 ns; + + myinputvector <= "1101"; + wait for 10 ns; + + myinputvector <= "1111"; + wait for 10 ns; + myinputvector <= "0000"; + wait for 10 ns; + + myinputvector <= "1100"; + wait for 10 ns; + + myinputvector <= "1010"; + wait for 10 ns; + + wait; + end process; +end stimuli; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test108.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test108.ams new file mode 100644 index 000000000..d8eb05903 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test108.ams @@ -0,0 +1,75 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test108.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test100.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple resistor model... +-- the test is done for checking the correct implementation +-- of the simple simultaneous equation statement.it checks +-- nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +entity test is +end entity; + +architecture atest of test is + terminal t1, t2: electrical; + quantity vd across id through T1; -- to T2; + quantity charge :real; + constant vt:real:=0.02; +begin + + p1: procedural is + begin + vd:=1.0*id; + end procedural; + +end architecture; + diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test109.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test109.ams new file mode 100644 index 000000000..3424a2d73 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test109.ams @@ -0,0 +1,80 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test109.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test109.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks for the correctness of the procedural statements. +-- multiple terms on the RHS +---------------------------------------------------------------------- +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUD REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + + --ALIAS GND is electrical'reference; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +entity test is +end entity; + +architecture atest of test is + terminal t1,t2: electrical; + quantity vd across id through t1 to t2; + quantity charge:real; + constant vt:real:=0.0258; + constant x:real:=1.0; + quantity ic:real; + +begin + p1: procedural + begin + id:=0.1*(exp((vd-1.0*id)/vt)-1.0); + charge := x*id; + ic:= charge'dot; + end procedural; + +end architecture; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test110.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test110.ams new file mode 100644 index 000000000..359bf84d0 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test110.ams @@ -0,0 +1,69 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test110.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +-- an example of a model having both a signal assignment statement +-- as well as a simple simultaneous statement. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND reference; + FUNCTION SIN (X : real ) RETURN real; + FUNCTION EXP (X : real ) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +use std.textio.all; +ENTITY test IS +END test; + +ARCHITECTURE behavior OF test IS + CONSTANT r1 : real := 100.0; -- value of R1 + terminal t1 : electrical; + QUANTITY vIn ACROSS t1; + QUANTITY vR ACROSS iR THROUGH t1 ; + signal y:bit:='0'; +BEGIN + +process(y) +begin + y <= not(y) after 1000 ns; + +end process; + + testbench:PROCESS + BEGIN + WAIT ON y; + END PROCESS; + res_stmt1: vR == iR * r1 ; + vsource: vIn == 5.0 * sin(2.0 * 3.14 * 100000.0 * real(time'pos(now)) * 1.0e-15); + +END ARCHITECTURE behavior; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test111.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test111.ams new file mode 100644 index 000000000..118ec318f --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test111.ams @@ -0,0 +1,75 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test111.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : model.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks the correctness of the Q'Tolerance. +-- the test checks for the simpel diode implementation +-- wherein the charge is evaluated wrt a relative tolerance value +---------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +entity test is + generic(a:real:=1.0e-10; b:real:=0.0); + port (terminal t1: electrical); +end entity; + +architecture atest of test is + quantity vd tolerance "reltol=1.0e-2" across id through t1; + quantity charge: real; + quantity ic : real; + constant rd: real:=1.0; +begin + e1: id== a*(sin((vd-id*rd)/0.5)-1.0); + e2: charge== b*id; + e3: ic==charge'dot; +end architecture; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test112.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test112.ams new file mode 100644 index 000000000..b50437f4d --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test112.ams @@ -0,0 +1,86 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test112.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : model.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks the correctness of the subtype declarations for the +-- through and across quantities. +---------------------------------------------------------------------- +PACKAGE electricalSystem IS + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; + +entity test is + +subtype voltage is real; +subtype current is real; +nature electrical is voltage across current through ground reference; + +end entity; + +architecture atest of test is + +constant R1: real :=10.0; +constant R2: real :=5.0; +constant R3: real :=1.0; +terminal T1,T2:electrical; +quantity V1 across I1 through T1 to T2; +quantity V2 across I2 through T2 to electrical'reference; +quantity V3 across I3 through T2 to electrical'reference; +quantity VS across T1 to electrical'reference; + +begin + +e1: V1 == I1*R1; +e2: V2 == I2*R2; +e3: V3 == I3*R3; + +esource:VS == 5.0 * sin(2.0 * 3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test113.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test113.ams new file mode 100644 index 000000000..81e546ea7 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test113.ams @@ -0,0 +1,79 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test113.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test113.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks the correctness of the Q'Tolerance for across qnty +-- and for the real quantity.The test checks for the simpel diode +-- implementation wherein the charge is evaluated wrt a relative +-- tolerance value +-- the test doesn't seem to take a tolerance associated with a +-- free quantity. we need to check on this!! (LRM : 4.3.1 spec +-- followed. +---------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +entity test is + generic(a:real:=1.0e-10; b:real:=0.0); + port (terminal t1: electrical); +end entity; + +architecture atest of test is + quantity vd across id through t1; -- to electrical'reference; + quantity charge:real tolerance "reltol=1.0e-2"; + --quantity ic : real; + constant rd: real:=1.0; +begin + e1: id== a*(sin((vd-id*rd)/0.5)-1.0); + e2: charge== b*id; + --e3: ic==charge'dot; +end architecture; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test114.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test114.ams new file mode 100644 index 000000000..1471d82c3 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test114.ams @@ -0,0 +1,77 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test114.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : model.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks the correctness of the two currents associated +-- as through between same terminals.for eg: consider 2 resistors in +-- parallel.. here vd is same and id and ic are the currents. +-- the test checks for the simpel diode implementation +-- wherein the charge is evaluated wrt a relative tolerance value +---------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +entity test is + generic(a:real:=1.0e-10; b:real:=0.0); + port (terminal t1: electrical); +end entity; + +architecture atest of test is + quantity vd across id, ic through t1; + quantity charge: real; + --quantity ic : real; + constant rd: real:=1.0; +begin + e1: id== ((vd-id*rd)/0.5); + e2: charge== b*id; + e3: ic==charge'dot; +end architecture; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test115.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test115.ams new file mode 100644 index 000000000..e71523f00 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test115.ams @@ -0,0 +1,79 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test115.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test115.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks for the correctness of the interface declaration: +-- quantity : in| out. +-- ref LRM 4.3.2 +--------------------------------------------------------------------- +PACKAGE electricalSystem IS + subtype voltage is real; + subtype current is real; + NATURE electrical is voltage across current THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +entity test is + port(quantity vout:out electrical); +end entity test; + +architecture atest of test is + terminal t1,t2: electrical; + + quantity vin across iin through t1; + quantity vr across ir through t1 to t2; + quantity vout across t1 to t2; + +begin + + e1: vin== 5.0 * sin(2.0 * 3.1415 * 10000000.0 * real(time'pos(now)) *1.0e-15); + e2: vr==ir*1.0; + e3: vout== vr; + +end architecture; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test116.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test116.ams new file mode 100644 index 000000000..87032a99a --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test116.ams @@ -0,0 +1,79 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test116.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test116.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks for the correctness of the interface declaration: +-- quantity : in| out. A simple R circuit with an ac voltage source +-- is used. +-- ref LRM 4.3.2 +--------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical is real across real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +entity test is + port(quantity vout:out voltage); +end entity test; + +architecture atest of test is + terminal t1,t2: electrical; + + quantity vin across iin through t1; + quantity vr across ir through t1 to t2; + quantity vout across t1 to t2; + +begin + + e1: vin== 5.0 * sin(2.0 * 3.1415 * 10000000.0 * real(time'pos(now)) *1.0e-15); + e2: vr==ir*1.0; + e3: vout== vr; + +end architecture; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test117.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test117.ams new file mode 100644 index 000000000..f9d993352 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test117.ams @@ -0,0 +1,83 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test117.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test117.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks the correctness of the subtype usage and also +-- checks for the tolerance aspect associated with the subtype. +---------------------------------------------------------------------- + +Package electricalsystem is + FUNCTION SIN(X : real) RETURN real; + +subtype voltage is real tolerance "default_voltage=1.0e-3"; +subtype current is real; -- tolerance "default_current= 1.0e-4"; +subtype resistance is real; + +nature electrical is voltage across current through ground reference; +end package electricalsystem; + +use work.electricalsystem.all; + +entity test is +end entity; + +architecture atest of test is +--subtype voltage is real tolerance "default_voltage=1.0e-3"; +--subtype current is real; -- tolerance "default_current= 1.0e-4"; +subtype resistance is real; + +nature electrical is voltage across current through; + +terminal t1, t2: electrical; +quantity vr tolerance across ir through t1 to t2; +quantity vs across t1; +--quantity vout across t2; + +begin +e1: vs==5.0 *sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +e2: vr==ir*1.0; + +end architecture; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test118.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test118.ams new file mode 100644 index 000000000..a9831e1ac --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test118.ams @@ -0,0 +1,93 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test118.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test118.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- + +-- the test checks for the correctness of the implemenatation of the case +-- statement. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + + --ALIAS GND is electrical'reference; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +entity test is +end entity test; + +architecture atest of test is + terminal t1:electrical; + signal ison: boolean; + quantity vr across ir through t1; + constant vt:real:=0.0258; +begin + +process + variable off : boolean:=true; +begin + ison <= not off; + case off is + when true=> + ison<= not off; + when false=> + ison<=off; + end case; +end process; + +source: vr==10.0 * sin(2.0 *(22.0/7.0)*100000.0*real(time'pos(now)) * 1.0e-15); +if ison use + ir== 5.0; --*(exp(vr/vt)-1.0); +else + ir==0.0; +end use; + +break on ison; + +end architecture; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test119.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test119.ams new file mode 100644 index 000000000..973d0f2db --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test119.ams @@ -0,0 +1,91 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test119.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test1.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- This is the simple resistor model that sets the foundation on which +-- we build SIERRA, the VHDL AMS simulator. The circuit consists of 3 +-- resistors connected to a voltage source. +-- T1 R1 T2 +-- o-----/\/\----o-------- +-- | | | +-- ( ) > > +-- |Vs = 5sinwt >R2 >R3 +-- | > > +-- |_____________|____|___ +-- |gnd +-- ---- +-------------------------------------------------------------------------- +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +entity test is +end entity; + +architecture atest of test is + + constant R1: real :=10.0; + constant R2: real :=5.0; + constant R3: real :=1.0; + terminal T1,T2:electrical; + quantity V1 across I1 through T1 to T2; + quantity V2 across I2 through T2 to electrical'reference; + quantity V3 across I3 through T2 to electrical'reference; + quantity VS across T1 to electrical'reference; + +begin + + e1: V1 == I1*R1; + e2: V2 == I2*R2; + e3: V3 == I3*R3; + + esource:VS == 5.0 * sin(2.0 * 3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test121.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test121.ams new file mode 100644 index 000000000..8166369d6 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test121.ams @@ -0,0 +1,80 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test121.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test3.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- this is to check the quantity: q'dot in the lhs and rhs of the +-- simultaneous statements +--------------------------------------------------------------------- +PACKAGE electricalSystem is + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +entity test is +end entity; + +architecture atest of test is + quantity x11: real; + constant x1:real:=2.0; + constant x2:real:=1.0; + constant m1 : real:=1.0; + quantity f : real; + quantity dx1 : real; + +begin +e1: f == 10.0* sin(2.0 * 3.141592 *10000.0 * real(time'pos(now))*1.0e-12); +e2: x11 == f*(x1-x2)/m1; +e3: dx1 == f'dot; + +-- x1'dot == f*(x1-x2)/m1; +-- x2'dot == f*(x1-x2)/m2; +-- xs == (m1*x1+m2*x2)/(m1+m2); +-- m3 == m1*x1'dot+ m2*x2'dot; +end atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test122.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test122.ams new file mode 100644 index 000000000..c3f9c096f --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test122.ams @@ -0,0 +1,80 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test122.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test122.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- to check for the correct implementation of the simple simultaneous +-- statements +------------------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + + --ALIAS GND is electrical'reference; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +entity chk is + + generic(i:real:=1.0e-9); + port(terminal t1, t2: electrical); + +end chk; + +architecture achk of chk is + quantity vd across id through t1 to t2; + quantity q: real; + quantity ic:real; + constant vth : real:= 0.025; +begin + +e1: id == i*(exp(vd/vth)-1.0); +e2: q == id*0.25; +e3: ic == q'dot; + +end achk; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test123.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test123.ams new file mode 100644 index 000000000..6e2699793 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test123.ams @@ -0,0 +1,82 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test123.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test113.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- to check the correct implementation of the simultaneous if statement +-- break and 'above is also used. it checks for the eqns v'=g*v**2 for +-- +g and -g. +---------------------------------------------------------------------- +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH; + FUNCTION SIN(X : real) RETURN real; +-- alias ground is electrical'reference; +END PACKAGE electricalSystem; + +use work.electricalsystem.all; +entity test is +end entity test; + +architecture atest of test is + + quantity v : real; + quantity s: real; + constant g : real :=9.81; + constant r : real:=1.02; + +begin + +break v=>0.0, s=>100.0; + +break v=>-v when not s'above(0.0); + +s'dot==v; + +if v>0.0 use + v'dot == -g+v*v*r; +else + v'dot == -g-v*v*r; +end use; + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test124.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test124.ams new file mode 100644 index 000000000..ee84d2125 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test124.ams @@ -0,0 +1,81 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test124.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test124.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- + +--this test is to chk the support of ALIAS, NATURE in the PACKAGE declaration +--the test also chks the corrct use of quantity and terminal declarations. +-------------------------------------------------------------------------- +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; +END PACKAGE electricalSystem; + +--entity declaration + +use work.electricalsystem.all; +ENTITY Rckt IS + +END Rckt; + +--architecture declaration + +ARCHITECTURE aRckt OF Rckt IS + + + terminal T1, T2 : electrical; + + quantity VR across IR through T1 to T2; + quantity VR1 across IR1 through T2; + quantity VS across T1; + constant R : REAL := 10.00; + +BEGIN + +eqn1 : VR == IR * R; +e2: VR1 == IR1 * R; +eqn2 : VS == 5.0; + +end arckt; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test125.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test125.ams new file mode 100644 index 000000000..6b82f12a1 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test125.ams @@ -0,0 +1,60 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test125.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +-- this model tests for the correst implementation of the 'above +-- statement. +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH; + FUNCTION SIN(X : real) RETURN real; + alias ground is electrical'reference; +END PACKAGE electricalSystem; + +use work.electricalsystem.all; + +entity product is +generic(bound:real:=1.0); +port( + quantity out1:real); +end product; + +architecture pro of product is +constant in1:real:=10.0; +constant in2:real:=1.0; +signal outofbound:out boolean; + +begin + outofbound<=true; + out1== in1*in2; + outofbound<=out1'above(1.0); + +end pro; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test126.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test126.ams new file mode 100644 index 000000000..2c8c320e3 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test126.ams @@ -0,0 +1,78 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test126.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test8.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks the corretness of the 'left 'right 'high 'low +-- 'ascending 'length declarations. +---------------------------------------------------------------------- +entity test is +port (y: out bit); +end test; + +architecture atest of test is +type value is range 10 downto 0; +signal a: bit; +begin + + y<=a; +e1:process +begin +if (value'left=10)then + a <='1'; + else + a <='0'; + end if; + assert (value'right=0) + report "pass 'right check" + assert(value'high=10) + report "pass 'high check" + assert (value'low=0) + report "pass 'low check" + assert (value'ascending=false) + report "pass 'ascending check" + assert (value'length=11) + report "pass 'length check" +end process; +end atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test127.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test127.ams new file mode 100644 index 000000000..09f2cceb9 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test127.ams @@ -0,0 +1,75 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test127.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test9.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- + +--this checks the step limit specification incorporated. +--this gives atleast 20 analog solution points if the +--" STEP LIMIT' is implemented correctly. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + + --ALIAS GND is electrical'reference; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity source is +generic (Amplitude :real:=1.0; + frequency:real:=1.0); +port (quantity sine:out real); +end entity source; + +architecture asource of source is + limit sine:real with 0.05/frequency; + +begin +e1: sine== Amplitude*sin(2*3.14159*frequency*real(time'pos(now))*1.0e-12); + +end architecture asource; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test128.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test128.ams new file mode 100644 index 000000000..760a2c40e --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test128.ams @@ -0,0 +1,86 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test128.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test104.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- this is a test that checks for the correct implementation of if use +-- end use. The condition is checked by comparing the quantity against a +-- known constant value. +----------------------------------------------------------------------- +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + + --ALIAS GND is electrical'reference; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +entity test is +end entity; + +architecture atest of test is + terminal T1, T2:electrical; + + quantity vin across T1 to electrical'reference; + constant a:real:=1.0; + constant b:real:=2.0; + + quantity vin1 across iin1 through T1 to T2; + quantity vin2 across iin2 through T2 to electrical'reference; +begin + +eq1: vin==5.0* sin(2.0 * 3.141592 *1000.0 * real(time'pos(now))*1.0e-12); +eq2: vin1== iin1*a; +eq3: vin2== iin2*b; +if (vin1>5.0) and (vin1<10.0) use +e1: vin1==vin/a; +elsif (vin2<5.0) use +e2: vin2==vin/b; +else +e3: vin1==vin; +end use; +end atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test129.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test129.ams new file mode 100644 index 000000000..052c634b1 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test129.ams @@ -0,0 +1,100 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test129.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +package electricalSystem is + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION POW(X,Y: real) RETURN real; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + type electrical_vector is array(0 to 3) of electrical; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; + +entity test is +generic( a: real); +port( terminal ip: electrical_vector; + terminal op:electrical); +end entity; + +architecture atest of test is +type electrical_vector is array(0 to 3) of electrical; +--variable i: real:=0.0; +variable a:real:=5.0; +variable output:real:=0.0; +quantity vin across ip to electrical'reference; +quantity vout across iout through ip to op; +begin + + for i in 0 to 3 loop + output:=output + vin(i)*a; + end loop; +vout:=output; + +end architecture atest; +-- test bench needs to be corrected + +use work.electricalSystem.all; +entity tb is +end entity; + +architecture atb of tb is +signal myvector : electrical_vector(0 to 3); +terminal tip : electrical_vector; +terminal top:electrical; +component test + port(terminal ip, op: electrical); +end component; +for all: test use entity work.test(atest); +begin + +unit: test port map(tip, top, electrical'reference); + +a_process: process +begin + +myvector == 1.0; +wait for 10 ns; +myvector == 2.0; +wait for 10 ns; +myvector == 2.0; +wait for 10 ns; +myvector ==1.0; +wait for 10 ns; + +wait; + +end process; + +end atb; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test130.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test130.ams new file mode 100644 index 000000000..7ac92b5bd --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test130.ams @@ -0,0 +1,98 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test130.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +package electricalSystem is + NATURE electrical IS real ACROSS real THROUGH; + FUNCTION POW(X,Y: real) RETURN real; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + type electrical_vector is array(0 to 3) of electrical; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; + +entity test is +port( terminal ip: electrical_vector; + terminal op:electrical); +end entity; + +architecture atest of test is +type electrical_vector is array(0 to 3) of electrical; +type t_a is array(0 to 3) of real; +variable i: real:=0.0; +variable output:real:=0.0; +quantity vin across ip to electrical'reference; +quantity vout across iout through ip to op; +begin +t1: process + variable a: t_a :=(1.0, 1.2, 1.5, 2.0); + for i in 0 to 3 loop + output:=output + vin(i)*a(i); + end loop; +vout:=output; +end architecture atest; + +use work.electricalSystem.all; +entity tb is +end entity; + +architecture atb of tb is +signal myvector : electrical_vector(0 to 3); +terminal tip : electrical_vector; +terminal top:electrical; +signal myconst : real_vector(0 to 3); +component test + port(terminal ip, op: electrical); +end component; +for all: test use entity work.test(atest); +begin + +unit: test port map(tip, top, electrical'reference); + +a_process: process +begin + +myvector == 1.0; +wait for 10 ns; +myvector == 2.0; +wait for 10 ns; +myvector == 2.0; +wait for 10 ns; +myvector==1.0; +wait for 10 ns; +wait; + +end process; + +end atb; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test133.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test133.ams new file mode 100644 index 000000000..7a0e28bac --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test133.ams @@ -0,0 +1,77 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test133.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test133.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- this test checks the correctness of the break statement for a +-- quantity port declaration. +-- LRM ref: 8.14 +---------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + subtype voltage is real; + +END PACKAGE electricalSystem; + +use work.electricalSystem.all; + +entity test is + generic (m: real := 1.0); + port (quantity x: out voltage); +end entity test; + +architecture atest of test is +--quantity x: real; +quantity q: real; +begin + break x => 0.0, x'dot => 0.1; + e1: q== x'dot; + x'dot'dot == -1.0*( m*(x*x - 1.0)* x'dot); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test134.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test134.ams new file mode 100644 index 000000000..de8f2e1ef --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test134.ams @@ -0,0 +1,98 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test134.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test151.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- this is a test to check the corretness of the implemntation of the break +-- statement and also the use of quantity port of type voltage. +-- this is a vco model which first sets the initial condition +-- using a break statement. Then again, a break statement is applied to keep +-- the phase within 0-2pi. Thr output voltage eqn is obtained as vout and the +-- phase eqn as phase'dot. +-- LRM ref: 8.14, 4.3.2. +---------------------------------------------------------------------- +PACKAGE electricalSystem IS + SUBTYPE voltage is real; + NATURE electrical IS real ACROSS real THROUGH; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; + +entity vco is + generic( + fc: real := 1.0e6; -- VCO frequency at Vc + df: real := 0.5e6; -- [Hz/V], frequency characteristic slope + Vc: voltage := 0.0 -- centre frequency input voltage + ); + port( quantity Vin: in voltage; + terminal OutTerminal: electrical); +end entity VCO; + +architecture avco of vco is + constant TwoPi: real := 6.283118530718; -- 2pi + + quantity Phase : real; + + -- define a branch for the output voltage source + + quantity Vout across Iout through OutTerminal to electrical'reference; + +begin + -- use break to set the phase initial condition + break Phase => 0.0; + + -- another break statement keeps the phase within 0.. 2pi + break Phase => Phase mod TwoPi on Phase'above(TwoPi); + + -- phase equation + Phase'dot == TwoPi*realmax(0.5E6, fc+(Vin-Vc)*df); + + -- output voltage source equation + Vout == 2.5*(1.0+sin(Phase)); + +end architecture avco; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test135.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test135.ams new file mode 100644 index 000000000..d247089fc --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test135.ams @@ -0,0 +1,71 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test135.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground refernce; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; + +USE use.electricalSystem.all; +ENTITY vpwl IS + GENERIC (v0 : real := 0.0); + PORT (SIGNAL slope : in real; + TERMINAL p, m : electrical); +END ENTITY vpwl; + +ARCHITECTURE one OF vpwl IS + QUANTITY v ACROSS i THROUGH p TO m; +BEGIN + v==v0; + BREAK WHEN slope'event; + v'dot == slope; +END ARCHITECTURE one; + +entity tb is +end entity; +architecture atb of tb is +signal myinput: real; + +begin + myinput<='1'; +ARCHITECTURE two OF vpwl IS + QUANTITY v ACROSS i THROUGH p TO m; + SIGNAL startv : voltage := v0; +BEGIN + BREAK WHEN slope'event; + startv <= v WHEN slope'event; + v == startv + slope'delayed * startv'last_event; +END ARCHITECTURE two; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test136.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test136.ams new file mode 100644 index 000000000..09357f084 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test136.ams @@ -0,0 +1,82 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test136.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test136.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A resistor bridge network... +-- the test is done for checking the correct implementation +-- of the simple simultaneous equation statement.it checks +-- nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +entity test is +end entity; + +architecture mesh of test is + +terminal t1, t2, t4 : electrical; +quantity v1 across i1 through t1 to t2; +quantity v2 across i2 through t2; +quantity v3 across i3 through t4; +quantity v4 across i4 through t1 to t4; +quantity v5 across i5 through t1; +quantity vs across t1; + +begin + +e1: v1== i1*10.0; +e2: v2== i2*10.0; +e3: v3== i3*10.0; +e4: v4== i4*10.0; +e5: v5== i5*20.0; + +esource: vs== 10.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-15); + +end architecture mesh; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test137.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test137.ams new file mode 100644 index 000000000..43c4d6dc9 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test137.ams @@ -0,0 +1,136 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test137.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------------- +-- File : test137.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +----------------------------------------------------------------------------- +-- Description : +----------------------------------------------------------------------------- +-- the test cheks the correctness of the electrical_vector.array of terminals +-- also the use of real vectors.. array of real values. +-- the circuit is a weighted summer the output is available at the +-- ooutput terminal o. +-- LRM 4.3.2 +------------------------------------------------------------------------------- +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + TYPE real_vector is array(0 to 3) of real; + TYPE electrical_vector is array(0 to 3) of electrical; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +generic (beta,gamma : real_vector); +port(terminal inp, inm: electrical_vector; + terminal o: electrical); +end entity; +architecture atest of test is +--TYPE real_vector is array(0 to 3) of real; +--TYPE electrical_vector is array(0 to 3) of electrical; +quantity vp across ip through inp to electrical'reference; +quantity vm across inm to electrical'reference; +quantity vo across io through o to electrical'reference; +variable bvs, gvs : real:=0.0; +function "*" (a:real_vector; + b: electrical_vector'across) +return real is + +variable result : real:=0.0; +begin + +for i in (0 to 3) loop + result:= result+ a(i)*b(i); +end loop; +return result; +end function "*"; +begin +vo== beta*vp - gamma*vm; +end architecture atest; + +use work.electricalSystem.all; + +entity tb is +end entity; + +architecture atb of tb is +signal myvec1,myvec2:real_vector(0 to 3); +signal myinput1, myinput2: electrical_vector(0 to 3); +terminal tinp, tinm: electrical_vector; +terminal to: electrical; + +component test + port(terminal inp, inm: electrical_vector; + terminal o: electrical); +end component test; +for all: test use entity work.test(atest); +begin +unit: test port map(tinp,tinm, to, electrical'reference); +a_process: process +begin + +myvec1 == 1.0; +myinput1 == 1.0; +myvec2 == 2.0; +myinput2 == 2.0; +wait for 10 ns; +myvec1 == 1.0; +myinput1 == 1.0; +myvec2 == 2.0; +myinput2 == 2.0; +wait for 10 ns; +myvec1 == 1.0; +myinput1 == 2.0; +myvec2 == 2.0; +myinput2 == 1.0; +wait for 10 ns; +myvec1 == 1.0; +myinput1 == 2.0; +myvec2 == 2.0; +myinput2 == 1.0; +wait for 10 ns; + +end process; + +end atb; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test138.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test138.ams new file mode 100644 index 000000000..4c11b3aeb --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test138.ams @@ -0,0 +1,72 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test138.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +package mosdata is +-- + type mosmodel is + record + vt0 : real; + kp : real; + end record mosmodel; + + nature electrical is real across real through ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + +end package mosdata; + +use work.mosdata.all; + +entity test is +generic ( + model: mosmodel:=( + vt0 => 0.7, + kp => 1.0); + + constant a: real:=1.0 + ); +end entity; + +architecture atest of test is +terminal t1, t2: electrical; +quantity vr across ir through t1 to t2; +quantity vs across t1; + +begin +e1: vs== 5.0 * sin(2.0 * 3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +e2: vr== ir* model.kp*a + model.vt0; + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test139.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test139.ams new file mode 100644 index 000000000..16e5a9ebf --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test139.ams @@ -0,0 +1,122 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test139.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +----------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +----------------------------------------------------------------------- +-- File : test139.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +----------------------------------------------------------------------- +-- Description : +----------------------------------------------------------------------- +-- this test checks the correctness of the record declaration as a type +-- it also checks for the usage of the record element declarations. +-- the assert statement is also checked. +-- the record is declared within a package +-- the test also checks the correctness of the function impelmentation. +-- the function accepts the record parameters and returns the result of +-- type real. +----------------------------------------------------------------------- +PACKAGE electricalsystem IS + + SUBTYPE voltage IS real; + SUBTYPE current IS real; + + NATURE electrical IS + voltage ACROSS + current THROUGH ground reference; + +END PACKAGE electricalsystem; + +PACKAGE types IS + + TYPE cmodel IS RECORD + cj : real; + cjsw : real; + defw : real; + narrow : real; + END RECORD; + +END PACKAGE types; + +USE work.electricalsystem.all; +USE work.types.all; + +ENTITY test IS + GENERIC (cnom : real := 0.0; + model : cmodel := (0.0, 0.0, 1.0e-6, 0.0); + l : real := 0.0; + w : real := 0.0; + ic : real := 0.0 ); + PORT (TERMINAL t1,t2 : electrical); +END ENTITY test; + +ARCHITECTURE atest OF test IS + FUNCTION c_init ( cnom : real; + model : cmodel; + l, w : real) + RETURN real IS + VARIABLE ceff : real; -- effective capacitance value + VARIABLE weff : real; -- effective channel width + BEGIN + + IF cnom /= 0.0 THEN + ASSERT (model.cj = 0.0 AND model.cjsw = 0.0) + REPORT "Both cnom and model specified"; + ceff := cnom; + ELSE + ASSERT (l > 0.0) + REPORT "Channel length not specified"; + IF w = 0.0 THEN + weff := model.defw; + ELSE + weff := w; + END IF; + ASSERT (weff > 0.0) + REPORT "Channel width not specified"; + ceff := model.cj*(l-model.narrow)*(weff-model.narrow) + + model.cjsw*(l+weff-2.0*model.narrow); + END IF; + RETURN (ceff); + END FUNCTION c_init; + + CONSTANT ceff : real := c_init(cnom, model, l, w); + QUANTITY v ACROSS i THROUGH t1 TO t2; +BEGIN + i == ceff * v'dot; +END ARCHITECTURE atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test140.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test140.ams new file mode 100644 index 000000000..f43142bac --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test140.ams @@ -0,0 +1,77 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test140.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test140.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks for the correctness of the quantity, terminal, nature +-- and package declarations. the terminals are assigned as terminals. +-- a simple V-R circuit is considered. +----------------------------------------------------------------------- + +PACKAGE electricalsystem IS + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +-- SUBTYPE voltage IS real; +-- SUBTYPE current IS real; + +NATURE electrical IS real ACROSS real THROUGH ground reference; + +END PACKAGE electricalsystem; +use work.electricalsystem.all; + +ENTITY test IS + PORT (TERMINAL p: electrical); +END ENTITY test; + +ARCHITECTURE sine OF test IS + constant ampl: REAL:=5.0; + constant freq: real:=10000.0; + QUANTITY v ACROSS i THROUGH p; + quantity vr across ir through p; +BEGIN +e1: v == ampl * sin(2.0 * 3.14159 * freq * real(time'pos(now))*1.0e-12); +e2: vr== ir*10.0; +END ARCHITECTURE sine; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test141.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test141.ams new file mode 100644 index 000000000..5303951b9 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test141.ams @@ -0,0 +1,75 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test141.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test141.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +-- this is the behavioral model of a simple error amplifier. +-- the entity consists of a quatity port and the architecture consists +-- of a simple simultaneos statement +---------------------------------------------------------------------- +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +-- subtype voltage is real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity ErrorAmplifier is + generic( Gain : REAL := 10.0 -- amplifier gain + ); + port( terminal P_T,N_T: electrical; -- analog input pins + quantity Vout : out real -- analog output + ); +end entity ErrorAmplifier; + +architecture Behavior of ErrorAmplifier is + +quantity DeltaV across P_T through N_T; -- differential input voltage +begin +e1: DeltaV== 1.0* sin(2.0 * 3.141592 *10000.0 * real(time'pos(now))*1.0e-12); +e2: Vout == Gain*DeltaV; + +end architecture Behavior; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test143.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test143.ams new file mode 100644 index 000000000..f83c97aa3 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test143.ams @@ -0,0 +1,83 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test143.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +------------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +------------------------------------------------------------------------- +-- File : test143.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +------------------------------------------------------------------------ +-- Description : +------------------------------------------------------------------------ +-- the test checks for the correctness of the concurrent signal +-- assignment. it accepts sine wave as input and the architecture has a +-- concurrent signal assignment statement that assigns either a 1 or 0 +-- depending on the condition. +------------------------------------------------------------------------ + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + subtype voltage is real; + subtype current is real; + +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity AnaComparator is + generic( Vth: voltage := 0.0 -- [V] comparator threshold level + ); + port( terminal P_T: electrical; + signal Out_T: out BIT + ); +end entity AnaComparator; + +architecture Behavior of AnaComparator is + quantity DeltaV across P_T to electrical'reference; -- differential input voltage + +begin + +e1: DeltaV== 5.0*sin(2.0*3.14159*10000.0*real(time'pos(now))*1.0e-15); + + out_T <= '1' when DeltaV'above(0.0) -- trigger event when V+>V- + else '0' when not DeltaV'above(0.0); -- trigger event when V+<=Vt- + +end architecture Behavior; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test144.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test144.ams new file mode 100644 index 000000000..7fe6c01b8 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test144.ams @@ -0,0 +1,130 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test144.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +------------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +------------------------------------------------------------------------- +-- File : test144.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------------- +-- Description : +----------------------------------------------------------------------------- +-- the test checks for the correctness of the ATTRIBUTE declaration +-- also checks function, real_vector and quantity vector declarations +-- the integer range<> is used instead of specifying the actaul range +-- or size of the matrix. +-- 1 D and 2 D matrix operations are verified. +-- the test performs the matrix dot product caluculation and also +-- product of a 2 D matrix with a column vector. +---------------------------------------------------------------------- + +PACKAGE electrical_system IS + + -- declare attribute to hold units + ATTRIBUTE unit : string; + NATURE electrical IS + real ACROSS + real THROUGH; + NATURE electrical_vector IS ARRAY(integer range<>) OF electrical; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + NATURE real_vector IS ARRAY(integer range<>) of real; +END PACKAGE electrical_system; + +PACKAGE real_aux IS + TYPE real_vector IS ARRAY(integer range<>) OF real; + TYPE real_matrix IS ARRAY(integer range<>, integer range<>) OF real; + + -- scalar := (row_)vector * (column_)vector + + FUNCTION "*"(v1, v2 : real_vector) RETURN real IS + VARIABLE result : real := 0.0; + BEGIN + ASSERT v1'range = v2'range; -- to ensure correct dot product evaluation + FOR i IN v1'range LOOP + result := result + v1(i) * v2(i); + END LOOP; + RETURN result; + END FUNCTION "*"; + + -- (column_)vector := matrix * (column_)vector + + FUNCTION "*"(m : real_matrix; v : real_vector) RETURN real_vector IS + VARIABLE result : real_vector(m'range(1)); + BEGIN + ASSERT m'range(2) = v'range; + FOR i IN result'range LOOP + result(i) = 0.0; + FOR j IN v'range LOOP + result(i) := result(i) + m(i,j) * v(j); + END LOOP; + END LOOP; + RETURN result; + END FUNCTION "*"; +END PACKAGE real_aux; + +use work.electrical_system.all; +-- ideal multiplier + +ENTITY mult IS + PORT (TERMINAL in1, in2, output, ref : electrical); +END ENTITY mult; + +ARCHITECTURE ideal OF mult IS + QUANTITY vout ACROSS iout THROUGH output TO ref; + QUANTITY vin1 ACROSS in1 TO ref; + QUANTITY vin2 ACROSS in2 TO ref; +BEGIN + vout == vin1 * vin2; +END ARCHITECTURE ideal; + +USE work.electrical_system.all; +USE work.real_aux.all; + +ENTITY xfrm IS + GENERIC (ml : real_matrix); -- self/mutual inductances + PORT (TERMINAL p, m : electrical_vector); +END ENTITY xfrm; + +ARCHITECTURE one OF xfrm IS + QUANTITY v ACROSS i THROUGH p TO m; -- arrays! +BEGIN + v == ml*real_vector(i'dot); +END ARCHITECTURE one; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test145.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test145.ams new file mode 100644 index 000000000..c27c40f5b --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test145.ams @@ -0,0 +1,359 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test145.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test145.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : June 2001 +---------------------------------------------------------------------- +-- Description : +-- this is a mos model. It tests for the correctness of the procedural +-- statement. +-- +-- the model accepts the mos data as generic constants. The terminals +-- are defined as of nature electrical. +-- it also tests the alias declaration for real'low. +-- Charges associated with the 4 terminals are declared as quantities. +-- The voltage associated with each of them is also defined. +-- a signal is used to drive i.e to carry out a generic initialization. +-- The various mos equations are evaluated depending on the conditions. +-- The equations for charges and currents are evaluated. +---------------------------------------------------------------------- + +package mosdata is + NATURE electrical is real across real through; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; + alias undefined is real'low; + constant Temperature: real:=27.0; + constant eps0 : real :=8.85418e-12; + constant Ni : real :=1.45e16; + constant Boltzmann : real :=1.380662e-23; + constant echarge: real :=1.6021892e-19; + constant epsSiO2 : real :=3.9*eps0; + constant epsSi : real :=11.7*eps0; + constant kTQ : real :=Boltzmann*temperature/echarge; + constant pi: real := 3.14159; +end package mosdata; + +use work.mosdata.all; +entity mos is + + generic( + width : real:=1.0E-4; + length : real:=1.0E-4; + channel: real :=1.0; + kp :real:= 2.0E-5; + gamma :undefined; + phi :undefined; + tox :real:= 1.0E-7; + nsub :real:= 0.0; + nss :real:=0.0; + nfs :real:= 0.0; + tpg :real:= 1.0; + xj :real:=0.0; + ld :real:= 0.0; + u0 :real:= 600.0; + vmax :real:=0.0; + xqc :real:= 1.0; + kf :real:=0.0; + af :real:=1.0; + fc :real:=0.5; + delta :real:=0.0; + theta :real:=0.0; + eta :real:=0.0; + Sigma :real:=0.0; + kappa :real:=0.2 ); + + port ( terminal drain, gate, source, bulk : electrical); + +end entity mos; + +architecture amos of mos is + quantity Qc, Qb, Qg: real; + quantity Qcq, Qbq, Qgq : real; -- channel, bulk and gate charges + quantity Vdsq across drain to source; + quantity Vgsq across gate to source; + quantity Vbsq across bulk to source; + quantity Idq through drain; + quantity Igq through gate; + quantity Isq through source; + quantity Ibq through bulk; + + signal Initialized: boolean; -- use a signal as generic initialisation + +begin + MOSeqns: procedural is + variable + cox,vt,beta,sigma,nsub,Phi,Gamma,nss,ngate,A,B,C,D,Vfb,fshort, + wp,wc,sqwpxj,vbulk,delv,vth,Vgstos, Vgst, + Ueff,Tau,Vsat,Vpp,fdrain, + stfct,leff,xd,qnfscox,fn,dcrit,deltal,It,Ids,R,Vds,Vgs,Vbs, + forward ,egfet,fermig, mobdeg: real; + begin -- procedural statements + + if not Initialized then + if tox<=0.0 then + cox:=epsSiO2/1.0e-7; + else + cox:=epsSiO2/tox; + end if; + + if kp = 0.0 then + beta:=cox*u0; + else + beta:=kp; + end if; + + nsub := nsub * 1.0e6; -- scale nsub to SI units + + if (phi = undefined) then + if (nsub > 0.0) then + if (0.1<2.0*KTQ*(nsub/Ni)) then + Phi:=(2.0*kTQ*(nsub/Ni)); + else + Phi:=0.1; + end if; + else + Phi:=0.6; + end if; + else + Phi:=phi; + end if; + + if (gamma = undefined) then + if (nsub > 0.0) then + Gamma:=sqrt(2.0*epsSi*echarge*nsub)/cox; + else + Gamma:=0.0; + end if; + else + Gamma:=gamma; + end if; + + nss:=nss*1.0e4; -- Scale to SI + ngate:=gamma*1.0e4; -- Scale to SI + + leff:=length-2.0*ld; + if leff>0.0 then + Sigma:= eta * 8.15e-22/(cox*leff*leff*leff); + else + Sigma:=0.0; + end if; + + if nsub>0.0 then -- N.B. nsub was scaled, above. + xd:=sqrt(2.0*epsSi/(echarge*nsub)); + else + xd:=0.0; + end if; + + if (nfs>0.0) and(cox>0.0) then + qnfscox:=echarge*nfs/cox; + else + qnfscox:=0.0; + end if; + + if cox>0.0 then + fn:=delta*pi*epsSi*0.5/(cox*width); + else + fn:=delta*pi*epsSi*0.5*tox/epsSiO2; + end if; + + --Scale beta and convert cox from Fm^-2 to F + beta:=beta*width/leff; + cox:=cox*width*leff; + + Initialized <= true; + end if; -- not initialized + + Vds:=channel*Vdsq; + if Vds>=0.0 then + Vgs:=channel* Vgsq; + Vbs:=channel* Vbsq; + forward:=1.0; + else + Vds:=-Vds; + Vgs:=channel* Vgsq; + Vbs:=channel* Vbsq; + forward:=-1.0; + end if; + + if Vbs<=0.0 then + A:=Phi-Vbs; + D:=sqrt(A); + else + D:=2.0*sqrt(Phi)*Phi/(2.0*Phi+Vbs); + A:=D*D; + end if; + + Vfb:=Vt-Gamma*sqrt(Phi)-Sigma*Vds; + if (xd=0.0) OR (xj=0.0) then + fshort:=1.0; + else + wp:=xd*D; + wc:=0.0631353*xj+0.8013292*wp-0.01110777*wp*wp/xj; + sqwpxj:=sqrt(1.0-(wp*wp/((wp+xj)*(wp+xj)))); + fshort:=1.0-((ld+wc)*sqwpxj-ld)/leff; + end if; + + vbulk:=Gamma*fshort*D+fn*A; + if nfs=0.0 then + delv:=0.0; + else + delv:=kTQ*(1.0+qnfscox+vbulk*0.5/A); + end if; + + vth:=Vfb+vbulk; + Vgstos:=Vgs-Vfb; + + if (vgs-vth > delv) then + Vgst:=Vgs-vth; + else + Vgst:= delv; + end if; + + if (vgs>=vth) or (delv/=0.0) then + + if (Vbs<=0.0) or (Phi /= 0.0) then + B:=0.5*Gamma/D+fn; + else + B:=fn; + end if; + + mobdeg:=1.0/(1.0+theta*Vgst); + + if (vmax /=0.0) then + Ueff:=u0*mobdeg; + Tau:=Ueff/Leff*vmax; + else + Tau:=0.0; + end if; + + Vsat:=Vgst/(1.0+B); + Vsat:=Vsat*(1.0-0.5*Tau*Vsat); -- not quite the same as SPICE + if (vds<Vsat) then + Vpp:=vds; + else + Vpp:= Vsat; + end if; + + fdrain:=1.0/(1.0+Tau*Vpp); + if (Vgs<vth+delv) and (nfs>0.0) then + stfct:=exp((Vgs-vth-delv)/delv); + else + stfct:=1.0; + end if; + + if Vds>=Vsat then + if (kappa>0.0) and (xd>0.0) then + + if vmax=0.0 then + deltal:=sqrt(kappa*xd*xd*(Vds-Vsat)); + else + dcrit:=(xd*xd*vmax*0.5)/(Ueff*(1.0-fdrain)); + + deltal:=sqrt(kappa*xd*xd*(Vds-Vsat)+dcrit*dcrit)-dcrit; + end if; + + if deltal<=0.5*Leff then + C:=Leff/(Leff-deltal); + else + C:=4.0*deltal/Leff; + end if; + + else + C:=1.0; + end if; + + else + C:=1.0; + end if; + + It:=Vgst-Vpp*(1.0+B)*0.5; + Beta:=Beta*mobdeg; + Ids:=Beta*Vpp*It*C*fdrain*stfct; + else + -- Cutoff + Ids:=0.0; + end if; -- vgs >= vth + + if Cox /= 0.0 then + --Charges + if Vgs<=vth then + if Gamma /= 0.0 then + if Vgstos < -A then + Qg:=Cox*(Vgstos+A); -- Accumulation + else + Qg:=0.5*Gamma*Cox*(sqrt(4.0*(Vgstos+A)+Gamma*Gamma-Gamma)); + end if ; -- vgstos <-A + else-- Gamma = 0.0 + Qg:=0.0; + end if; -- gamma /= 0 + Qb:=-Qg; + Qc:=0.0; + else + -- depletion mode: + R:=(1.0+B)*Vpp*Vpp/(12.0*It); + Qg:=Cox*(Vgstos-Vpp*0.5+R); + Qc:=-Cox*(Vgst+(1.0+B)*(R-Vpp*0.5)); + Qb:=-(Qc+Qg); + end if; + + else + Qg:=0.0; + Qc:=0.0; + Qb:=0.0; + end if; -- cox /= 0 + + -- equations for charges (in a procedural we have assignments to + --quantitites): + Qcq := Qc; + Qgq := Qg; + Qbq := Qb; + + -- equations for currents: + Idq := channel*forward*Ids+channel*xqc*Qc'dot; + Igq := channel*Qg'dot; + Ibq := channel*Qb'dot; + Isq := -Idq - Igq - Ibq; + + end procedural; +end architecture amos; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test146.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test146.ams new file mode 100644 index 000000000..03319068f --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test146.ams @@ -0,0 +1,109 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test146.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test100.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- half wave Rectifier model ... +-- the test is done for checking the correct implementation +--of the simultaneous if statement.it checks +--nature declaration, terminal and quantity declarations. + + +---------------------------------------------------------------------- +-- T1 diode D T2 +-- o-----|>|-----o-------o The circuit comprises: +-- | | i) A diode . +-- ( ) >R=100ohms ii) A sinusoidal voltage source. +-- |Vs = 5sinwt > iii)A resistor R. +-- | > +-- |_____________|_______o +-- |gnd +-- ----- +---------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH; + FUNCTION SIN (X : real ) RETURN real; + FUNCTION EXP (X : real ) RETURN real; +END PACKAGE electricalSystem; + +---------------------------------------------------------------------- + +USE work.electricalSystem.all; + +ENTITY hwr IS +END hwr; + +ARCHITECTURE ahwr OF hwr IS + + terminal T1, T2 : electrical; + quantity VDiode across IDiode through T1 to T2; + quantity V2 across I2 through T2 to electrical'reference; + quantity VS across T1 to electrical'reference; + + CONSTANT saturation_current : real := 0.0000000000001; + CONSTANT Vt : real := 0.025; + + CONSTANT BV : real := 100.0; + CONSTANT neg_sat : real := -saturation_current; + +BEGIN + + --diode equations + if( vDiode >= (-1.0 * Vt)) USE + eq1: iDiode == saturation_current; + + ELSIF ((vDiode < (-3.0 * Vt)) AND (vDiode > -BV)) use + eq2: iDiode == neg_sat; + + ELSE + eq3: iDiode == neg_sat; + END USE ; + + eqn2: v2 == 100.0 * i2; + + eqn4: vs == 5.0 * sin(2.0 * 3.14 * 100000.0 * + real(time'pos(now)) * 1.0e-15 ); + +END ahwr ; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test147.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test147.ams new file mode 100644 index 000000000..59574f436 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test147.ams @@ -0,0 +1,75 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test147.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test147.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- this checks for the corect implementation of the 'dot'dot and negation +-- operator implementation for simple simulataeous statements +---------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity V1 across I1 through T1 to T2; +quantity V2: real; +quantity V3: real; +quantity VS across Isource through T1; + +begin + +e1: I1 == V1'dot*1e-15; +e2: V2 == VS'dot'dot; +e3: V3 == -VS'dot; +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test148.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test148.ams new file mode 100644 index 000000000..4445de2be --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test148.ams @@ -0,0 +1,77 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test148.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test148.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test checks for the correctness of the quantity, terminal, nature +-- and package declarations. the terminals are assigned as terminals. +-- a simple V-R circuit is considered. +----------------------------------------------------------------------- + +PACKAGE electricalsystem IS + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +-- SUBTYPE voltage IS real; +-- SUBTYPE current IS real; + +NATURE electrical IS real ACROSS real THROUGH ground reference; + +END PACKAGE electricalsystem; +use work.electricalsystem.all; + +ENTITY test IS + generic(ampl:real:=5.0); + PORT (TERMINAL p: electrical); +END ENTITY test; + +ARCHITECTURE sine OF test IS + constant freq: real:=10000.0; + QUANTITY v ACROSS i THROUGH p; + quantity vr across ir through p; +BEGIN +e1: v == ampl * sin(2.0 * 3.14159 * freq * real(time'pos(now))*1.0e-12); +e2: vr== ir*10.0; +END ARCHITECTURE sine; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test149.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test149.ams new file mode 100644 index 000000000..befafb72e --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test149.ams @@ -0,0 +1,113 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test149.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test149.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple resistor model... +-- the test is done for checking the correct implementation of the +-- componet declaration. The model consists of 2 resistor models which are +-- instantiated. + +package electricalSystem is + NATURE electrical IS real ACROSS real THROUGH Ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalsystem.all; + +entity test1 is + port (terminal P, N : electrical ); +end entity test1; + +architecture behav of test1 is + quantity Vt1 across It1 through P to N; +begin + res1 : Vt1 == It1 * 10.0 ; +end architecture behav; + +use work.electricalsystem.all; +entity test2 is + port (terminal P, N : electrical ); +end test2; + +architecture behav of test2 is + quantity Vt2 across It2 through P to N; +begin + res1 : Vt2 == It2 * 100.0 ; +end behav; + + +use work.electricalsystem.all; + +entity resistor_ckt is +end resistor_ckt; + +architecture ares_ckt of resistor_ckt is + + component test1 is + port (terminal P, N : electrical ); + end component; + + component test2 is + port (terminal P, N : electrical ); + end component; + + for all : test1 use entity work.test1(behav); + for all : test2 use entity work.test2(behav); + + terminal a,b,c,t1,t2 : electrical; + quantity vout across iout through t2 to electrical'reference; + quantity vs across a to electrical'reference; + +begin + e1 : test1 port map (P => a, N => b); + e2 : test2 port map (P => b, N => c); + e3 : vout == iout * 1200.0; + e4 : test1 port map (P => c, N => t1); + e5 : test1 port map (P => t1, N => t2); + source : vs == 5.0 * sin(2.0 * 3.1415 * 10000.0* real(time'pos(now)) * 1.0e-12); +end architecture ares_ckt; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test150.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test150.ams new file mode 100644 index 000000000..d159873e0 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test150.ams @@ -0,0 +1,75 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test150.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test150.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple RC model... +-- the test is done for checking the correct implementation +-- of the simple simultaneous equation statement with 'dot expression on +-- RHS. it checks nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity V1 across I1 through T1 to T2; +quantity V2 across I2 through T2; +quantity VS across T1; + +begin + +e1: V1 == I1*10.0; +e2: I2 == 1.0e-12*V2'dot; + +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test151.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test151.ams new file mode 100644 index 000000000..647d8eb53 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test151.ams @@ -0,0 +1,76 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test151.ams,v 1.1 2002-03-27 22:11:18 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test151.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple resistor model...2 resistors in parallel +-- the test is done for checking the correct implementation +-- of the simple simultaneous equation statement with multiple expressions +-- RHS. It checks nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1:electrical; +quantity V1 across I1 through T1 to electrical'reference; +quantity V2 across I2 through T1 to electrical'reference; +quantity VS across T1; +quantity I12 : real; +begin + +e1: V1 == I1*10.0; +e2: V2 == I2*10.0; +e3: I12 == I1+I2; + +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test152.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test152.ams new file mode 100644 index 000000000..a3a5fd9f1 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test152.ams @@ -0,0 +1,75 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test152.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test150.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple RC model... +-- the test is done for checking the correct implementation of the simple +-- simultaneous equation statement with 'dot expression on RHS. it checks +-- nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity V1 across I1 through T1 to T2; +quantity V2 across I2 through T2; +quantity VS across T1; + +begin + +e1: V1 == I1*10.0; +e2: I2 == V2'dot*1.0e-12; + +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test153.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test153.ams new file mode 100644 index 000000000..091e91fde --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test153.ams @@ -0,0 +1,79 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test153.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test100.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple model which has a voltage source. +-- The output voltage Vout is dependent on the value of vS at that point +-- of time. If the voltage is below Vref, the output is a 1 else output is +-- a 0. the test is done for checking the correct implementation of the +-- simple simultaneous if statement.it checks nature declaration, terminal +-- and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity VS across T1; +quantity Vout: real; +constant Vref:real:=5.0; +begin + +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +if (VS <= Vref) use +e1: Vout == 1.0; +else +e2: Vout == 0.0; +end use; + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test154.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test154.ams new file mode 100644 index 000000000..eb87aee45 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test154.ams @@ -0,0 +1,79 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test154.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test154.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple model which has a voltage source. +-- The output voltage Vout is dependent on the value of VS wrt Vref +-- If the voltage is below Vref, the output is a 0 else output is a 1. +-- the test is done for checking the correct implementation +--of the simple simultaneous if statement.it checks +--nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity VS across T1; +quantity Vout: real; +constant Vref:real:=5.0; +begin + +esource: VS == 5.0; + +if (VS<=Vref) use +e1: Vout == 1.0; +else +e2: Vout == 0.0; +end use; + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test155.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test155.ams new file mode 100644 index 000000000..56e0adfd7 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test155.ams @@ -0,0 +1,81 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test155.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test155.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple model which has a voltage source. +-- The output voltage Vout is dependent on the value of VS wrt Vref +-- If the voltage is above/below Vref, the output is a 0 else output is a 1. +-- the test is done for checking the correct implementation +-- of the simple simultaneous if statement with multiple if conditions.it +-- checks nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity VS across T1; +quantity Vout: real; +constant Vref:real:=5.0; +begin + +esource: VS == 5.0; + +if (VS<Vref) use +e1: Vout == 0.0; +elsif (VS=Vref) use +e2: Vout == 1.0; +else +e3: Vout == 0.0; +end use; + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test156.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test156.ams new file mode 100644 index 000000000..8837429f1 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test156.ams @@ -0,0 +1,108 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test156.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +-- check the implemetatio of ports and generics. + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity inv is + port ( + x : in bit; + xout : out bit); +end inv; + +architecture inverter of inv is +begin + + xout <= not x after 100ns ; + +end inverter ; + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND reference; + FUNCTION SIN (X : real ) RETURN real; + FUNCTION EXP (X : real ) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; + +entity resistor is + generic ( res : real := 10.0 ) ; + port (terminal P, N : electrical ); +end resistor; + +architecture behav of resistor is + quantity VPTON across IPTON through P to N; +begin + res1 : VPTON == IPTON * res ; +end behav; + +use work.electricalSystem.all; + +ENTITY circuit1 IS +END circuit1; + +ARCHITECTURE behavior OF circuit1 IS + component inv is + port ( + x : in bit; + xout : out bit); + end component ; + for all : inv use entity work.inv(inverter) ; + + component resistor is + generic ( res : real := 10.0 ) ; + port (terminal P, N : electrical ); + end component; + for all : resistor use entity work.resistor(behav); + + terminal n1,n2 : electrical; + QUANTITY vIn ACROSS iIn THROUGH n1 ; + + signal y:bit:='0'; + +BEGIN + + D2 : inv port map(x=>y, xout=>y); + + testbench:PROCESS + BEGIN + WAIT ON y; + END PROCESS; + + R1 : resistor generic map ( res => 500.0) port map (P => n1, N => n2); + R2 : resistor port map (P => n2, N => ground); + vsource: vIn == 5.0 * sin(2.0 * 3.14 * 100000.0 * real(time'pos(now)) * 1.0e-15); + +END ARCHITECTURE behavior; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test157.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test157.ams new file mode 100644 index 000000000..d73dadb62 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test157.ams @@ -0,0 +1,108 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test157.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +-- check the implemetatio of ports and generics. + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +--entity inv is +-- port ( +-- x : in bit; +-- xout : out bit); +--end inv; + +--architecture inverter of inv is +--begin + +-- xout <= not x after 100ns ; + +--end inverter ; + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND reference; + FUNCTION SIN (X : real ) RETURN real; + FUNCTION EXP (X : real ) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; + +entity resistor is + generic ( res : real := 10.0 ) ; + port (terminal P, N : electrical ); +end resistor; + +architecture behav of resistor is + quantity VPTON across IPTON through P to N; +begin + res1 : VPTON == IPTON * res ; +end behav; + +use work.electricalSystem.all; + +ENTITY circuit1 IS +END circuit1; + +ARCHITECTURE behavior OF circuit1 IS +-- component inv is +-- port ( +-- x : in bit; +-- xout : out bit); +-- end component ; +-- for all : inv use entity work.inv(inverter) ; + + component resistor is + generic ( res : real := 10.0 ) ; + port (terminal P, N : electrical ); + end component; + for all : resistor use entity work.resistor(behav); + + terminal n1,n2 : electrical; + QUANTITY vIn ACROSS iIn THROUGH n1 ; + +-- signal y:bit:='0'; + +BEGIN + +-- D2 : inv port map(x=>y, xout=>y); + +-- testbench:PROCESS +-- BEGIN +-- WAIT ON y; +-- END PROCESS; + + R1 : resistor generic map ( res => 500.0) port map (P => n1, N => n2); + R2 : resistor port map (P => n2, N => ground); + vsource: vIn == 5.0 * sin(2.0 * 3.14 * 100000.0 * real(time'pos(now)) * 1.0e-15); + +END ARCHITECTURE behavior; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test158.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test158.ams new file mode 100644 index 000000000..0f80dc695 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test158.ams @@ -0,0 +1,98 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test158.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test134.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : June 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- this is a test to check the corretness of the implemntation of the break +-- statement and also the use of quantity port of type voltage. +-- this is a vco model which first sets the initial condition +-- using a break statement. Then again, a break statement is applied to keep +-- the phase within 0-2pi. Thr output voltage eqn is obtained as vout and the +-- phase eqn as phase'dot. +-- LRM ref: 8.14, 4.3.2. +---------------------------------------------------------------------- +PACKAGE electricalSystem IS + -- SUBTYPE voltage is real; + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; + FUNCTION SQRT(X : real) RETURN real; + FUNCTION POW(X,Y : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; + +entity vco is + generic( + fc: real := 1.0e6; -- VCO frequency at Vc + df: real := 0.5e6; -- [Hz/V], frequency characteristic slope + Vc: voltage := 0.0 -- centre frequency input voltage + ); + port( quantity Vin: in real; + terminal OutTerminal: electrical); +end entity VCO; + +architecture avco of vco is + constant TwoPi: real := 6.283118530718; -- 2pi + + quantity Phase : real; + + -- define a branch for the output voltage source + + quantity Vout across Iout through OutTerminal to electrical'reference; + +begin + -- use break to set the phase initial condition + break Phase => 0.0; + + -- another break statement keeps the phase within 0.. 2pi + break Phase => Phase mod TwoPi on Phase'above(TwoPi); + + -- phase equation + Phase'dot == TwoPi*realmax(0.5E6, fc+(Vin-Vc)*df); + + -- output voltage source equation + Vout == 2.5*(1.0+sin(Phase)); + +end architecture avco; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test161.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test161.ams new file mode 100644 index 000000000..f63c3803a --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test161.ams @@ -0,0 +1,75 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test161.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test150.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple RC model... +-- the test is done for checking the correct implementation +-- of the simple simultaneous equation statement with 'dot expression on +-- RHS. it checks nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity V1 across I1 through T1 to T2; +quantity V2 across I2 through T2; +quantity VS across T1; + +begin + +e1: V1 == I1*10.0; +e2: V2 == I1'integ/1.0e-12; + +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test162.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test162.ams new file mode 100644 index 000000000..dbc7b3bac --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test162.ams @@ -0,0 +1,74 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test162.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test147.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- this checks for the corect implementation of the 'dot'dot and negation +-- operator implementation for simple simulataeous statements +---------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity V1 across I1 through T1 to T2; +quantity V2: real; +quantity i2 :real; +quantity VS across Isource through T1; + +begin + +e1: I1 == V1'dot*1.0e-15; +e2: V2 == V1'dot; +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test163.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test163.ams new file mode 100644 index 000000000..3b26a8aac --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test163.ams @@ -0,0 +1,81 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test163.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test162.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple rc model...with 2 res in parallel connected thru a capacitor +-- -------------||----- +-- | | +-- | R | R +-- -------------------- +-- the test is done for checking the correct implementation +--of the simple simultaneous equation statement.it checks +--nature declaration, terminal, 'dot and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity VR1 across IR1 through T1; +quantity VC across IC through T1 to T2; +quantity VR2 across IR2 through T2; +quantity VS across T1; + +begin + +e1: VR1 == IR1*100.0; +e2: IC == VC'dot *1.0e-12; +e3: VR2 == IR2*10.0; + +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test164.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test164.ams new file mode 100644 index 000000000..17a077817 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test164.ams @@ -0,0 +1,81 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test164.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test164.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple rc model...with 2 res in parallel connected thru a capacitor +-- -------------||----- +-- | | +-- | R | R +-- -------------------- +-- the test is done for checking the correct implementation +-- of the simple simultaneous equation statement.it checks +-- nature declaration, terminal, 'dot, 'integ and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity VR1 across IR1 through T1; +quantity VC across IC through T1 to T2; +quantity VR2 across IR2 through T2; +quantity VS across T1; + +begin + +e1: VR1 == IR1*100.0; +e2: IC == VC'dot *1.0e-12; +e3: VR2 == IR2*10.0; +e4: VC == IC'integ/1.0e15 +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test165.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test165.ams new file mode 100644 index 000000000..cf085096d --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test165.ams @@ -0,0 +1,80 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test165.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test164.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple rl model... +-- -----^^^------------- +-- R | > +-- | L > R +-- -------------------- +-- the test is done for checking the correct implementation +-- of the simple simultaneous equation statement.it checks +-- nature declaration, terminal, 'dot, and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity VR1 across IR1 through T1 to T2; +quantity VL across IL through T2; +quantity VR2 across IR2 through T2; +quantity VS across T1; + +begin + +e1: VR1 == IR1*10.0; +e2: VL == IL'dot *1.0; +e3: VR2 == IR2*10.0; +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test166.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test166.ams new file mode 100644 index 000000000..92dc6af26 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test166.ams @@ -0,0 +1,80 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test166.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test166.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple rl model... +-- -----^^^------------- +-- R | > +-- | L > R +-- -------------------- +-- the test is done for checking the correct implementation +-- of the simple simultaneous equation statement.it checks +-- nature declaration, terminal, 'dot,'integ and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity VR1 across IR1 through T1 to T2; +quantity VL across IL through T2; +quantity VR2 across IR2 through T2; +quantity VS across T1; + +begin + +e1: VR1 == IR1*10.0; +e2: VL == IL'dot *1.0; +e3: VR2 == IR2*10.0; +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); +e4: IL== 1.0* VL'integ; +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test167.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test167.ams new file mode 100644 index 000000000..35849f231 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test167.ams @@ -0,0 +1,81 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test167.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test167.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- An RC model... +-- the test is done for checking the correct implementation +-- of the simple simultaneous equation statement.it checks +-- nature declaration, terminal, 'dot, 'integ and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2, T3, T4:electrical; +quantity V1 across I1 through T1 to T2; +quantity V2 across I2 through T2 to T3; +quantity VC across IC through T3; +quantity VC1 across IC1 through T2 to T4; +quantity V3 across I3 through T4; +quantity VS across T1; + +begin + +e1: V1 == I1*1.0; +e2: V2 == I2*1.0; +e3: V3 == I3*10.0; +e4: IC == VC'dot*1.0e-12; +e5: IC1 == VC1'dot*1.0e-12; + +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test168.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test168.ams new file mode 100644 index 000000000..c78d544b6 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test168.ams @@ -0,0 +1,81 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test168.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test168.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- An RC model... +-- the test is done for checking the correct implementation +-- of the simple simultaneous equation statement.it checks +-- nature declaration, terminal, 'dot, 'integ and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2, T3, T4:electrical; +quantity V1 across I1 through T1 to T2; +quantity V2 across I2 through T2 to T3; +quantity VC across IC through T3; +quantity VC1 across IC1 through T2 to T4; +quantity V3 across I3 through T4; +quantity VS across T1; + +begin + +e1: V1 == I1*1.0; +e2: V2 == I2*1.0; +e3: V3 == I3*10.0; +e4: VC == IC'integ*1.0e12; +e5: VC1 == IC1'integ*1.0e12; + +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test169.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test169.ams new file mode 100644 index 000000000..c0b15e18f --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test169.ams @@ -0,0 +1,143 @@ + +-- Copyright (C) 1999-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test169.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +-------------------------------------------------------------------- +-- Ebers-moll Model for a transistor -- +-- VHDL-AMS Implementation -- +-- Developed at the Distributed Processing Lab at the University -- +-- of Cincinnati -- +-- by VishwaShanth Kasula on May 10, 1999 -- +-------------------------------------------------------------------- +-- Circuit Topology -- +-- BJT Ebers-Moll static model +-- Testbench Ckt to evaluate the DC operatioing point of an npn BJT, +-- Sedra smith page no. 152, fig 4.9 +-------------------------------------------------------------------- + +-- Three regions are simulated +-- Active region, vbb = 4.0 V +-- Saturation region, vbb = 6.0 V +-- Cutoff region, vbb = 0.0; + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground reference; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalsystem.all; + +entity bjt_npn is + generic(isat : real := 1.0e-16; -- Saturation Current + bf : real := 100.0; -- Ideal maximus forward current + br : real := 1.0; -- ideal maximum reverse current + rb : real := 1.0e-5; -- Base resistance + rc : real := 1.0e-5; -- collector resistance + re : real := 1.0e-5; -- emmiter resistance + vaf : real := 100.0); -- Forward Early Voltage + port(terminal e,b,c : electrical); +end bjt_npn; + +architecture structure of bjt_npn is + terminal b1, c1, e1 : electrical; + quantity vbo across ib through b to b1; + quantity vco across ic through c to c1; + quantity veo across ie through e to e1; + quantity vct across Ict through c1 to e1;--current source + quantity vbe across ibe through b1 to e1; + quantity vbc across ibc through b1 to c1; + quantity vce : real := 1.0; -- used to calculate VCE + constant gmin : real := 1.0e-12; -- condutsnce in parallel with every pn junction + constant vt : real := 0.02589; -- thermal voltage + +begin + brk : break vbe => 1.0, vbc => -1.0; + + diodecond1 : if(vbe > -5.0*vt) use + diodebef : ibe == ((isat*(exp(vbe/vt) - 1.0)) + (gmin*vbe))/bf; + elsif (vbe <= -5.0*vt ) use + diodeber: ibe == ((-1.0*isat) + (gmin*vbe))/bf; + end use; + diodecond2 : if(vbc > -5.0*vt) use + diodebcf : ibc == ((isat*(exp(vbc/vt) - 1.0)) + (gmin*vbc))/br; + elsif(vbc <= -5.0*vt) use + diodebcr : ibc == ((-1.0*isat) + (gmin*vbc))/br; + end use; + bres : vbo == ib * 1.0e-6; + cres : vco == ic * 1.0e-6; + eres : veo == ie * 1.0e-6; + kcl_eqn : ie == -1.0*(ib + ic); + vcevolt : vce == vbe - vbc; + ictdep : Ict == ((Ibe*bf) - (Ibc*br)) * (1.0 -(vbc/vaf)); + +end architecture structure; + + +--***************************************************** +--TEST BENCH +use std.textio.all; +use work.electricalsystem.all; + +entity bjt_testbench is +end bjt_testbench; + +architecture structure of bjt_testbench is + terminal t1, t2, t3, t4 : electrical ; + component bjt_npn_comp + generic(isat : real := 1.0e-16; -- Saturation Current + bf : real := 100.0; -- Ideal maximus forward current + br : real := 1.0; -- ideal maximum reverse current + rb : real := 1.0e-5; -- Base resistance + rc : real := 1.0e-5; -- collector resistance + re : real := 1.0e-5; -- emmiter resistance + vaf : real := 100.0); -- Forward Early Voltage + port(terminal e,b,c : electrical); + end component; + for all : bjt_npn_comp use entity work.bjt_npn(structure); + + quantity vcc across icc through t1 to electrical'reference; + quantity vrc across irc through t1 to t2; + quantity vbb across ibb through t3 to electrical'reference; + quantity vre across ire through t4 to electrical'reference; + +begin + + bjt : bjt_npn_comp + generic map (isat => 1.8104e-15, vaf => 100.0) + port map(t4,t3,t2); + emres : vre == ire * 3.3e3; + ccurr : vcc == 10.0; + ecurr : vbb == 6.0; + cores : vrc == irc * 4.7e3; + +end architecture structure; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test170.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test170.ams new file mode 100644 index 000000000..dff75159a --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test170.ams @@ -0,0 +1,86 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test170.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test106.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple resistor model... +-- the test is done for checking the correct implementation +-- of the simple simultaneous equation statement.it checks +-- nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2, T3, T4,T5,T6:electrical; +quantity VRgen across IRgen through T1 to T2; +quantity VLgen across ILgen through T2 to T3; +quantity VRin across IRin through T3; +quantity VR1 across IR1 through T4 to T5; +quantity VR1A across IR1A through T4 to T6; +quantity VC1A across IC1A through T6 to T5; +quantity VC1 across IC1 through T5; +quantity VS across T1; +constant C1: real:=3.5e-3; +constant C1A: real:=0.3e-3; +begin + +e1: VRgen == IRgen*10.0; +e2: VLgen == 0.5*ILgen'dot; +e3: VRin == IRin*500.0; +e4: VR1 == IR1*1.0; +e5: VR1A == IR1A*0.2; +e6: VC1 == C1 /IC1'integ; +e7: VC1A == C1A/IC1A'integ; + +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test171.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test171.ams new file mode 100644 index 000000000..3d0dd76c9 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test171.ams @@ -0,0 +1,96 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test171.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test171.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test is done for checking the correct implementation +-- of the simultaneous if equation statement.it checks +-- nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2, T3 :electrical; +quantity VC1 across IC1 through T1 to T2; +quantity VC2 across IC2 through T3; +quantity VD1 across ID1 through T2; +quantity VD2 across ID2 through T2 to T3; +quantity VS across T1; +constant BV: real:=100.0; +constant satcur: real:=1.0e-12; +constant negsatcur: real:= -1.0*satcur; +constant VT: real:=0.025; +constant C1: real:= 1.0e-12; +constant C2: real:= 1.0e-12; +begin + +e1: IC1 == C1 * VC1'dot; +e2: IC2 == C2*VC2'dot; +diode1: if (VD1>=(-3.0*VT)) use + ID1 == satcur*(exp(VD1/VT)-1.0); + elsif (VD1 < (-3.0*VT) and (VD1 >-BV)) use + ID1==negsatcur; + else + ID1 == negsatcur * (exp(-(BV+ VD1/VT)-1)+satcur); + end use; + +diode2: if (VD2>=(-3.0*VT)) use + ID2 == satcur*(exp(VD2/VT)-1.0); + elsif (VD2 < (-3.0*VT) and (VD2 >-BV)) use + ID2==negsatcur; + else + ID2 == negsatcur * (exp(-(BV+ VD2/VT)-1)+satcur); + end use; + +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test172.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test172.ams new file mode 100644 index 000000000..123b9dd29 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test172.ams @@ -0,0 +1,98 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test172.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test172.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : May 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test is done for checking the correct implementation +-- of the simultaneous if equation statement.it checks +-- nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +port (input: in bit; + output: out bit); +end entity; + +architecture atest of test is +terminal t1, t2: electrical; +quantity v1 across i1 through t1 to t2; +quantity v2 across t2; +begin + +e1: v1== 1.0; +e2: v2==0.0; + + if (v1==1.0) use + output <= '1'; + else + output <='0'; + end use; + + if (v2==2.0) use + output <='0'; + else + output <='1'; + end use; +end architecture atest; +use work.electricalSystem.all; +--entity tb is +--port (tinput: in bit; +-- toutput: out bit); +--end entity; +--architecture atb of tb is +--terminal tt1, tt2: electrical; +--quantity tv1 across ti1 through tt1 to tt2; +--quantity tv2 across tt2; +--begin + +--tv1==1.0; +--tv2==0.0; + +--end architecture atb; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test173.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test173.ams new file mode 100644 index 000000000..c43afe846 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test173.ams @@ -0,0 +1,77 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test173.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test173.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test is done for checking the correct implementation +-- of the simultaneous if equation statement.it checks +-- nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal t1, t2: electrical; +quantity v1 across i1 through t1 to t2; +quantity v2 across t2; + +begin +e1: v1== 1.0; +e2: v2==0.0; + + if (v1==1.0) use + output <= '1'; + end use; + + if (v2==2.0) use + output <='1'; + end use; +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test174.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test174.ams new file mode 100644 index 000000000..4bf8c01ba --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test174.ams @@ -0,0 +1,89 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test174.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test174.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple resistor model... +-- the test is done for checking the correct implementation +-- of the simultaneous case statement.it checks +-- nature declaration, terminal and quantity declarations + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH Ground reference ; + FUNCTION SIN (X : real ) RETURN real; + FUNCTION EXP (X : real ) RETURN real; +END PACKAGE electricalSystem; + + +USE work.electricalSystem.all; + +ENTITY simcase IS +END simcase; + +ARCHITECTURE asimcase OF simcase IS + + terminal T1, T2 : electrical; + + quantity v1 across i1 through T1 ; + quantity v2 across i2 through T1 to T2; + quantity v3 across i3 through T2 ; + +BEGIN + + eqn1 : v1 == 1.0; + +c1: case (v1*2.0) use + + when (2.0) use + v2 == i2 * 100.0; + v3 == i3 * 100.0; + when (6.0) use + v2 == i2 * 200.0; + v3 == i3 * 200.0; + when (10.0) use + v2 == i2 * 300.0; + v3 == i3 * 300.0; + end case c1; + +END asimcase ; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test175.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test175.ams new file mode 100644 index 000000000..544527dc2 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test175.ams @@ -0,0 +1,87 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test175.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test175.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test is done for checking the correct implementation +--of the simultaneous case statement.it checks +--nature declaration, terminal and quantity declarations + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH Ground reference ; + FUNCTION SIN (X : real ) RETURN real; + FUNCTION EXP (X : real ) RETURN real; +END PACKAGE electricalSystem; + +USE work.electricalSystem.all; + +ENTITY simcase IS +END simcase; + +ARCHITECTURE asimcase OF simcase IS + + terminal T1, T2 : electrical; + + quantity v1 across i1 through T1 ; + quantity v2 across i2 through T1 to T2; + quantity v3 across i3 through T2 ; + +BEGIN + + eqn1 : v1 == 1.0; + eqn2 : v2 == 2.0; +c1: case (v1*2.0) use + + when (2.0) use + if (v2==2.0) use + v2 == i2 * 100.0; + else + v2 ==i2*10.0; + end use; + when (6.0) use + v2 == i2 * 200.0; + when (10.0) use + v2 == i2 * 300.0; + end case c1; +END asimcase ; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test176.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test176.ams new file mode 100644 index 000000000..dd7f81126 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test176.ams @@ -0,0 +1,80 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test176.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test176.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test is done for checking the correct implementation +-- of the simultaneous null statement.it checks +-- nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity test is +end entity; + +architecture atest of test is +terminal T1,T2:electrical; +quantity V1 across I1 through T1 to T2; +quantity V2 across I2 through T2; +quantity V3 across I3 through T2; +quantity VS across T1; + +begin + + V1==1.0; + if (V1<=1.0) use + NULL; + else + V2 == V1*1.0; + end use; + + +esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test177.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test177.ams new file mode 100644 index 000000000..75b230ab9 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test177.ams @@ -0,0 +1,82 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test177.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test177.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test is done for checking the correct implementation +-- of the 'path_name attribute. + +--PACKAGE electricalSystem IS +-- NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; +-- FUNCTION SIN (X : real ) RETURN real; +-- FUNCTION EXP (X : real ) RETURN real; +--END PACKAGE electricalSystem; + +--USE work.electricalSystem.all; + +ENTITY Bottom IS +generic(GBottom:integer); +--port (PBottom:integer); +constant SBottom:integer:=4; +END Bottom; + +ARCHITECTURE BottomArch OF Bottom IS +begin + ProcessBottom: process + variable V:integer; + begin + if GBottom=4 then + assert + V'Path_Name= ":top:b1:b2:g1(4):b3:11:processbottom:v"; + -- and GBottom'Path_Name=":top:b1:b2:g1(4):b3:11:gbottom"; + elsif GBottom=1 then + assert + V'Path_Name= ":top:12:processbottom:v"; + else + assert + GBottom'Path_Name="top:12:gbottom"; + end if; + wait; + end process ProcessBottom; +end architecture BottomArch; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test178.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test178.ams new file mode 100644 index 000000000..a3f8ea63a --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test178.ams @@ -0,0 +1,80 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test178.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test178.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test is done for checking the correct implementation +-- of the simultaneous procedural equation statement.it checks +-- nature declaration, terminal and quantity declarations. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN (X : real ) RETURN real; + FUNCTION EXP (X : real ) RETURN real; +END PACKAGE electricalSystem; + + +USE work.electricalSystem.all; + +ENTITY simproc IS +END simproc; + +ARCHITECTURE asimproc OF simproc IS + + terminal T1: electrical; + quantity vd across id through T1; + quantity charge: real; + constant vt: real:= 1.0; +BEGIN + eq1: vd==1.0; + proc1: procedural is + variable vres:real; + constant tau:real:=1.0; + variable ares: real; + begin + e1: ares:=vd*1.0; + e3: vres:=vt; + end procedural; + +END asimproc ; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test179.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test179.ams new file mode 100644 index 000000000..1249b0680 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test179.ams @@ -0,0 +1,86 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test179.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test179.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- A simple resistor model... +-- the test is done for checking the correct implementation +-- 'instance_name attribute + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN (X : real ) RETURN real; + FUNCTION EXP (X : real ) RETURN real; +END PACKAGE electricalSystem; + + +USE work.electricalSystem.all; + +ENTITY Bottom IS +generic(GBottom:integer); +port (PBottom:integer); +constant SBottom:integer:=4; +END Bottom; + +ARCHITECTURE BottomArch OF Bottom IS +begin +-- SBottom :=4; + ProcessBottom: process + variable V:integer; + begin + if GBottom=4 then + assert + V'Instance_Name=":top(top):b1:b2:g1(4):b3:11@bottom(bottomarch):processbottom:v" + and + GBottom'Instance_Name=":top(top):b1:b2:g1(4):b3:11@bottom(bottomarch):gbottom"; + elsif GBottom=1 then + assert + V'Instance_Name=":top(top):12@bottom(bottomarch):processbottom:v"; + else + assert + GBottom'Instance_Name= ":top(top):12@bottom(bottomarch):gbottom"; + end if; + wait; + end process ProcessBottom; +end architecture BottomArch; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test180.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test180.ams new file mode 100644 index 000000000..feae7a692 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test180.ams @@ -0,0 +1,70 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test180.ams,v 1.2 2003-08-05 15:14:24 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test180.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test is done for checking the correct implementation +-- of the break statement.it checks simple break and break on +-- codition. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; +use work.electricalSystem.all; + +entity VCO is +port(terminal InTerminal,OutTerminal: electrical); +end VCO; + +architecture PhaseIntegrator of VCO is + quantity Vin across Iin through InTerminal to OutTerminal; + constant TwoPi: real := 6.283118530718; -- 2pi + quantity Phase : real; -- phase is a free quantity: + quantity Vout across Iout through OutTerminal; +begin + break Phase => TwoPi; + Vout == 2.5*(sin(Phase)); -- output statement +end PhaseIntegrator; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test181.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test181.ams new file mode 100644 index 000000000..873a1f597 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test181.ams @@ -0,0 +1,72 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test181.ams,v 1.2 2003-08-05 15:14:24 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test181.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test is done for checking the correct implementation +-- of the break statement.it checks simple break and break on +-- codition. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN(X : real) RETURN real; + FUNCTION EXP(X : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalSystem.all; +entity VCO is + port(terminal InTerminal,OutTerminal: electrical); +end VCO; + +architecture PhaseIntegrator of VCO is + quantity Vin across Iin through InTerminal to OutTerminal; + constant TwoPi: real := 6.283118530718; -- 2pi + quantity Phase : real; -- phase is a free quantity: + quantity Vout across Iout through OutTerminal; +begin + break Phase => TwoPi; + -- break allows to define the initial conditions + break Phase => 0.0 on Phase'above(TwoPi); + Vout == 2.5*(sin(Phase)); -- output statement +end PhaseIntegrator; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test182.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test182.ams new file mode 100644 index 000000000..d945f0172 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test182.ams @@ -0,0 +1,72 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test182.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test182.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- the test is done for checking the correct implementation +-- of the 'above attribute. + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN (X : real ) RETURN real; + FUNCTION EXP (X : real ) RETURN real; +END PACKAGE electricalSystem; + + +USE work.electricalSystem.all; + +entity test is +port(signal vout:out boolean); +end entity; + +architecture atest of test is + +terminal T1: electrical; +quantity vin across iin through T1; +--constant vt: real:=3.0; +begin +e2 : vout <= vin'above(0.0); +e1: vin == 5.0 * sin(2.0 *3.141592 *100000.0 * real(time'pos(now))*1.0e-12); + +end architecture atest; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test183.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test183.ams new file mode 100644 index 000000000..9cd07f34b --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test183.ams @@ -0,0 +1,59 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test183.ams,v 1.2 2003-08-05 15:14:24 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +-- this model tests for the correst implementation of the 'above +-- statement. +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground REFERENCE; + FUNCTION SIN(X : real) RETURN real; +END PACKAGE electricalSystem; + +use work.electricalsystem.all; + +entity product is +generic(bound:real:=1.0); +port( + quantity out1:real); +end product; + +architecture pro of product is +constant in1:real:=10.0; +constant in2:real:=1.0; +signal outofbound:out boolean; + +begin + outofbound<=true; + out1== in1*in2; + outofbound<=out1'above(bound); + +end pro; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test184.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test184.ams new file mode 100644 index 000000000..ad706e0e2 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test184.ams @@ -0,0 +1,110 @@ + +-- Copyright (C) 2001-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test184.ams,v 1.2 2003-08-05 15:14:24 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +--------------------------------------------------------------------- +---------------------------------------------------------------------- +-- SIERRA REGRESSION TESTING MODEL +-- Develooped at: +-- Distriburted Processing Laboratory +-- University of Cincinnati +-- Cincinnati +---------------------------------------------------------------------- +-- File : test100.ams +-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu) +-- Created : Sept 2001 +---------------------------------------------------------------------- +-- Description : +---------------------------------------------------------------------- +-- half wave Rectifier model ... +-- the test is done for checking the correct implementation +-- of the simultaneous if statement.it checks +-- nature declaration, terminal and quantity declarations. + +---------------------------------------------------------------------- +-- T1 diode D T2 +-- o-----|>|-----o-------o The circuit comprises: +-- | | i) A diode . +-- ( ) >R=100ohms ii) A sinusoidal voltage source. +-- |Vs = 5sinwt > iii)A resistor R. +-- | > +-- |_____________|_______o +-- |gnd +-- ----- +---------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH ground REFERENCE; + FUNCTION SIN (X : real ) RETURN real; + FUNCTION EXP (X : real ) RETURN real; +END PACKAGE electricalSystem; + +---------------------------------------------------------------------- + +USE work.electricalSystem.all; + +ENTITY hwr IS +END hwr; + +ARCHITECTURE ahwr OF hwr IS + + terminal T1, T2 : electrical; + quantity VDiode across IDiode through T1 to T2; + quantity V2 across I2 through T2 ; + quantity VS across T1 ; + + CONSTANT saturation_current : real := 0.0000000000001; + CONSTANT Vt : real := 0.025; + + CONSTANT BV : real := 100.0; + CONSTANT neg_sat : real := -saturation_current; + +BEGIN + + --diode equations + if( vDiode >= (-1.0 * Vt)) USE + eq1: iDiode == saturation_current * (exp(vDiode/Vt) - 1.0); + + ELSIF ((vDiode < (-3.0 * Vt)) AND (vDiode > -BV)) use + eq2: iDiode == neg_sat; + + ELSE + eq3: iDiode == neg_sat * (exp(-(BV + vDiode)/Vt) - 1.0 + + saturation_current); + END USE ; + + eqn2: v2 == 100.0 * i2; + + eqn4: vs == 5.0 * sin(2.0 * 3.14 * 100000.0 * + real(time'pos(now)) * 1.0e-15 ); + +END ahwr ; diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test185.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test185.ams new file mode 100644 index 000000000..785249934 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test185.ams @@ -0,0 +1,56 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test185.ams,v 1.1 2002-03-27 22:11:19 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE; + FUNCTION SIN (X : real ) RETURN real; + FUNCTION EXP (X : real ) RETURN real; +END PACKAGE electricalSystem; + +USE work.electricalSystem.all; + +ENTITY simcase IS +END simcase; + +ARCHITECTURE asimcase OF simcase IS + + terminal T1: electrical; + + quantity v1 across i1 through T1 ; + +BEGIN + eq1: v1==1.0; + if (v1<=1.0) use + e1: null; + end use; +END asimcase ; |