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+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: mixed_model_1.ams,v 1.1 2002-03-27 22:11:17 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-- an example of a model having both a signal assignment statement
+-- as well as a simple simultaneous statement.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND reference;
+    FUNCTION SIN (X : real ) RETURN real;
+    FUNCTION EXP  (X : real ) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+use std.textio.all;
+ENTITY circuit1 IS
+END circuit1;
+
+ARCHITECTURE behavior OF circuit1 IS
+    CONSTANT resistance1 : real := 100.0;        -- value of R1
+    terminal n1 : electrical;
+  QUANTITY vIn ACROSS n1;
+  QUANTITY vR ACROSS iR THROUGH n1 ;
+  signal y:bit:='0';
+BEGIN
+
+process(y)
+begin
+  y <= not(y) after 1000 ns;
+ 
+end process;
+
+ testbench:PROCESS
+        VARIABLE outline : LINE;
+        VARIABLE Headline   : string(1 TO 8) :=
+            "time y";
+        VARIABLE   seperator    : string(1 TO 1) := " ";
+        VARIABLE   flag     : bit := '0';
+        FILE outfile: text OPEN WRITE_MODE IS "mixed_model_1.out";
+    BEGIN
+        IF (flag = '0') THEN
+            flag := '1';
+            WRITE(outline,Headline);
+            WRITELINE(outfile,outline);
+        ELSE
+            WRITE(outline, now);
+            WRITE(outline,seperator);
+            WRITE(outline,y);
+            WRITE(outline,seperator);
+            writeline(outfile,outline); 
+        END IF;
+        WAIT ON y;
+    END PROCESS;
+  res_stmt1: vR == iR * resistance1 ;
+  vsource: vIn == 5.0 * sin(2.0 * 3.14 * 100000.0 * real(time'pos(now)) *  1.0e-15);
+
+END ARCHITECTURE behavior;