1 files changed, 47 insertions, 0 deletions
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_12.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_12.vhd
new file mode 100644
index 000000000..2410f1c7a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_12.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_tb_05_12.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity in_pad is
+  port ( i : in bit;  z : out bit );
+end entity in_pad;
+
+
+entity reg32 is
+  port ( en : in bit;  clk : in bit;  d : in bit_vector(31 downto 0);
+  q : out bit_vector(31 downto 0) );
+end entity reg32;
+
+
+entity adder is
+  port ( a, b : in bit_vector(31 downto 0);
+         y : out bit_vector(31 downto 0);
+	 c : out bit );
+end entity adder;
+
+
+entity filter is
+end entity filter;
+