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-rw-r--r--testsuite/synth/issue2286/tb_test_addsub.vhdl51
-rw-r--r--testsuite/synth/issue2286/test_addsub.vhdl26
-rwxr-xr-xtestsuite/synth/issue2286/testsuite.sh9
3 files changed, 86 insertions, 0 deletions
diff --git a/testsuite/synth/issue2286/tb_test_addsub.vhdl b/testsuite/synth/issue2286/tb_test_addsub.vhdl
new file mode 100644
index 000000000..da2150ebe
--- /dev/null
+++ b/testsuite/synth/issue2286/tb_test_addsub.vhdl
@@ -0,0 +1,51 @@
+entity tb_test_addsub is
+end tb_test_addsub;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+architecture behav of tb_test_addsub is
+ signal s_slv : std_logic_vector(3 downto 0);
+ signal s_nat : natural range 0 to 15;
+ signal s_add_slvslv : std_logic_vector(3 downto 0);
+ signal s_add_slvnat : std_logic_vector(3 downto 0);
+ signal s_add_natslv : std_logic_vector(3 downto 0);
+ signal s_sub_slvslv : std_logic_vector(3 downto 0);
+ signal s_sub_slvnat : std_logic_vector(3 downto 0);
+ signal s_sub_natslv : std_logic_vector(3 downto 0);
+begin
+ dut: entity work.test_addsub
+ port map (s_slv,
+ s_nat,
+ s_add_slvslv,
+ s_add_slvnat,
+ s_add_natslv,
+ s_sub_slvslv,
+ s_sub_slvnat,
+ s_sub_natslv);
+ process
+ begin
+ s_slv <= x"6";
+ s_nat <= 6;
+ wait for 1 ns;
+ assert s_add_slvslv = x"C" severity failure;
+ assert s_add_slvnat = x"C" severity failure;
+ assert s_add_natslv = x"C" severity failure;
+ assert s_sub_slvslv = x"0" severity failure;
+ assert s_sub_slvnat = x"0" severity failure;
+ assert s_sub_natslv = x"0" severity failure;
+
+ s_slv <= x"6";
+ s_nat <= 10;
+ wait for 1 ns;
+ assert s_add_slvslv = x"C" severity failure;
+ assert s_add_slvnat = x"0" severity failure;
+ assert s_add_natslv = x"0" severity failure;
+ assert s_sub_slvslv = x"0" severity failure;
+ assert s_sub_slvnat = x"C" severity failure;
+ assert s_sub_natslv = x"4" severity failure;
+
+ wait;
+ end process;
+end behav;
diff --git a/testsuite/synth/issue2286/test_addsub.vhdl b/testsuite/synth/issue2286/test_addsub.vhdl
new file mode 100644
index 000000000..00e6aed21
--- /dev/null
+++ b/testsuite/synth/issue2286/test_addsub.vhdl
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std_unsigned.all;
+
+entity test_addsub is
+ port (
+ slv : in std_logic_vector(3 downto 0);
+ nat : in natural range 0 to 15;
+ add_slvslv : out std_logic_vector(3 downto 0);
+ add_slvnat : out std_logic_vector(3 downto 0);
+ add_natslv : out std_logic_vector(3 downto 0);
+ sub_slvslv : out std_logic_vector(3 downto 0);
+ sub_slvnat : out std_logic_vector(3 downto 0);
+ sub_natslv : out std_logic_vector(3 downto 0)
+ );
+end;
+
+architecture rtl of test_addsub is
+begin
+ add_slvslv <= slv + slv;
+ add_slvnat <= slv + nat;
+ add_natslv <= nat + slv;
+ sub_slvslv <= slv - slv;
+ sub_slvnat <= slv - nat;
+ sub_natslv <= nat - slv;
+end;
diff --git a/testsuite/synth/issue2286/testsuite.sh b/testsuite/synth/issue2286/testsuite.sh
new file mode 100755
index 000000000..e4f4b7ded
--- /dev/null
+++ b/testsuite/synth/issue2286/testsuite.sh
@@ -0,0 +1,9 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+
+synth_tb test_addsub
+
+echo "Test successful"