4 files changed, 81 insertions, 0 deletions
diff --git a/testsuite/synth/issue2124/a.vhdl b/testsuite/synth/issue2124/a.vhdl
new file mode 100644
index 000000000..ad35b843a
--- /dev/null
+++ b/testsuite/synth/issue2124/a.vhdl
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity a is
+end entity;
+
+architecture behaviour of a is
+
+  component b
+    port (
+      c : in  std_logic;
+      q : out std_logic
+      );
+  end component;
+  
+begin
+
+  inst : b
+    port map (
+      c => '0',
+      q => open
+      );
+  
+end architecture;
diff --git a/testsuite/synth/issue2124/a2.vhdl b/testsuite/synth/issue2124/a2.vhdl
new file mode 100644
index 000000000..eb75b51b4
--- /dev/null
+++ b/testsuite/synth/issue2124/a2.vhdl
@@ -0,0 +1,25 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity a2 is
+end entity;
+
+architecture behaviour of a2 is
+
+  component b
+    port (
+      c : in  std_logic;
+      q : out std_logic
+      );
+  end component;
+
+  for inst : b use entity work.b;
+begin
+
+  inst : b
+    port map (
+      c => '0',
+      q => open
+      );
+  
+end architecture;
diff --git a/testsuite/synth/issue2124/b.vhdl b/testsuite/synth/issue2124/b.vhdl
new file mode 100644
index 000000000..5f35b2d42
--- /dev/null
+++ b/testsuite/synth/issue2124/b.vhdl
@@ -0,0 +1,23 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity b is
+  port (
+    c : in  std_logic;
+    d : in  std_logic;
+    q : out std_logic
+    );
+end entity;
+
+architecture behaviour of b is
+begin
+
+  process (c)
+  begin
+    if rising_edge(c)
+    then
+      q <= d;
+    end if;
+  end process;
+  
+end architecture;
diff --git a/testsuite/synth/issue2124/testsuite.sh b/testsuite/synth/issue2124/testsuite.sh
new file mode 100755
index 000000000..9e304da10
--- /dev/null
+++ b/testsuite/synth/issue2124/testsuite.sh
@@ -0,0 +1,9 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth a.vhdl b.vhdl -e a > syn_a.vhdl
+
+synth --expect-failure --std=93 a2.vhdl b.vhdl -e a2
+
+echo "Test successful"