diff options
Diffstat (limited to 'testsuite/synth')
-rw-r--r-- | testsuite/synth/issue955/ent.vhdl | 24 | ||||
-rw-r--r-- | testsuite/synth/issue955/ent1.vhdl | 25 | ||||
-rw-r--r-- | testsuite/synth/issue955/tb_ent1.vhdl | 55 | ||||
-rwxr-xr-x | testsuite/synth/issue955/testsuite.sh | 22 |
4 files changed, 126 insertions, 0 deletions
diff --git a/testsuite/synth/issue955/ent.vhdl b/testsuite/synth/issue955/ent.vhdl new file mode 100644 index 000000000..f3d23f5dc --- /dev/null +++ b/testsuite/synth/issue955/ent.vhdl @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity ent is + port ( + clk : in std_logic; + o : out bit + ); +end ent; + +architecture a of ent is + type reg_t is array(0 to 7) of std_logic_vector(0 to 7); + + signal reg : reg_t; +begin + process(clk) + begin + if rising_edge(clk) then + reg <= reg(1 to 7) & x"00"; + end if; + end process; + + o <= '1'; +end; diff --git a/testsuite/synth/issue955/ent1.vhdl b/testsuite/synth/issue955/ent1.vhdl new file mode 100644 index 000000000..68c0f9c06 --- /dev/null +++ b/testsuite/synth/issue955/ent1.vhdl @@ -0,0 +1,25 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity ent1 is + port ( + clk : in std_logic; + o : out std_logic_vector (0 to 7) + ); +end ent1; + +architecture a of ent1 is + type reg_t is array(0 to 7) of std_logic_vector(0 to 7); + + signal reg : reg_t := (x"10", x"11", x"12", x"13", + x"14", x"15", x"16", x"17"); +begin + process(clk) + begin + if rising_edge(clk) then + reg <= reg(1 to 7) & x"00"; + end if; + end process; + + o <= reg (0); +end; diff --git a/testsuite/synth/issue955/tb_ent1.vhdl b/testsuite/synth/issue955/tb_ent1.vhdl new file mode 100644 index 000000000..9cb8bb6b4 --- /dev/null +++ b/testsuite/synth/issue955/tb_ent1.vhdl @@ -0,0 +1,55 @@ +entity tb_ent1 is +end tb_ent1; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_ent1 is + signal clk : std_logic; + signal dout : std_logic_vector (7 downto 0); +begin + dut: entity work.ent1 + port map (clk => clk, o => dout); + + process + procedure pulse is + begin + clk <= '0'; + wait for 1 ns; + clk <= '1'; + wait for 1 ns; + end pulse; + begin + wait for 1 ns; + assert dout = x"10" severity failure; + + pulse; + assert dout = x"11" severity failure; + + pulse; + assert dout = x"12" severity failure; + + pulse; + assert dout = x"13" severity failure; + + pulse; + assert dout = x"14" severity failure; + + pulse; + assert dout = x"15" severity failure; + + pulse; + assert dout = x"16" severity failure; + + pulse; + assert dout = x"17" severity failure; + + pulse; + assert dout = x"00" severity failure; + + pulse; + assert dout = x"00" severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/issue955/testsuite.sh b/testsuite/synth/issue955/testsuite.sh new file mode 100755 index 000000000..39568eb47 --- /dev/null +++ b/testsuite/synth/issue955/testsuite.sh @@ -0,0 +1,22 @@ +#! /bin/sh + +. ../../testenv.sh + +for f in ent; do + synth $f.vhdl -e $f > syn_$f.vhdl +# analyze syn_$f.vhdl +done +clean + +for t in ent1; do + analyze $t.vhdl tb_$t.vhdl + elab_simulate tb_$t + clean + + synth $t.vhdl -e $t > syn_$t.vhdl + analyze syn_$t.vhdl tb_$t.vhdl + elab_simulate tb_$t --ieee-asserts=disable-at-0 + clean +done + +echo "Test successful" |