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Diffstat (limited to 'testsuite/synth/sns01/muls.vhdl')
| -rw-r--r-- | testsuite/synth/sns01/muls.vhdl | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/testsuite/synth/sns01/muls.vhdl b/testsuite/synth/sns01/muls.vhdl new file mode 100644 index 000000000..01e5a9c84 --- /dev/null +++ b/testsuite/synth/sns01/muls.vhdl @@ -0,0 +1,34 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity muls is + port ( + l4 : std_logic_vector (3 downto 0); + r3 : std_logic_vector (2 downto 0); + + mul_u4u3u : out std_logic_vector (6 downto 0); + mul_s4s3s : out std_logic_vector (6 downto 0); + mul_u4s3s : out std_logic_vector (7 downto 0); + mul_s4u3s : out std_logic_vector (7 downto 0); + + mul_u4u3v : out std_logic_vector (6 downto 0); + mul_s4s3v : out std_logic_vector (6 downto 0); + mul_u4s3v : out std_logic_vector (7 downto 0); + mul_s4u3v : out std_logic_vector (7 downto 0)); +end muls; + +library ieee; +use ieee.std_logic_arith.all; + +architecture behav of muls is +begin + mul_u4u3u <= std_logic_vector (unsigned'(unsigned(l4) * unsigned(r3))); + mul_s4s3s <= std_logic_vector (signed'(signed(l4) * signed(r3))); + mul_u4s3s <= std_logic_vector (signed'(unsigned(l4) * signed(r3))); + mul_s4u3s <= std_logic_vector (signed'(signed(l4) * unsigned(r3))); + + mul_u4u3v <= unsigned(l4) * unsigned(r3); + mul_s4s3v <= signed(l4) * signed(r3); + mul_u4s3v <= unsigned(l4) * signed(r3); + mul_s4u3v <= signed(l4) * unsigned(r3); +end behav; |