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Diffstat (limited to 'testsuite/synth/slice02/tb_slice01.vhdl')
-rw-r--r-- | testsuite/synth/slice02/tb_slice01.vhdl | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/testsuite/synth/slice02/tb_slice01.vhdl b/testsuite/synth/slice02/tb_slice01.vhdl new file mode 100644 index 000000000..ec684fba0 --- /dev/null +++ b/testsuite/synth/slice02/tb_slice01.vhdl @@ -0,0 +1,22 @@ +entity tb_slice01 is +end tb_slice01; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_slice01 is + signal di : std_logic_vector (7 downto 0); + signal do : std_logic_vector (3 downto 0); +begin + dut: entity work.slice01 + port map (di, do); + + process + begin + di <= b"11_10_01_00"; + wait for 1 ns; + assert do = b"10_11" severity error; + + wait; + end process; +end behav; |