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-rw-r--r--testsuite/synth/psl02/verif2.vhdl6
1 files changed, 6 insertions, 0 deletions
diff --git a/testsuite/synth/psl02/verif2.vhdl b/testsuite/synth/psl02/verif2.vhdl
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--- /dev/null
+++ b/testsuite/synth/psl02/verif2.vhdl
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+vunit verif2 (assert2)
+{
+ default clock is rising_edge(clk);
+ assume always cnt < 10;
+ assert always cnt /= 5 abort rst;
+}