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-rw-r--r--testsuite/synth/issue8/tb_test5.vhdl19
-rw-r--r--testsuite/synth/issue8/tb_vector8_test1.vhdl19
-rw-r--r--testsuite/synth/issue8/test2.vhdl15
-rw-r--r--testsuite/synth/issue8/test3.vhdl28
-rw-r--r--testsuite/synth/issue8/test4.vhdl28
-rw-r--r--testsuite/synth/issue8/test5.vhdl15
-rwxr-xr-xtestsuite/synth/issue8/testsuite.sh16
-rw-r--r--testsuite/synth/issue8/vector8_test1.vhdl16
8 files changed, 156 insertions, 0 deletions
diff --git a/testsuite/synth/issue8/tb_test5.vhdl b/testsuite/synth/issue8/tb_test5.vhdl
new file mode 100644
index 000000000..14ef0660e
--- /dev/null
+++ b/testsuite/synth/issue8/tb_test5.vhdl
@@ -0,0 +1,19 @@
+entity tb_test5 is
+end tb_test5;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_test5 is
+ signal r : std_logic_vector(7 downto 0);
+begin
+ dut: entity work.test5
+ port map (r);
+
+ process
+ begin
+ wait for 1 ns;
+ assert r(7) = '1' severity failure;
+ wait;
+ end process;
+end behav;
diff --git a/testsuite/synth/issue8/tb_vector8_test1.vhdl b/testsuite/synth/issue8/tb_vector8_test1.vhdl
new file mode 100644
index 000000000..0a37884d5
--- /dev/null
+++ b/testsuite/synth/issue8/tb_vector8_test1.vhdl
@@ -0,0 +1,19 @@
+entity tb_vector8_test1 is
+end tb_vector8_test1;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_vector8_test1 is
+ signal r : std_logic;
+begin
+ dut: entity work.vector8_test1
+ port map (r);
+
+ process
+ begin
+ wait for 1 ns;
+ assert r = '1' severity failure;
+ wait;
+ end process;
+end behav;
diff --git a/testsuite/synth/issue8/test2.vhdl b/testsuite/synth/issue8/test2.vhdl
new file mode 100644
index 000000000..dca1601bb
--- /dev/null
+++ b/testsuite/synth/issue8/test2.vhdl
@@ -0,0 +1,15 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity test2 is
+ port (led: out std_logic_vector (7 downto 0));
+end test2;
+
+architecture synth of test2 is
+
+begin
+ led(7) <= '0';
+ led(6) <= '1';
+-- led(5) <= '0';
+-- led(3 downto 0) <= x"9";
+end synth;
diff --git a/testsuite/synth/issue8/test3.vhdl b/testsuite/synth/issue8/test3.vhdl
new file mode 100644
index 000000000..3e17936ca
--- /dev/null
+++ b/testsuite/synth/issue8/test3.vhdl
@@ -0,0 +1,28 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity test3 is
+ port (led: out std_logic_vector (7 downto 0);
+ rst : std_logic;
+ clk : std_logic);
+end test3;
+
+architecture synth of test3 is
+ signal int : std_logic_vector(1 downto 0);
+begin
+-- led(7) <= '0';
+-- led(6) <= '1';
+-- led(5) <= '0';
+-- led(3 downto 0) <= x"9";
+ process (clk) is
+ begin
+ if rising_edge (clk) then
+ if rst = '1' then
+ int(1) <= '0';
+ else
+ int(1) <= not int(1);
+ end if;
+ end if;
+ end process;
+ led(5) <= int (1);
+end synth;
diff --git a/testsuite/synth/issue8/test4.vhdl b/testsuite/synth/issue8/test4.vhdl
new file mode 100644
index 000000000..4875fa1ec
--- /dev/null
+++ b/testsuite/synth/issue8/test4.vhdl
@@ -0,0 +1,28 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity test4 is
+ port (led: out std_logic_vector (7 downto 0);
+ rst : std_logic;
+ clk : std_logic);
+end test4;
+
+architecture synth of test4 is
+ signal int : std_logic_vector(1 downto 0);
+begin
+-- led(7) <= '0';
+-- led(6) <= '1';
+-- led(5) <= '0';
+-- led(3 downto 0) <= x"9";
+-- int(0) <= '0';
+ process (clk) is
+ begin
+ if rst = '1' then
+ int(1) <= '0';
+ elsif rising_edge (clk) then
+ int(1) <= not int(1);
+ end if;
+ end process;
+ led(5) <= int (1);
+-- led(4) <= int(0);
+end synth;
diff --git a/testsuite/synth/issue8/test5.vhdl b/testsuite/synth/issue8/test5.vhdl
new file mode 100644
index 000000000..0d1fbc0e5
--- /dev/null
+++ b/testsuite/synth/issue8/test5.vhdl
@@ -0,0 +1,15 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity test5 is
+ port (led: out std_logic_vector (7 downto 0));
+end test5;
+
+architecture synth of test5 is
+
+begin
+ led(7) <= '1';
+-- led(6) <= '1';
+-- led(5) <= '0';
+-- led(3 downto 0) <= x"9";
+end synth;
diff --git a/testsuite/synth/issue8/testsuite.sh b/testsuite/synth/issue8/testsuite.sh
new file mode 100755
index 000000000..df039cb08
--- /dev/null
+++ b/testsuite/synth/issue8/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in vector8_test1 test5; do
+ analyze $t.vhdl tb_$t.vhdl
+ elab_simulate tb_$t
+ clean
+
+ synth $t.vhdl -e $t > syn_$t.vhdl
+ analyze syn_$t.vhdl tb_$t.vhdl
+ elab_simulate tb_$t
+ clean
+done
+
+echo "Test successful"
diff --git a/testsuite/synth/issue8/vector8_test1.vhdl b/testsuite/synth/issue8/vector8_test1.vhdl
new file mode 100644
index 000000000..585d003b0
--- /dev/null
+++ b/testsuite/synth/issue8/vector8_test1.vhdl
@@ -0,0 +1,16 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity vector8_test1 is
+ port (led7: out std_logic);
+end vector8_test1;
+
+architecture synth of vector8_test1 is
+
+signal v : std_logic_vector(7 downto 0);
+
+begin
+ v(7) <= '1';
+ led7 <= v(7);
+end synth;