1 files changed, 23 insertions, 0 deletions
diff --git a/testsuite/synth/issue662/psl_stable.vhdl b/testsuite/synth/issue662/psl_stable.vhdl
new file mode 100644
index 000000000..675cdbd56
--- /dev/null
+++ b/testsuite/synth/issue662/psl_stable.vhdl
@@ -0,0 +1,23 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity psl_stable is
+  port (clk, a, b, c : in std_logic;
+        d         : in std_logic_vector(3 downto 0)
+  );
+end entity psl_stable;
+
+
+architecture psl of psl_stable is
+begin
+
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
+  -- This assertion holds
+  STABLE_0_a : assert always {not a; a} |=> (stable(c) until_ b);
+
+  -- This assertion holds
+  STABLE_1_a : assert always {not a; a} |=> (stable(d) until_ b);
+
+end architecture psl;