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-rwxr-xr-xtestsuite/synth/issue2054/testsuite.sh20
1 files changed, 20 insertions, 0 deletions
diff --git a/testsuite/synth/issue2054/testsuite.sh b/testsuite/synth/issue2054/testsuite.sh
new file mode 100755
index 000000000..a51e970f4
--- /dev/null
+++ b/testsuite/synth/issue2054/testsuite.sh
@@ -0,0 +1,20 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth --out=verilog flip_flop.vhdl -e > syn_flip_flop.v
+if grep "input wire" syn_flip_flop.v; then
+ exit 1
+fi
+
+synth --out=verilog testcase2.vhdl -e > syn_testcase2.v
+if grep "assign edge" syn_testcase2.v; then
+ exit 1
+fi
+
+synth --out=verilog testcase3.vhdl -e > syn_testcase3.v
+if grep "edge =" syn_testcase3.v; then
+ exit 1
+fi
+
+echo "Test successful"