5 files changed, 125 insertions, 0 deletions
diff --git a/testsuite/synth/issue2032/repro1.vhdl b/testsuite/synth/issue2032/repro1.vhdl
new file mode 100644
index 000000000..ef19fa66d
--- /dev/null
+++ b/testsuite/synth/issue2032/repro1.vhdl
@@ -0,0 +1,29 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.ALL;
+
+entity range_filter is
+    generic(
+        G_WIDTH              :   natural := 29
+    );
+    port(
+        filter_input       : in    std_logic_vector(G_WIDTH - 1 downto 0);
+        valid              : out   std_logic
+    );
+end entity;
+
+architecture rtl of range_filter is
+    procedure to_decimal(
+        signal val   : in  std_logic_vector(28 downto 0);
+        signal res   : out natural
+    ) is
+    begin
+        res <= to_integer(unsigned(val));
+    end procedure to_decimal;
+
+    signal value_dec                :   natural range 0 to (2 ** G_WIDTH - 1);
+begin
+    to_decimal(filter_input, value_dec);
+
+    valid  <= '1' when value_dec <= 12 else '0';
+end architecture;
diff --git a/testsuite/synth/issue2032/repro2.vhdl b/testsuite/synth/issue2032/repro2.vhdl
new file mode 100644
index 000000000..f03e63c91
--- /dev/null
+++ b/testsuite/synth/issue2032/repro2.vhdl
@@ -0,0 +1,29 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.ALL;
+
+entity range_filter is
+    generic(
+        G_WIDTH              :   natural := 29
+    );
+    port(
+        filter_input       : in    std_logic_vector(G_WIDTH - 1 downto 0);
+        valid              : out   std_logic
+    );
+end entity;
+
+architecture rtl of range_filter is
+    procedure to_decimal(
+        signal val   : in  std_logic_vector(15 downto 0);
+        signal res   : out natural
+    ) is
+    begin
+        res <= to_integer(unsigned(val));
+    end procedure to_decimal;
+
+    signal value_dec                :   natural range 0 to (2 ** G_WIDTH - 1);
+begin
+    to_decimal(filter_input, value_dec);
+
+    valid  <= '1' when value_dec <= 12 else '0';
+end architecture;
diff --git a/testsuite/synth/issue2032/repro3.vhdl b/testsuite/synth/issue2032/repro3.vhdl
new file mode 100644
index 000000000..ef19fa66d
--- /dev/null
+++ b/testsuite/synth/issue2032/repro3.vhdl
@@ -0,0 +1,29 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.ALL;
+
+entity range_filter is
+    generic(
+        G_WIDTH              :   natural := 29
+    );
+    port(
+        filter_input       : in    std_logic_vector(G_WIDTH - 1 downto 0);
+        valid              : out   std_logic
+    );
+end entity;
+
+architecture rtl of range_filter is
+    procedure to_decimal(
+        signal val   : in  std_logic_vector(28 downto 0);
+        signal res   : out natural
+    ) is
+    begin
+        res <= to_integer(unsigned(val));
+    end procedure to_decimal;
+
+    signal value_dec                :   natural range 0 to (2 ** G_WIDTH - 1);
+begin
+    to_decimal(filter_input, value_dec);
+
+    valid  <= '1' when value_dec <= 12 else '0';
+end architecture;
diff --git a/testsuite/synth/issue2032/repro4.vhdl b/testsuite/synth/issue2032/repro4.vhdl
new file mode 100644
index 000000000..238b80b1b
--- /dev/null
+++ b/testsuite/synth/issue2032/repro4.vhdl
@@ -0,0 +1,28 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.ALL;
+
+entity range_filter is
+    generic(
+        G_WIDTH              :   natural := 29
+    );
+    port(
+        filter_input       : in    std_logic_vector(G_WIDTH - 1 downto 0);
+        valid              : out   std_logic
+    );
+end entity;
+
+architecture rtl of range_filter is
+    procedure to_decimal(
+        signal res   : out natural
+    ) is
+    begin
+        res <= 4;
+    end procedure to_decimal;
+
+    signal value_dec                :   natural range 0 to (2 ** G_WIDTH - 1);
+begin
+    to_decimal(value_dec);
+
+    valid  <= '1' when value_dec <= 12 else '0';
+end architecture;
diff --git a/testsuite/synth/issue2032/testsuite.sh b/testsuite/synth/issue2032/testsuite.sh
new file mode 100755
index 000000000..16335c1b0
--- /dev/null
+++ b/testsuite/synth/issue2032/testsuite.sh
@@ -0,0 +1,10 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_failure repro1.vhdl -e
+synth_failure repro2.vhdl -e
+synth_failure repro3.vhdl -e
+synth_failure repro4.vhdl -e
+
+echo "Test successful"