1 files changed, 12 insertions, 0 deletions
diff --git a/testsuite/synth/issue1972/ent.vhdl b/testsuite/synth/issue1972/ent.vhdl
new file mode 100644
index 000000000..502f47785
--- /dev/null
+++ b/testsuite/synth/issue1972/ent.vhdl
@@ -0,0 +1,12 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ent is
+  port (output : out std_ulogic);
+end entity;
+
+architecture rtl of ent is
+  signal sr : std_ulogic_vector(0 downto 1);
+begin
+  output <= sr(1);
+end architecture;