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-rw-r--r--testsuite/synth/issue1217/tb_top.vhdl21
1 files changed, 21 insertions, 0 deletions
diff --git a/testsuite/synth/issue1217/tb_top.vhdl b/testsuite/synth/issue1217/tb_top.vhdl
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+++ b/testsuite/synth/issue1217/tb_top.vhdl
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+entity tb_top is
+end tb_top;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_top is
+ signal p : std_logic;
+ signal q : std_logic;
+begin
+ dut: entity work.top
+ port map (p, q);
+
+ process
+ begin
+ wait for 1 ns;
+ assert p = '0' severity failure;
+ assert q = '1' severity failure;
+ wait;
+ end process;
+end behav;