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-rw-r--r--testsuite/synth/issue1058/ent.vhdl22
1 files changed, 22 insertions, 0 deletions
diff --git a/testsuite/synth/issue1058/ent.vhdl b/testsuite/synth/issue1058/ent.vhdl
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index 000000000..b636b4780
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+++ b/testsuite/synth/issue1058/ent.vhdl
@@ -0,0 +1,22 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ent is
+ port (
+ clk : in std_logic;
+ o : out std_logic_vector(31 downto 0)
+ );
+end ent;
+
+architecture a of ent is
+begin
+ process(clk)
+ variable var : std_logic_vector(31 downto 0);
+ begin
+ if rising_edge(clk) then
+ var := x"0000_0000";
+ o <= x"8000_0000" or var;
+ end if;
+ end process;
+end a;
+