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-rw-r--r--testsuite/synth/dff01/dff14.vhdl20
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diff --git a/testsuite/synth/dff01/dff14.vhdl b/testsuite/synth/dff01/dff14.vhdl
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+++ b/testsuite/synth/dff01/dff14.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+
+entity dff14 is
+ port (q : out std_logic;
+ d : std_logic;
+ clk : std_logic);
+end dff14;
+
+architecture behav of dff14 is
+begin
+ process (clk) is
+ variable m : std_logic;
+ begin
+ if rising_edge (clk) then
+ m := d;
+ end if;
+ q <= m;
+ end process;
+end behav;