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Diffstat (limited to 'testsuite/synth/attr01/attr02.vhdl')
-rw-r--r-- | testsuite/synth/attr01/attr02.vhdl | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/testsuite/synth/attr01/attr02.vhdl b/testsuite/synth/attr01/attr02.vhdl new file mode 100644 index 000000000..bb7016bde --- /dev/null +++ b/testsuite/synth/attr01/attr02.vhdl @@ -0,0 +1,31 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity attr02 is + port ( + rst : std_logic; + clk : std_logic; + cnt : out std_logic_vector (7 downto 0) + ); + attribute keep : boolean; + attribute keep of rst : signal is True; +end attr02; + +architecture behav of attr02 is + signal counter : std_logic_vector (7 downto 0); + +begin + process (clk) + begin + if rising_edge (clk) then + if rst = '1' then + counter <= (others => '0'); + else + counter <= std_logic_vector (unsigned (counter) + 1); + end if; + end if; + end process; + + cnt <= counter; +end behav; |