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-rw-r--r--testsuite/gna/issue1864/test.vhdl19
-rwxr-xr-xtestsuite/gna/issue1864/testsuite.sh11
2 files changed, 30 insertions, 0 deletions
diff --git a/testsuite/gna/issue1864/test.vhdl b/testsuite/gna/issue1864/test.vhdl
new file mode 100644
index 000000000..c6dce7dfd
--- /dev/null
+++ b/testsuite/gna/issue1864/test.vhdl
@@ -0,0 +1,19 @@
+package int_vec_pkg is
+ type t_integer_array is array (0 downto 0) of integer_vector(0 downto 0);
+ type t_real_array is array (0 downto 0) of real_vector(0 downto 0);
+ type t_time_array is array (0 downto 0) of time_vector(0 downto 0);
+ signal int_vec : t_integer_array;
+ signal real_vec : t_real_array;
+ signal time_vec : t_time_array;
+end package;
+use work.int_vec_pkg.all;
+
+entity test is
+end entity test;
+architecture beh of test is
+begin
+ process
+ begin
+ wait;
+ end process;
+end architecture beh;
diff --git a/testsuite/gna/issue1864/testsuite.sh b/testsuite/gna/issue1864/testsuite.sh
new file mode 100755
index 000000000..1d84c0f57
--- /dev/null
+++ b/testsuite/gna/issue1864/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze test.vhdl
+elab_simulate test
+
+clean
+
+echo "Test successful"