3 files changed, 58 insertions, 0 deletions
diff --git a/testsuite/gna/issue1120/repro2.vhdl b/testsuite/gna/issue1120/repro2.vhdl
new file mode 100644
index 000000000..915b66ba4
--- /dev/null
+++ b/testsuite/gna/issue1120/repro2.vhdl
@@ -0,0 +1,19 @@
+entity repro2 is
+  generic(
+    BITS  : positive := 4);
+  port(
+    min : in  bit_vector(BITS - 1 downto 0) := "1010");
+end entity;
+
+architecture rtl of repro2 is
+begin
+  process
+    variable sum : bit_vector(BITS - 2 downto 0);
+    variable carry : bit;
+  begin
+    (carry, sum) := min;
+    assert carry = '1';
+    assert sum = "010";
+    wait;
+  end process;
+end architecture;
diff --git a/testsuite/gna/issue1120/test.vhdl b/testsuite/gna/issue1120/test.vhdl
new file mode 100644
index 000000000..3cbb63e16
--- /dev/null
+++ b/testsuite/gna/issue1120/test.vhdl
@@ -0,0 +1,25 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity test is
+  generic(
+    BITS  : positive;
+    ZEROS : unsigned(BITS - 1 downto 0) := (others => '0'));
+  port(
+    min : in  u_unsigned(BITS - 1 downto 0) := ZEROS);
+end entity;
+
+architecture rtl of test is
+
+begin
+
+  process
+    variable sum : unsigned(BITS - 2 downto 0);
+    variable carry : std_ulogic;
+  begin
+    (carry, sum) := min;
+    wait;
+  end process;
+
+end architecture;
diff --git a/testsuite/gna/issue1120/testsuite.sh b/testsuite/gna/issue1120/testsuite.sh
new file mode 100755
index 000000000..58e638319
--- /dev/null
+++ b/testsuite/gna/issue1120/testsuite.sh
@@ -0,0 +1,14 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze repro2.vhdl
+elab_simulate repro2
+
+analyze test.vhdl
+elab_simulate test
+
+clean
+
+echo "Test successful"