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-rw-r--r--testsuite/gna/issue817/repro1.vhdl15
-rwxr-xr-xtestsuite/gna/issue817/testsuite.sh10
2 files changed, 25 insertions, 0 deletions
diff --git a/testsuite/gna/issue817/repro1.vhdl b/testsuite/gna/issue817/repro1.vhdl
new file mode 100644
index 000000000..4ff7d8bd9
--- /dev/null
+++ b/testsuite/gna/issue817/repro1.vhdl
@@ -0,0 +1,15 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ent is
+end entity;
+
+architecture arch of ent is
+begin
+ process
+ variable valid_tmp : std_logic_vector := (others => '0');
+ begin
+ valid_tmp := (others => '0');
+ wait;
+ end process;
+end architecture;
diff --git a/testsuite/gna/issue817/testsuite.sh b/testsuite/gna/issue817/testsuite.sh
new file mode 100755
index 000000000..ff7dfbeef
--- /dev/null
+++ b/testsuite/gna/issue817/testsuite.sh
@@ -0,0 +1,10 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze_failure -frelaxed repro1.vhdl
+
+clean
+
+echo "Test successful"