3 files changed, 66 insertions, 0 deletions
diff --git a/testsuite/gna/issue676/adder.vhdl b/testsuite/gna/issue676/adder.vhdl
new file mode 100644
index 000000000..a69c1cc99
--- /dev/null
+++ b/testsuite/gna/issue676/adder.vhdl
@@ -0,0 +1,33 @@
+library ieee ;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std_unsigned.all;
+
+entity Adder is
+	
+generic(
+    N : positive := 4
+    );
+    
+port(
+    A    : in  std_logic_vector(N-1 downto 0);
+    B    : in  std_logic_vector(N-1 downto 0);
+    Cin  : in  std_logic;
+    Sum  : out std_logic_vector(N-1 downto 0);
+    Cout : out std_logic
+    );
+    
+end Adder;
+
+architecture RTL of Adder is
+	signal cout_sum: std_logic_vector(Sum'length downto 0);
+begin
+
+--	This works fine:
+--  cout_sum <= ("0" & A) + B + Cin;
+--	Cout <= cout_sum(Sum'length);
+--	Sum <= cout_sum(Sum'length-1 downto 0);
+
+-- This crashes GHDL:
+	(Cout, Sum) <= ("0" & A) + B + Cin;
+
+end RTL; 
diff --git a/testsuite/gna/issue676/inc2.vhdl b/testsuite/gna/issue676/inc2.vhdl
new file mode 100644
index 000000000..62b301166
--- /dev/null
+++ b/testsuite/gna/issue676/inc2.vhdl
@@ -0,0 +1,21 @@
+library ieee ;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std_unsigned.all;
+
+entity Inc2 is
+
+generic(
+    N : positive := 4
+    );
+
+port(
+    A    : in  std_logic_vector(N-1 downto 0);
+    Sum  : out std_logic_vector(N downto 0)
+    );
+
+end Inc2;
+
+architecture RTL of Inc2 is
+begin
+  sum <= ('0', A) + 1;
+end RTL;
diff --git a/testsuite/gna/issue676/testsuite.sh b/testsuite/gna/issue676/testsuite.sh
new file mode 100755
index 000000000..d1244d652
--- /dev/null
+++ b/testsuite/gna/issue676/testsuite.sh
@@ -0,0 +1,12 @@
+#! /bin/sh
+
+#exit 0
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze adder.vhdl
+elab_simulate adder
+
+clean
+
+echo "Test successful"