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-rw-r--r--testsuite/gna/issue524/cond.vhdl21
1 files changed, 21 insertions, 0 deletions
diff --git a/testsuite/gna/issue524/cond.vhdl b/testsuite/gna/issue524/cond.vhdl
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+++ b/testsuite/gna/issue524/cond.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cond is
+ port (i, rst, clk : std_logic;
+ o : out std_logic);
+end;
+
+architecture behav of cond is
+begin
+ process (clk) is
+ begin
+ if rising_edge(clk) then
+ if rst then
+ o <= '0';
+ else
+ o <= i;
+ end if;
+ end if;
+ end process;
+end;