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-rw-r--r--testsuite/gna/issue2066/repro1.vhdl14
1 files changed, 14 insertions, 0 deletions
diff --git a/testsuite/gna/issue2066/repro1.vhdl b/testsuite/gna/issue2066/repro1.vhdl
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index 000000000..aa1dfca11
--- /dev/null
+++ b/testsuite/gna/issue2066/repro1.vhdl
@@ -0,0 +1,14 @@
+entity repro1 is
+end;
+
+architecture rtl of repro1 is
+ signal vec : bit_vector(7 downto 0);
+begin
+ vec <= (3 downto 0 => "111", others => '0'); -- Associate a 3 bit element to a 4 bit slice
+ process
+ begin
+ wait for 1 ns;
+ report to_string(vec);
+ wait;
+ end process;
+end architecture rtl;