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-rw-r--r--testsuite/gna/issue2066/aggregate_bug.vhdl18
1 files changed, 18 insertions, 0 deletions
diff --git a/testsuite/gna/issue2066/aggregate_bug.vhdl b/testsuite/gna/issue2066/aggregate_bug.vhdl
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+++ b/testsuite/gna/issue2066/aggregate_bug.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+
+entity aggregate_bug is
+end entity aggregate_bug;
+
+architecture rtl of aggregate_bug is
+ signal vec : std_logic_vector(7 downto 0);
+begin
+ vec <= (3 downto 0 => "111", others => '0'); -- Associate a 3 bit element to a 4 bit slice
+ process
+ begin
+ wait for 1 ns;
+ report to_string(vec);
+ wait for 1 ns;
+ std.env.finish;
+ end process;
+end architecture rtl;