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-rw-r--r--testsuite/gna/bug075/dff.vhdl48
1 files changed, 48 insertions, 0 deletions
diff --git a/testsuite/gna/bug075/dff.vhdl b/testsuite/gna/bug075/dff.vhdl
new file mode 100644
index 000000000..d0eb81371
--- /dev/null
+++ b/testsuite/gna/bug075/dff.vhdl
@@ -0,0 +1,48 @@
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity dff is
+ port (
+ d, clk: in std_logic;
+ q: out std_logic
+ );
+end entity dff;
+
+architecture behave of dff is
+begin
+ process (clk)
+ begin
+ if clk = '1' then
+ q <= d;
+ end if;
+ end process;
+end architecture behave;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity dff is
+end entity dff;
+
+architecture behave of dff is
+ component dff is
+ port (
+ d, clk: in std_logic;
+ q: out std_logic
+ );
+ end component;
+ signal d_in: std_logic;
+ signal clk_in: std_logic;
+ signal q_out: std_logic;
+begin
+d_ff:
+ dff port map ( d_in, clk_in, q_out);
+no_label:
+ process
+ begin
+ if clk_in = '1' then
+ q_out <= d_in;
+ end if;
+ end process;
+end architecture behave;