diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/std_names.adb | 1 | ||||
| -rw-r--r-- | src/std_names.ads | 3 |
2 files changed, 3 insertions, 1 deletions
diff --git a/src/std_names.adb b/src/std_names.adb index 245c8a1a9..cf3ffeef5 100644 --- a/src/std_names.adb +++ b/src/std_names.adb @@ -687,6 +687,7 @@ package body Std_Names is Def ("gclk", Name_Gclk); Def ("loc", Name_Loc); Def ("keep", Name_Keep); + Def ("syn_black_box", Name_Syn_Black_Box); -- Verilog directives Def ("define", Name_Define); diff --git a/src/std_names.ads b/src/std_names.ads index 5fc5bf919..f1165488b 100644 --- a/src/std_names.ads +++ b/src/std_names.ads @@ -772,7 +772,8 @@ package Std_Names is Name_Gclk : constant Name_Id := Name_First_Synthesis + 004; Name_Loc : constant Name_Id := Name_First_Synthesis + 005; Name_Keep : constant Name_Id := Name_First_Synthesis + 006; - Name_Last_Synthesis : constant Name_Id := Name_Keep; + Name_Syn_Black_Box : constant Name_Id := Name_First_Synthesis + 007; + Name_Last_Synthesis : constant Name_Id := Name_Syn_Black_Box; -- Verilog Directives. Name_First_Directive : constant Name_Id := Name_Last_Synthesis + 1; |