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-rw-r--r--src/vhdl/translate/trans-chap14.adb2
-rw-r--r--src/vhdl/translate/trans-chap2.adb4
-rw-r--r--src/vhdl/translate/trans-chap3.adb24
-rw-r--r--src/vhdl/translate/trans-chap6.adb10
-rw-r--r--src/vhdl/translate/trans-chap7.adb14
-rw-r--r--src/vhdl/translate/trans-chap8.adb4
-rw-r--r--src/vhdl/translate/trans-chap9.adb4
7 files changed, 31 insertions, 31 deletions
diff --git a/src/vhdl/translate/trans-chap14.adb b/src/vhdl/translate/trans-chap14.adb
index e95afb5c4..4618edcb1 100644
--- a/src/vhdl/translate/trans-chap14.adb
+++ b/src/vhdl/translate/trans-chap14.adb
@@ -577,7 +577,7 @@ package body Trans.Chap14 is
Info : Type_Info_Acc;
Var : O_Dnode;
Data : Last_Time_Data;
- Right_Bound : Iir_Int64;
+ Right_Bound : Int64;
If_Blk : O_If_Block;
begin
Name := Chap6.Translate_Name (Prefix, Mode_Signal);
diff --git a/src/vhdl/translate/trans-chap2.adb b/src/vhdl/translate/trans-chap2.adb
index 7d32e50f6..5cbf85e62 100644
--- a/src/vhdl/translate/trans-chap2.adb
+++ b/src/vhdl/translate/trans-chap2.adb
@@ -1455,7 +1455,7 @@ package body Trans.Chap2 is
| Type_Iir_Constraint
| Type_Iir_Mode
| Type_Iir_Index32
- | Type_Iir_Int64
+ | Type_Int64
| Type_Boolean
| Type_Iir_Staticness
| Type_Iir_All_Sensitized
@@ -1467,7 +1467,7 @@ package body Trans.Chap2 is
| Type_Iir_Direction
| Type_Iir_Int32
| Type_Int32
- | Type_Iir_Fp64
+ | Type_Fp64
| Type_Token_Type
| Type_Name_Id =>
null;
diff --git a/src/vhdl/translate/trans-chap3.adb b/src/vhdl/translate/trans-chap3.adb
index 971d52b31..8c3021d43 100644
--- a/src/vhdl/translate/trans-chap3.adb
+++ b/src/vhdl/translate/trans-chap3.adb
@@ -340,7 +340,7 @@ package body Trans.Chap3 is
St : constant Iir :=
Get_Subtype_Definition (Get_Type_Declarator (Def));
L, H : Iir;
- Lv, Hv : Iir_Int64;
+ Lv, Hv : Int64;
begin
Get_Low_High_Limit (Get_Range_Constraint (St), L, H);
Lv := Get_Value (L);
@@ -983,12 +983,12 @@ package body Trans.Chap3 is
-- Get the length of DEF, ie the number of elements.
-- If the length is not statically defined, returns -1.
function Get_Array_Subtype_Length (Def : Iir_Array_Subtype_Definition)
- return Iir_Int64
+ return Int64
is
Indexes_List : constant Iir_Flist := Get_Index_Subtype_List (Def);
Index : Iir;
- Idx_Len : Iir_Int64;
- Len : Iir_Int64;
+ Idx_Len : Int64;
+ Len : Int64;
begin
-- Check if the bounds of the array are locally static.
Len := 1;
@@ -1059,7 +1059,7 @@ package body Trans.Chap3 is
Info : constant Type_Info_Acc := Get_Info (Def);
Pinfo : constant Type_Info_Acc := Get_Info (Parent_Type);
- Len : Iir_Int64;
+ Len : Int64;
Id : O_Ident;
El_Constrained : Boolean;
@@ -2068,24 +2068,24 @@ package body Trans.Chap3 is
end;
when Type_Mode_I64 =>
declare
- V : Iir_Int64;
+ V : Int64;
begin
V := Get_Value (Lit);
if Is_Hi then
- return V = Iir_Int64'Last;
+ return V = Int64'Last;
else
- return V = Iir_Int64'First;
+ return V = Int64'First;
end if;
end;
when Type_Mode_P64 =>
declare
- V : Iir_Int64;
+ V : Int64;
begin
V := Get_Physical_Value (Lit);
if Is_Hi then
- return V = Iir_Int64'Last;
+ return V = Int64'Last;
else
- return V = Iir_Int64'First;
+ return V = Int64'First;
end if;
end;
when Type_Mode_F64 =>
@@ -2657,7 +2657,7 @@ package body Trans.Chap3 is
Indexes_List : constant Iir_Flist := Get_Index_Subtype_List (Atype);
Nbr_Dim : constant Natural := Get_Nbr_Elements (Indexes_List);
Index : Iir;
- Val : Iir_Int64;
+ Val : Int64;
Rng : Iir;
begin
Val := 1;
diff --git a/src/vhdl/translate/trans-chap6.adb b/src/vhdl/translate/trans-chap6.adb
index 9d0da87c8..a277d452b 100644
--- a/src/vhdl/translate/trans-chap6.adb
+++ b/src/vhdl/translate/trans-chap6.adb
@@ -310,8 +310,8 @@ package body Trans.Chap6 is
Cond2 : O_Enode;
Index : O_Enode;
Index_Base_Type : Iir;
- V : Iir_Int64;
- B : Iir_Int64;
+ V : Int64;
+ B : Int64;
begin
B := Eval_Pos (Get_Left_Limit (Index_Range));
if Get_Expr_Staticness (Expr) = Locally then
@@ -558,9 +558,9 @@ package body Trans.Chap6 is
Slice_Index_Type : constant Iir := Get_Index_Type (Slice_Type, 0);
Slice_Range : constant Iir :=
Get_Range_Constraint (Slice_Index_Type);
- Prefix_Left, Slice_Left : Iir_Int64;
- Off : Iir_Int64;
- Slice_Length : Iir_Int64;
+ Prefix_Left, Slice_Left : Int64;
+ Off : Int64;
+ Slice_Length : Int64;
begin
Prefix_Left := Eval_Pos (Get_Left_Limit (Index_Range));
Slice_Left := Eval_Pos (Get_Left_Limit (Slice_Range));
diff --git a/src/vhdl/translate/trans-chap7.adb b/src/vhdl/translate/trans-chap7.adb
index 98cc8894e..9d1e0796c 100644
--- a/src/vhdl/translate/trans-chap7.adb
+++ b/src/vhdl/translate/trans-chap7.adb
@@ -199,7 +199,7 @@ package body Trans.Chap7 is
Index_Type : constant Iir :=
Get_Index_Type (Aggr_Type, Dim - 1);
Index_Range : constant Iir := Eval_Static_Range (Index_Type);
- Len : constant Iir_Int64 :=
+ Len : constant Int64 :=
Eval_Discrete_Range_Length (Index_Range);
Assocs : constant Iir := Get_Association_Choices_Chain (Aggr);
Vect : Iir_Array (0 .. Integer (Len - 1));
@@ -1229,7 +1229,7 @@ package body Trans.Chap7 is
Expr_Type : constant Iir := Get_Return_Type (Concat_Imp);
Index_Type : constant Iir := Get_Index_Type (Expr_Type, 0);
Info : constant Type_Info_Acc := Get_Info (Expr_Type);
- Static_Length : Iir_Int64 := 0;
+ Static_Length : Int64 := 0;
Nbr_Dyn_Expr : Natural := 0;
type Handle_Acc is access procedure (E : Iir);
@@ -2971,7 +2971,7 @@ package body Trans.Chap7 is
-- Assign EXPR to current position (defined by index VAR_INDEX), and
-- update VAR_INDEX. Handles sub-aggregates.
- procedure Do_Assign (Assoc : Iir; Expr : Iir; Assoc_Len : out Iir_Int64)
+ procedure Do_Assign (Assoc : Iir; Expr : Iir; Assoc_Len : out Int64)
is
Dest : Mnode;
begin
@@ -3008,7 +3008,7 @@ package body Trans.Chap7 is
is
P : Natural;
El : Iir;
- Assoc_Len : Iir_Int64;
+ Assoc_Len : Int64;
begin
-- First, assign positionnal association.
-- FIXME: count the number of positionnal association and generate
@@ -3072,7 +3072,7 @@ package body Trans.Chap7 is
procedure Translate_Array_Aggregate_Gen_Named
is
El : Iir;
- Assoc_Len : Iir_Int64;
+ Assoc_Len : Int64;
begin
El := Get_Association_Choices_Chain (Aggr);
@@ -3525,7 +3525,7 @@ package body Trans.Chap7 is
is
Aggr_Type : constant Iir := Get_Type (Aggr);
Assoc : Iir;
- Static_Len : Iir_Int64;
+ Static_Len : Int64;
Var_Len : O_Dnode;
Expr_Type : Iir;
Range_Type : Iir;
@@ -4217,7 +4217,7 @@ package body Trans.Chap7 is
declare
Otype : constant O_Tnode :=
Get_Ortho_Type (Expr_Type, Mode_Value);
- Val : Iir_Int64;
+ Val : Int64;
begin
-- Get the value now, as it may generate a constraint_error.
Val := Get_Physical_Value (Expr);
diff --git a/src/vhdl/translate/trans-chap8.adb b/src/vhdl/translate/trans-chap8.adb
index 79b05a055..427a30464 100644
--- a/src/vhdl/translate/trans-chap8.adb
+++ b/src/vhdl/translate/trans-chap8.adb
@@ -1206,7 +1206,7 @@ package body Trans.Chap8 is
Expr : constant Iir := Get_Expression (Stmt);
Expr_Type : Iir;
Base_Type : Iir;
- Sel_Length : Iir_Int64;
+ Sel_Length : Int64;
Cond : O_Enode;
begin
-- Translate into if/elsif statements.
@@ -1294,7 +1294,7 @@ package body Trans.Chap8 is
-- Number of associations.
Nbr_Assocs : Natural;
- Sel_Length : Iir_Int64;
+ Sel_Length : Int64;
-- Dichotomy table (table of choices).
String_Type : O_Tnode;
diff --git a/src/vhdl/translate/trans-chap9.adb b/src/vhdl/translate/trans-chap9.adb
index 58e0d6dcb..92ed100d5 100644
--- a/src/vhdl/translate/trans-chap9.adb
+++ b/src/vhdl/translate/trans-chap9.adb
@@ -1351,7 +1351,7 @@ package body Trans.Chap9 is
| Type_Iir_Constraint
| Type_Iir_Mode
| Type_Iir_Index32
- | Type_Iir_Int64
+ | Type_Int64
| Type_Boolean
| Type_Iir_Staticness
| Type_Iir_All_Sensitized
@@ -1363,7 +1363,7 @@ package body Trans.Chap9 is
| Type_Iir_Direction
| Type_Iir_Int32
| Type_Int32
- | Type_Iir_Fp64
+ | Type_Fp64
| Type_Token_Type
| Type_Name_Id =>
null;