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-rw-r--r--src/vhdl/translate/trans-chap8.adb9
1 files changed, 4 insertions, 5 deletions
diff --git a/src/vhdl/translate/trans-chap8.adb b/src/vhdl/translate/trans-chap8.adb
index a4416f068..493f2336e 100644
--- a/src/vhdl/translate/trans-chap8.adb
+++ b/src/vhdl/translate/trans-chap8.adb
@@ -907,12 +907,12 @@ package body Trans.Chap8 is
procedure Translate_Variable_Rec_Aggr
(Targ : Iir_Aggregate; Targ_Type : Iir; Val : Mnode)
is
+ El_List : constant Iir_Flist :=
+ Get_Elements_Declaration_List (Get_Base_Type (Targ_Type));
Aggr_El : Iir;
- El_List : Iir_List;
El_Index : Natural;
Elem : Iir;
begin
- El_List := Get_Elements_Declaration_List (Get_Base_Type (Targ_Type));
El_Index := 0;
Aggr_El := Get_Association_Choices_Chain (Targ);
while Aggr_El /= Null_Iir loop
@@ -3943,13 +3943,12 @@ package body Trans.Chap8 is
procedure Translate_Signal_Target_Record_Aggr
(Aggr : Mnode; Target : Iir; Target_Type : Iir)
is
+ El_List : constant Iir_Flist :=
+ Get_Elements_Declaration_List (Get_Base_Type (Target_Type));
Aggr_El : Iir;
- El_List : Iir_List;
El_Index : Natural;
Element : Iir_Element_Declaration;
begin
- El_List := Get_Elements_Declaration_List
- (Get_Base_Type (Target_Type));
El_Index := 0;
Aggr_El := Get_Association_Choices_Chain (Target);
while Aggr_El /= Null_Iir loop