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Diffstat (limited to 'src/vhdl/translate/trans-chap12.ads')
| -rw-r--r-- | src/vhdl/translate/trans-chap12.ads | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/vhdl/translate/trans-chap12.ads b/src/vhdl/translate/trans-chap12.ads index 7e6231638..23abea998 100644 --- a/src/vhdl/translate/trans-chap12.ads +++ b/src/vhdl/translate/trans-chap12.ads @@ -20,8 +20,12 @@ package Trans.Chap12 is -- Generate ortho declarations for elaboration. procedure Gen_Elab_Decls; + -- Generate ortho code to elaborate declaration of the top unit. procedure Call_Elab_Decls (Arch : Iir; Arch_Instance : O_Enode); + -- Write to file FILELIST all the files that are needed to link the design. + procedure Write_File_List (Filelist : String); + -- Primary unit + secondary unit (architecture name which may be null) -- to elaborate. procedure Elaborate (Primary : String; |