1 files changed, 6 insertions, 8 deletions
diff --git a/src/ghdldrv/ghdlsimul.adb b/src/ghdldrv/ghdlsimul.adb
index 259a3dc57..468c2253c 100644
--- a/src/ghdldrv/ghdlsimul.adb
+++ b/src/ghdldrv/ghdlsimul.adb
@@ -45,13 +45,12 @@ with Elab.Vhdl_Context;
 with Elab.Vhdl_Debug;
 with Elab.Vhdl_Insts;
 with Elab.Debugger;
+
 with Synth.Flags;
 with Simul.Vhdl_Elab;
 with Simul.Vhdl_Simul;
 
 package body Ghdlsimul is
-   Flag_Interractive : Boolean := False;
-
    procedure Compile_Init (Analyze_Only : Boolean) is
    begin
       Common_Compile_Init (Analyze_Only);
@@ -65,6 +64,7 @@ package body Ghdlsimul is
       --  The design is always analyzed in whole.
       Flags.Flag_Whole_Analyze := True;
       Vhdl.Canon.Canon_Flag_Add_Labels := True;
+      Vhdl.Canon.Canon_Flag_Add_Suspend_State := True;
 
       Vhdl.Annotations.Flag_Synthesis := True;
 
@@ -101,10 +101,6 @@ package body Ghdlsimul is
       Simul.Vhdl_Elab.Gather_Processes (Inst);
       Simul.Vhdl_Elab.Elab_Processes;
 
-      if Flag_Interractive then
-         Elab.Debugger.Debug_Elab (Inst);
-      end if;
-
       if False then
          Elab.Vhdl_Debug.Disp_Hierarchy (Inst, False, True);
       end if;
@@ -174,6 +170,8 @@ package body Ghdlsimul is
       Flags.Flag_String (5) := Time_Resolution;
       Grtlink.Flag_String := Flags.Flag_String;
 
+      Synth.Flags.Severity_Level := Grt.Options.Severity_Level;
+
       Elaborate_Proc := Simul.Vhdl_Simul.Runtime_Elaborate'Access;
       Simul.Vhdl_Simul.Simulation;
 
@@ -189,11 +187,11 @@ package body Ghdlsimul is
    is
    begin
       if Option = "--debug" or Option = "-g" then
-         Synth.Flags.Flag_Debug_Enable := True;
+         Elab.Debugger.Flag_Debug_Enable := True;
       elsif Option = "-t" then
          Synth.Flags.Flag_Trace_Statements := True;
       elsif Option = "-i" then
-         Flag_Interractive := True;
+         Simul.Vhdl_Simul.Flag_Interractive := True;
       else
          return False;
       end if;