diff options
Diffstat (limited to 'pyGHDL')
| -rw-r--r-- | pyGHDL/dom/Attribute.py | 4 | ||||
| -rw-r--r-- | pyGHDL/dom/Concurrent.py | 32 | ||||
| -rw-r--r-- | pyGHDL/dom/DesignUnit.py | 8 | ||||
| -rw-r--r-- | pyGHDL/dom/Expression.py | 6 | ||||
| -rw-r--r-- | pyGHDL/dom/Sequential.py | 19 | ||||
| -rw-r--r-- | pyGHDL/dom/Symbol.py | 72 | ||||
| -rw-r--r-- | pyGHDL/dom/_Translate.py | 29 | ||||
| -rw-r--r-- | pyGHDL/dom/_Utils.py | 47 |
8 files changed, 81 insertions, 136 deletions
diff --git a/pyGHDL/dom/Attribute.py b/pyGHDL/dom/Attribute.py index 7133c86a2..7dcb7b1ef 100644 --- a/pyGHDL/dom/Attribute.py +++ b/pyGHDL/dom/Attribute.py @@ -45,7 +45,7 @@ from pyGHDL.libghdl.vhdl import nodes from pyGHDL.libghdl.vhdl.tokens import Tok from pyGHDL.dom import DOMMixin, Position, DOMException, Expression from pyGHDL.dom._Utils import GetNameOfNode, GetIirKindOfNode, GetDocumentationOfNode -from pyGHDL.dom._Translate import GetNameFromNode, GetExpressionFromNode +from pyGHDL.dom._Translate import GetName, GetExpressionFromNode from pyGHDL.dom.Names import SimpleName from pyGHDL.dom.Symbol import SimpleSubtypeSymbol @@ -109,7 +109,7 @@ class AttributeSpecification(VHDLModel_AttributeSpecification, DOMMixin): @classmethod def parse(cls, attributeNode: Iir) -> "AttributeSpecification": attributeDesignator = nodes.Get_Attribute_Designator(attributeNode) - attributeName = GetNameFromNode(attributeDesignator) + attributeName = GetName(attributeDesignator) documentation = GetDocumentationOfNode(attributeNode) names = [] diff --git a/pyGHDL/dom/Concurrent.py b/pyGHDL/dom/Concurrent.py index 3b3c06f2e..71ee634cc 100644 --- a/pyGHDL/dom/Concurrent.py +++ b/pyGHDL/dom/Concurrent.py @@ -70,12 +70,6 @@ from pyVHDLModel.Concurrent import ( from pyGHDL.libghdl import Iir, utils from pyGHDL.libghdl.vhdl import nodes from pyGHDL.dom import DOMMixin, DOMException, Position -from pyGHDL.dom._Utils import ( - GetNameOfNode, - GetEntityInstantiationSymbol, - GetComponentInstantiationSymbol, - GetConfigurationInstantiationSymbol, -) from pyGHDL.dom.Range import Range from pyGHDL.dom.Symbol import ( ArchitectureSymbol, @@ -146,7 +140,7 @@ class EntityInstantiation(VHDLModel_EntityInstantiation, DOMMixin): @classmethod def parse(cls, instantiationNode: Iir, instantiatedUnit: Iir, label: str) -> "EntityInstantiation": - from pyGHDL.dom._Translate import GetGenericMapAspect, GetPortMapAspect + from pyGHDL.dom._Translate import GetName, GetGenericMapAspect, GetPortMapAspect entityId = nodes.Get_Entity_Name(instantiatedUnit) entitySymbol = GetEntityInstantiationSymbol(entityId) @@ -154,7 +148,7 @@ class EntityInstantiation(VHDLModel_EntityInstantiation, DOMMixin): architectureSymbol = None architectureId = nodes.Get_Architecture(instantiatedUnit) if architectureId != nodes.Null_Iir: - architectureSymbol = ArchitectureSymbol(GetNameOfNode(architectureId), entitySymbol) + architectureSymbol = ArchitectureSymbol(GetName(architectureId), entitySymbol) genericAssociations = GetGenericMapAspect(nodes.Get_Generic_Map_Aspect_Chain(instantiationNode)) portAssociations = GetPortMapAspect(nodes.Get_Port_Map_Aspect_Chain(instantiationNode)) @@ -230,13 +224,13 @@ class ProcessStatement(VHDLModel_ProcessStatement, DOMMixin): @classmethod def parse(cls, processNode: Iir, label: str, hasSensitivityList: bool) -> "ProcessStatement": - from pyGHDL.dom._Translate import GetDeclaredItemsFromChainedNodes, GetSequentialStatementsFromChainedNodes + from pyGHDL.dom._Translate import GetName, GetDeclaredItemsFromChainedNodes, GetSequentialStatementsFromChainedNodes sensitivityList = None if hasSensitivityList: sensitivityList = [] for item in utils.list_iter(nodes.Get_Sensitivity_List(processNode)): - sensitivityList.append(GetNameOfNode(item)) + sensitivityList.append(GetName(item)) declaredItems = GetDeclaredItemsFromChainedNodes(nodes.Get_Declaration_Chain(processNode), "process", label) statements = GetSequentialStatementsFromChainedNodes( @@ -490,7 +484,7 @@ class CaseGenerateStatement(VHDLModel_CaseGenerateStatement, DOMMixin): from pyGHDL.dom._Translate import ( GetExpressionFromNode, GetRangeFromNode, - GetNameFromNode, + GetName, ) expression = GetExpressionFromNode(nodes.Get_Expression(generateNode)) @@ -524,7 +518,7 @@ class CaseGenerateStatement(VHDLModel_CaseGenerateStatement, DOMMixin): nodes.Iir_Kind.Attribute_Name, nodes.Iir_Kind.Parenthesis_Name, ): - rng = GetNameFromNode(choiceRange) + rng = GetName(choiceRange) else: pos = Position.parse(alternative) raise DOMException( @@ -585,11 +579,11 @@ class ForGenerateStatement(VHDLModel_ForGenerateStatement, DOMMixin): GetDeclaredItemsFromChainedNodes, GetConcurrentStatementsFromChainedNodes, GetRangeFromNode, - GetNameFromNode, + GetName, ) spec = nodes.Get_Parameter_Specification(generateNode) - loopIndex = GetNameOfNode(spec) + loopIndex = GetName(spec) discreteRange = nodes.Get_Discrete_Range(spec) rangeKind = GetIirKindOfNode(discreteRange) @@ -599,7 +593,7 @@ class ForGenerateStatement(VHDLModel_ForGenerateStatement, DOMMixin): nodes.Iir_Kind.Attribute_Name, nodes.Iir_Kind.Parenthesis_Name, ): - rng = GetNameFromNode(discreteRange) + rng = GetName(discreteRange) else: pos = Position.parse(generateNode) raise DOMException( @@ -651,10 +645,10 @@ class ConcurrentSimpleSignalAssignment(VHDLModel_ConcurrentSimpleSignalAssignmen @classmethod def parse(cls, assignmentNode: Iir, label: str) -> "ConcurrentSimpleSignalAssignment": - from pyGHDL.dom._Translate import GetNameFromNode + from pyGHDL.dom._Translate import GetName target = nodes.Get_Target(assignmentNode) - targetName = GetNameFromNode(target) + targetName = GetName(target) waveform = [] for wave in utils.chain_iter(nodes.Get_Waveform_Chain(assignmentNode)): @@ -677,12 +671,12 @@ class ConcurrentProcedureCall(VHDLModel_ConcurrentProcedureCall, DOMMixin): @classmethod def parse(cls, concurrentCallNode: Iir, label: str) -> "ConcurrentProcedureCall": - from pyGHDL.dom._Translate import GetNameFromNode, GetParameterMapAspect + from pyGHDL.dom._Translate import GetName, GetParameterMapAspect callNode = nodes.Get_Procedure_Call(concurrentCallNode) prefix = nodes.Get_Prefix(callNode) - procedureName = GetNameFromNode(prefix) + procedureName = GetName(prefix) parameterAssociations = GetParameterMapAspect(nodes.Get_Parameter_Association_Chain(callNode)) return cls(concurrentCallNode, label, procedureName, parameterAssociations) diff --git a/pyGHDL/dom/DesignUnit.py b/pyGHDL/dom/DesignUnit.py index 079364742..6484d1532 100644 --- a/pyGHDL/dom/DesignUnit.py +++ b/pyGHDL/dom/DesignUnit.py @@ -63,8 +63,8 @@ from pyGHDL.libghdl import utils from pyGHDL.libghdl._types import Iir from pyGHDL.libghdl.vhdl import nodes from pyGHDL.dom import DOMMixin, Position, DOMException -from pyGHDL.dom._Utils import GetNameOfNode, GetDocumentationOfNode, GetPackageMemberSymbol, GetContextSymbol -from pyGHDL.dom._Translate import GetGenericsFromChainedNodes, GetPortsFromChainedNodes +from pyGHDL.dom._Utils import GetNameOfNode, GetDocumentationOfNode, GetPackageMemberSymbol +from pyGHDL.dom._Translate import GetGenericsFromChainedNodes, GetPortsFromChainedNodes, GetName from pyGHDL.dom._Translate import GetDeclaredItemsFromChainedNodes, GetConcurrentStatementsFromChainedNodes from pyGHDL.dom.Symbol import EntitySymbol, ContextReferenceSymbol, LibraryReferenceSymbol, PackageSymbol @@ -158,7 +158,7 @@ class Architecture(VHDLModel_Architecture, DOMMixin): name = GetNameOfNode(architectureNode) documentation = GetDocumentationOfNode(architectureNode) entityNameNode = nodes.Get_Entity_Name(architectureNode) - entitySymbol = EntitySymbol(entityNameNode, GetNameOfNode(entityNameNode)) + entitySymbol = EntitySymbol(entityNameNode, GetName(entityNameNode)) declaredItems = GetDeclaredItemsFromChainedNodes( nodes.Get_Declaration_Chain(architectureNode), "architecture", name ) @@ -241,7 +241,7 @@ class PackageBody(VHDLModel_PackageBody, DOMMixin): @classmethod def parse(cls, packageBodyNode: Iir, contextItems: Iterable[VHDLModel_ContextUnion]): - packageName = GetNameOfNode(packageBodyNode) + packageName = GetName(packageBodyNode) packageSymbol = PackageSymbol(packageBodyNode, packageName) documentation = GetDocumentationOfNode(packageBodyNode) declaredItems = GetDeclaredItemsFromChainedNodes( diff --git a/pyGHDL/dom/Expression.py b/pyGHDL/dom/Expression.py index 608801af6..0d8dbfba7 100644 --- a/pyGHDL/dom/Expression.py +++ b/pyGHDL/dom/Expression.py @@ -488,7 +488,7 @@ class Aggregate(VHDLModel_Aggregate, DOMMixin): from pyGHDL.dom._Translate import ( GetExpressionFromNode, GetRangeFromNode, - GetNameFromNode, + GetName, ) choices = [] @@ -512,7 +512,7 @@ class Aggregate(VHDLModel_Aggregate, DOMMixin): nodes.Iir_Kind.Attribute_Name, nodes.Iir_Kind.Parenthesis_Name, ): - rng = GetNameFromNode(choiceRange) + rng = GetName(choiceRange) else: pos = Position.parse(item) raise DOMException( @@ -521,7 +521,7 @@ class Aggregate(VHDLModel_Aggregate, DOMMixin): choices.append(RangedAggregateElement(item, rng, value)) elif kind == nodes.Iir_Kind.Choice_By_Name: - name = GetNameFromNode(nodes.Get_Choice_Name(item)) + name = GetName(nodes.Get_Choice_Name(item)) symbol = Symbol(item, name) choices.append(NamedAggregateElement(item, symbol, value)) elif kind == nodes.Iir_Kind.Choice_By_Others: diff --git a/pyGHDL/dom/Sequential.py b/pyGHDL/dom/Sequential.py index d1396941e..f289ae969 100644 --- a/pyGHDL/dom/Sequential.py +++ b/pyGHDL/dom/Sequential.py @@ -58,7 +58,6 @@ from pyVHDLModel.Sequential import SequentialAssertStatement as VHDLModel_Sequen from pyGHDL.libghdl import Iir, utils from pyGHDL.libghdl.vhdl import nodes from pyGHDL.dom import DOMMixin, Position, DOMException -from pyGHDL.dom._Utils import GetNameOfNode from pyGHDL.dom.Range import Range from pyGHDL.dom.Concurrent import WaveformElement, ParameterAssociationItem # TODO: move out from concurrent? @@ -247,7 +246,7 @@ class CaseStatement(VHDLModel_CaseStatement, DOMMixin): from pyGHDL.dom._Translate import ( GetExpressionFromNode, GetRangeFromNode, - GetNameFromNode, + GetName, ) expression = GetExpressionFromNode(nodes.Get_Expression(caseNode)) @@ -281,7 +280,7 @@ class CaseStatement(VHDLModel_CaseStatement, DOMMixin): nodes.Iir_Kind.Attribute_Name, nodes.Iir_Kind.Parenthesis_Name, ): - rng = GetNameFromNode(choiceRange) + rng = GetName(choiceRange) else: pos = Position.parse(alternative) raise DOMException( @@ -340,11 +339,11 @@ class ForLoopStatement(VHDLModel_ForLoopStatement, DOMMixin): from pyGHDL.dom._Translate import ( GetSequentialStatementsFromChainedNodes, GetRangeFromNode, - GetNameFromNode, + GetName, ) spec = nodes.Get_Parameter_Specification(loopNode) - loopIndex = GetNameOfNode(spec) + loopIndex = GetName(spec) discreteRange = nodes.Get_Discrete_Range(spec) rangeKind = GetIirKindOfNode(discreteRange) @@ -354,7 +353,7 @@ class ForLoopStatement(VHDLModel_ForLoopStatement, DOMMixin): nodes.Iir_Kind.Attribute_Name, nodes.Iir_Kind.Parenthesis_Name, ): - rng = GetNameFromNode(discreteRange) + rng = GetName(discreteRange) else: pos = Position.parse(loopNode) raise DOMException( @@ -381,10 +380,10 @@ class SequentialSimpleSignalAssignment(VHDLModel_SequentialSimpleSignalAssignmen @classmethod def parse(cls, assignmentNode: Iir, label: str = None) -> "SequentialSimpleSignalAssignment": - from pyGHDL.dom._Translate import GetNameFromNode + from pyGHDL.dom._Translate import GetName target = nodes.Get_Target(assignmentNode) - targetName = GetNameFromNode(target) + targetName = GetName(target) waveform = [] for wave in utils.chain_iter(nodes.Get_Waveform_Chain(assignmentNode)): @@ -407,12 +406,12 @@ class SequentialProcedureCall(VHDLModel_SequentialProcedureCall, DOMMixin): @classmethod def parse(cls, callNode: Iir, label: str) -> "SequentialProcedureCall": - from pyGHDL.dom._Translate import GetNameFromNode, GetParameterMapAspect + from pyGHDL.dom._Translate import GetName, GetParameterMapAspect cNode = nodes.Get_Procedure_Call(callNode) prefix = nodes.Get_Prefix(cNode) - procedureName = GetNameFromNode(prefix) + procedureName = GetName(prefix) parameterAssociations = GetParameterMapAspect(nodes.Get_Parameter_Association_Chain(cNode)) return cls(callNode, procedureName, parameterAssociations, label) diff --git a/pyGHDL/dom/Symbol.py b/pyGHDL/dom/Symbol.py index e62ec4137..7c29acf06 100644 --- a/pyGHDL/dom/Symbol.py +++ b/pyGHDL/dom/Symbol.py @@ -61,88 +61,72 @@ from pyGHDL.dom.Range import Range @export class LibraryReferenceSymbol(VHDLModel_LibraryReferenceSymbol, DOMMixin): @InheritDocString(VHDLModel_LibraryReferenceSymbol) - def __init__(self, identifierNode: Iir, identifier: str): - super().__init__(identifier) + def __init__(self, identifierNode: Iir, name: Name): + super().__init__(name) DOMMixin.__init__(self, identifierNode) @export class PackageReferenceSymbol(VHDLModel_PackageReferenceSymbol, DOMMixin): @InheritDocString(VHDLModel_PackageReferenceSymbol) - def __init__(self, identifierNode: Iir, identifier: str, prefix: LibraryReferenceSymbol): - super().__init__(identifier, prefix) - DOMMixin.__init__(self, identifierNode) - - -@export -class PackageMembersReferenceSymbol(VHDLModel_PackageMembersReferenceSymbol, DOMMixin): - @InheritDocString(VHDLModel_PackageMembersReferenceSymbol) - def __init__(self, identifierNode: Iir, identifier: str, prefix: PackageReferenceSymbol): - super().__init__(identifier, prefix) - DOMMixin.__init__(self, identifierNode) - - -@export -class AllPackageMembersReferenceSymbol(VHDLModel_AllPackageMembersReferenceSymbol, DOMMixin): - @InheritDocString(VHDLModel_AllPackageMembersReferenceSymbol) - def __init__(self, identifierNode: Iir, prefix: PackageReferenceSymbol): - super().__init__(prefix) + def __init__(self, identifierNode: Iir, name: Name): + super().__init__(name) DOMMixin.__init__(self, identifierNode) @export class ContextReferenceSymbol(VHDLModel_ContextReferenceSymbol, DOMMixin): @InheritDocString(VHDLModel_ContextReferenceSymbol) - def __init__(self, identifierNode: Iir, identifier: str, prefix: LibraryReferenceSymbol): - super().__init__(identifier, prefix) + def __init__(self, identifierNode: Iir, name: Name): + super().__init__(name) DOMMixin.__init__(self, identifierNode) @export class EntityInstantiationSymbol(VHDLModel_EntityInstantiationSymbol, DOMMixin): @InheritDocString(VHDLModel_EntityInstantiationSymbol) - def __init__(self, identifierNode: Iir, identifier: str, prefix: LibraryReferenceSymbol): - super().__init__(identifier, prefix) + def __init__(self, identifierNode: Iir, name: Name): + super().__init__(name) DOMMixin.__init__(self, identifierNode) @export class ComponentInstantiationSymbol(VHDLModel_ComponentInstantiationSymbol, DOMMixin): @InheritDocString(VHDLModel_ComponentInstantiationSymbol) - def __init__(self, identifierNode: Iir, identifier: str): - super().__init__(identifier) + def __init__(self, identifierNode: Iir, name: Name): + super().__init__(name) DOMMixin.__init__(self, identifierNode) @export class ConfigurationInstantiationSymbol(VHDLModel_ConfigurationInstantiationSymbol, DOMMixin): @InheritDocString(VHDLModel_ConfigurationInstantiationSymbol) - def __init__(self, identifierNode: Iir, identifier: str): - super().__init__(identifier) + def __init__(self, identifierNode: Iir, name: Name): + super().__init__(name) DOMMixin.__init__(self, identifierNode) @export class EntitySymbol(VHDLModel_EntitySymbol, DOMMixin): @InheritDocString(VHDLModel_EntitySymbol) - def __init__(self, identifierNode: Iir, identifier: str): - super().__init__(identifier) + def __init__(self, identifierNode: Iir, name: Name): + super().__init__(name) DOMMixin.__init__(self, identifierNode) @export class ArchitectureSymbol(VHDLModel_ArchitectureSymbol, DOMMixin): @InheritDocString(VHDLModel_ArchitectureSymbol) - def __init__(self, identifierNode: Iir, identifier: str, prefix: EntitySymbol): - super().__init__(identifier, prefix) + def __init__(self, identifierNode: Iir, name: Name): + super().__init__(name) DOMMixin.__init__(self, identifierNode) @export class PackageSymbol(VHDLModel_PackageSymbol, DOMMixin): @InheritDocString(VHDLModel_PackageSymbol) - def __init__(self, identifierNode: Iir, identifier: str): - super().__init__(identifier) + def __init__(self, identifierNode: Iir, name: Name): + super().__init__(name) DOMMixin.__init__(self, identifierNode) @@ -184,29 +168,29 @@ class ConstrainedCompositeSubtypeSymbol(VHDLModel_ConstrainedCompositeSubtypeSym @export class SimpleObjectOrFunctionCallSymbol(VHDLModel_SimpleObjectOrFunctionCallSymbol, DOMMixin): - def __init__(self, node: Iir, identifier: str): - super().__init__(identifier) + def __init__(self, node: Iir, name: Name): + super().__init__(name) DOMMixin.__init__(self, node) @classmethod def parse(cls, node: Iir): - from pyGHDL.dom._Translate import GetNameFromNode + from pyGHDL.dom._Translate import GetName - name = GetNameFromNode(node) + name = GetName(node) - return cls(node, str(name)) # XXX: hacked + return cls(node, name) @export class IndexedObjectOrFunctionCallSymbol(VHDLModel_IndexedObjectOrFunctionCallSymbol, DOMMixin): - def __init__(self, node: Iir, prefix: Name, indices: Iterable[ExpressionUnion]): - super().__init__(prefix, indices) + def __init__(self, node: Iir, name: Name): + super().__init__(name) DOMMixin.__init__(self, node) @classmethod def parse(cls, node: Iir): - from pyGHDL.dom._Translate import GetNameFromNode + from pyGHDL.dom._Translate import GetName - name = GetNameFromNode(node) + name = GetName(node) - return cls(node, name, []) + return cls(node, name) diff --git a/pyGHDL/dom/_Translate.py b/pyGHDL/dom/_Translate.py index 9ccc05158..8ab6283b2 100644 --- a/pyGHDL/dom/_Translate.py +++ b/pyGHDL/dom/_Translate.py @@ -166,26 +166,25 @@ from pyGHDL.dom.PSL import DefaultClock @export -def GetNameFromNode(node: Iir) -> Name: +def GetName(node: Iir) -> Name: kind = GetIirKindOfNode(node) if kind == nodes.Iir_Kind.Simple_Name: name = GetNameOfNode(node) return SimpleName(node, name) elif kind == nodes.Iir_Kind.Selected_Name: name = GetNameOfNode(node) - prefixName = GetNameFromNode(nodes.Get_Prefix(node)) + prefixName = GetName(nodes.Get_Prefix(node)) return SelectedName(node, name, prefixName) - elif kind == nodes.Iir_Kind.Attribute_Name: - name = GetNameOfNode(node) - prefixName = GetNameFromNode(nodes.Get_Prefix(node)) - return AttributeName(node, name, prefixName) elif kind == nodes.Iir_Kind.Parenthesis_Name: - prefixName = GetNameFromNode(nodes.Get_Prefix(node)) + prefixName = GetName(nodes.Get_Prefix(node)) associations = GetAssociations(node) - return ParenthesisName(node, prefixName, associations) + elif kind == nodes.Iir_Kind.Attribute_Name: + name = GetNameOfNode(node) + prefixName = GetName(nodes.Get_Prefix(node)) + return AttributeName(node, name, prefixName) elif kind == nodes.Iir_Kind.Selected_By_All_Name: - prefixName = GetNameFromNode(nodes.Get_Prefix(node)) + prefixName = GetName(nodes.Get_Prefix(node)) return AllName(node, prefixName) else: raise DOMException(f"Unknown name kind '{kind.name}'") @@ -227,7 +226,7 @@ def GetArrayConstraintsFromSubtypeIndication( nodes.Iir_Kind.Selected_Name, nodes.Iir_Kind.Attribute_Name, ): - constraints.append(GetNameFromNode(constraint)) + constraints.append(GetName(constraint)) else: position = Position.parse(constraint) raise DOMException( @@ -277,7 +276,7 @@ def GetAnonymousTypeFromNode(node: Iir) -> BaseType: return IntegerType(node, typeName, r) elif kind in (nodes.Iir_Kind.Attribute_Name, nodes.Iir_Kind.Parenthesis_Name): - n = GetNameFromNode(typeDefinition) + n = GetName(typeDefinition) return IntegerType(node, typeName, n) elif kind == nodes.Iir_Kind.Physical_Type_Definition: @@ -322,7 +321,7 @@ def GetSubtypeIndicationFromIndicationNode(subtypeIndicationNode: Iir, entity: s @export def GetSimpleTypeFromNode(subtypeIndicationNode: Iir) -> SimpleSubtypeSymbol: - subtypeName = GetNameFromNode(subtypeIndicationNode) + subtypeName = GetName(subtypeIndicationNode) return SimpleSubtypeSymbol(subtypeIndicationNode, str(subtypeName)) # XXX: hacked @@ -353,7 +352,7 @@ def GetCompositeConstrainedSubtypeFromNode( simpleTypeMark = SimpleName(typeMark, typeMarkName) constraints = GetArrayConstraintsFromSubtypeIndication(subtypeIndicationNode) - return ConstrainedCompositeSubtypeSymbol(subtypeIndicationNode, str(simpleTypeMark), constraints) # XXX: hacked + return ConstrainedCompositeSubtypeSymbol(subtypeIndicationNode, simpleTypeMark, constraints) @export @@ -609,7 +608,7 @@ def GetMapAspect(mapAspect: Iir, cls: Type, entity: str) -> Generator[Associatio if formalNode is nodes.Null_Iir: formal = None else: - formal = GetNameFromNode(formalNode) + formal = GetName(formalNode) actual = GetExpressionFromNode(nodes.Get_Actual(generic)) @@ -619,7 +618,7 @@ def GetMapAspect(mapAspect: Iir, cls: Type, entity: str) -> Generator[Associatio if formalNode is nodes.Null_Iir: formal = None else: - formal = GetNameFromNode(formalNode) + formal = GetName(formalNode) yield cls(generic, OpenName(generic), formal) else: diff --git a/pyGHDL/dom/_Utils.py b/pyGHDL/dom/_Utils.py index 7ab02ace9..5a9c1c135 100644 --- a/pyGHDL/dom/_Utils.py +++ b/pyGHDL/dom/_Utils.py @@ -35,23 +35,15 @@ from typing import Union from pyTooling.Decorators import export from pyVHDLModel.Base import Mode +from pyVHDLModel.Name import Name +from pyVHDLModel.Symbol import PackageMembersReferenceSymbol, AllPackageMembersReferenceSymbol from pyGHDL.libghdl import LibGHDLException, name_table, errorout_memory, files_map, file_comments from pyGHDL.libghdl._types import Iir from pyGHDL.libghdl.vhdl import nodes, utils from pyGHDL.libghdl.vhdl.nodes import Null_Iir from pyGHDL.dom import DOMException, Position -from pyGHDL.dom.Symbol import ( - LibraryReferenceSymbol, - PackageReferenceSymbol, - PackageMembersReferenceSymbol, - AllPackageMembersReferenceSymbol, - ContextReferenceSymbol, - EntityInstantiationSymbol, - ComponentInstantiationSymbol, - ConfigurationInstantiationSymbol, -) - +from pyGHDL.dom.Names import SelectedName, AllName, SimpleName __MODE_TRANSLATION = { nodes.Iir_Mode.In_Mode: Mode.In, @@ -172,35 +164,12 @@ def GetPackageSymbol(node: Iir) -> PackageReferenceSymbol: def GetPackageMemberSymbol( node: Iir, -) -> Union[PackageReferenceSymbol, PackageMembersReferenceSymbol, AllPackageMembersReferenceSymbol]: - kind = GetIirKindOfNode(node) - prefixName = GetPackageSymbol(nodes.Get_Prefix(node)) - if kind == nodes.Iir_Kind.Selected_Name: - name = GetNameOfNode(node) - return PackageMembersReferenceSymbol(node, name, prefixName) - elif kind == nodes.Iir_Kind.Selected_By_All_Name: - prefixName = GetPackageSymbol(nodes.Get_Prefix(node)) - return AllPackageMembersReferenceSymbol(node, prefixName) - else: - raise DOMException(f"{kind.name} at {Position.parse(node)}") - +) -> Union[PackageMembersReferenceSymbol, AllPackageMembersReferenceSymbol]: + from pyGHDL.dom._Translate import GetName -def GetContextSymbol(node: Iir) -> ContextReferenceSymbol: - kind = GetIirKindOfNode(node) - if kind == nodes.Iir_Kind.Selected_Name: - name = GetNameOfNode(node) - prefixName = GetLibrarySymbol(nodes.Get_Prefix(node)) - return ContextReferenceSymbol(node, name, prefixName) - else: - raise DOMException(f"{kind.name} at {Position.parse(node)}") - - -def GetEntityInstantiationSymbol(node: Iir) -> EntityInstantiationSymbol: - kind = GetIirKindOfNode(node) - if kind == nodes.Iir_Kind.Selected_Name: - name = GetNameOfNode(node) - prefixName = GetLibrarySymbol(nodes.Get_Prefix(node)) - return EntityInstantiationSymbol(node, name, prefixName) + name = GetName(node) + if isinstance(name, AllName): + return AllPackageMembersReferenceSymbol(name) else: raise DOMException(f"{kind.name} at {Position.parse(node)}") |