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-rw-r--r--pyGHDL/dom/DesignUnit.py4
1 files changed, 2 insertions, 2 deletions
diff --git a/pyGHDL/dom/DesignUnit.py b/pyGHDL/dom/DesignUnit.py
index 59b04a947..28a5dc0b6 100644
--- a/pyGHDL/dom/DesignUnit.py
+++ b/pyGHDL/dom/DesignUnit.py
@@ -48,7 +48,7 @@ from pyVHDLModel import (
LibraryClause as VHDLModel_LibraryClause,
UseClause as VHDLModel_UseClause,
ContextReference as VHDLModel_ContextReference,
- Name,
+ Name, ContextUnion,
)
from pyVHDLModel.SyntaxModel import (
Entity as VHDLModel_Entity,
@@ -295,7 +295,7 @@ class Context(VHDLModel_Context, DOMMixin):
self,
node: Iir,
identifier: str,
- references: Iterable[Union[LibraryClause, UseClause, ContextReference]] = None,
+ references: Iterable[ContextUnion] = None,
documentation: str = None,
):
super().__init__(identifier, references, documentation)