diff options
| -rw-r--r-- | src/vhdl/vhdl-ieee-std_logic_unsigned.adb | 16 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes.ads | 8 |
2 files changed, 24 insertions, 0 deletions
diff --git a/src/vhdl/vhdl-ieee-std_logic_unsigned.adb b/src/vhdl/vhdl-ieee-std_logic_unsigned.adb index 9fbdac603..5acf9ae4f 100644 --- a/src/vhdl/vhdl-ieee-std_logic_unsigned.adb +++ b/src/vhdl/vhdl-ieee-std_logic_unsigned.adb @@ -33,6 +33,18 @@ package body Vhdl.Ieee.Std_Logic_Unsigned is Arg_Int_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Eq_Int_Slv, others => Iir_Predefined_None); + Lt_Patterns : constant Binary_Pattern_Type := + (Arg_Slv_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Lt_Slv_Slv, + Arg_Slv_Int => Iir_Predefined_Ieee_Std_Logic_Unsigned_Lt_Slv_Int, + Arg_Int_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Lt_Int_Slv, + others => Iir_Predefined_None); + + Le_Patterns : constant Binary_Pattern_Type := + (Arg_Slv_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Le_Slv_Slv, + Arg_Slv_Int => Iir_Predefined_Ieee_Std_Logic_Unsigned_Le_Slv_Int, + Arg_Int_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Le_Int_Slv, + others => Iir_Predefined_None); + Add_Patterns : constant Binary_Pattern_Type := (Arg_Slv_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Slv, Arg_Slv_Int => Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Int, @@ -114,6 +126,10 @@ package body Vhdl.Ieee.Std_Logic_Unsigned is case Get_Identifier (Decl) is when Name_Op_Equality => Handle_Binary (Eq_Patterns); + when Name_Op_Less => + Handle_Binary (Lt_Patterns); + when Name_Op_Less_Equal => + Handle_Binary (Le_Patterns); when Name_Op_Plus => Handle_Binary (Add_Patterns); when others => diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index 2e9e8c049..ec354499d 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -4886,6 +4886,14 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Sl, Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Sl_Slv, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Lt_Slv_Slv, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Lt_Slv_Int, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Lt_Int_Slv, + + Iir_Predefined_Ieee_Std_Logic_Unsigned_Le_Slv_Slv, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Le_Slv_Int, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Le_Int_Slv, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Eq_Slv_Slv, Iir_Predefined_Ieee_Std_Logic_Unsigned_Eq_Slv_Int, Iir_Predefined_Ieee_Std_Logic_Unsigned_Eq_Int_Slv |