diff options
| -rw-r--r-- | testsuite/synth/issue1039/ent.vhdl | 25 | ||||
| -rwxr-xr-x | testsuite/synth/issue1039/testsuite.sh | 12 |
2 files changed, 37 insertions, 0 deletions
diff --git a/testsuite/synth/issue1039/ent.vhdl b/testsuite/synth/issue1039/ent.vhdl new file mode 100644 index 000000000..f600fcf8b --- /dev/null +++ b/testsuite/synth/issue1039/ent.vhdl @@ -0,0 +1,25 @@ +library ieee; +use ieee.std_logic_1164.all, + ieee.numeric_std.all; + +entity ent is + port ( + clk : in std_logic; + addr : in std_logic_vector(2 downto 0); + wr_data : in std_logic_vector(3 downto 0); + rd_data : out std_logic_vector(3 downto 0) + ); +end ent; + +architecture a of ent is + type ram_type is array (0 to 7) of std_logic_vector(3 downto 0); + signal ram : ram_type := (others => (others => '0')); +begin + process(clk) + begin + if rising_edge(clk) then + ram(to_integer(unsigned(addr))) <= wr_data; + rd_data <= ram(to_integer(unsigned(addr))); + end if; + end process; +end; diff --git a/testsuite/synth/issue1039/testsuite.sh b/testsuite/synth/issue1039/testsuite.sh new file mode 100755 index 000000000..bc454cfda --- /dev/null +++ b/testsuite/synth/issue1039/testsuite.sh @@ -0,0 +1,12 @@ +#! /bin/sh + +. ../../testenv.sh + +for t in ent; do + synth $t.vhdl -e $t > syn_$t.vhdl + analyze syn_$t.vhdl +done + +clean + +echo "Test successful" |